Download: SERVICE MANUAL CD RECEIVER KD-S735R

SERVICE MANUAL CD RECEIVER KD-S735R

Area Suffix E Continental Europe EX Central Europe 45Wx4

DISP MO RND

78910 11 12 RDS TP PTY SCM

COMPACT

DIGITAL AUDIO

TABLE OF CONTENTS

1 Important Safety Precautions ..1-2 2 Disassembly method ..1-4 3 Adjustment method ..1-11 4 Description of major ICs ..1-15

No.49762

COPYRIGHT © 2002 VICTOR COMPANY OF JAPAN, LTD. 2002/12,

SECTION 1 Important Safety Precautions

1.1 Safety Precautions ! Burrs formed during molding may be left over on some parts of the chassis. Therefore, pay attention to such burrs in the case of preforming repair of this system. ! Please use enough caution not to see the beam directly or touch it in case of an adjustment or operation check. 1-2, 1.2 Preventing static electricity Electrostatic discharge (ESD), which occurs when static electricity stored in the body, fabric, etc. is discharged, can destroy the laser diode in the traverse unit (optical pickup). Take care to prevent this when performing repairs. 1.2.1 Grounding to prevent damage by static electricity Static electricity in the work area can destroy the optical pickup (laser diode) in devices such as DVD players. Be careful to use proper grounding in the area where repairs are being performed. (1) Ground the workbench Ground the workbench by laying conductive material (such as a conductive sheet) or an iron plate over it before placing the traverse unit (optical pickup) on it. (2) Ground yourself Use an anti-static wrist strap to release any static electricity built up in your body. (caption) Anti-static wrist strap 1M Conductive material (conductive sheet) or iron plate (3) Handling the optical pickup • In order to maintain quality during transport and before installation, both sides of the laser diode on the replacement optical pickup are shorted. After replacement, return the shorted parts to their original condition. (Refer to the text.) • Do not use a tester to check the condition of the laser diode in the optical pickup. The tester's internal power source can easily destroy the laser diode. 1.3 Handling the traverse unit (optical pickup) (1) Do not subject the traverse unit (optical pickup) to strong shocks, as it is a sensitive, complex unit. (2) Cut off the shorted part of the flexible cable using nippers, etc. after replacing the optical pickup. For specific details, refer to the replacement procedure in the text. Remove the anti-static pin when replacing the traverse unit. Be careful not to take too long a time when attaching it to the connector. (3) Handle the flexible cable carefully as it may break when subjected to strong force. (4) I t is not possible to adjust the semi-fixed resistor that adjusts the laser power. Do not turn it. 1.4 Attention when traverse unit is decomposed *Please refer to "Disassembly method" in the text for the CD pickup unit. • Apply solder to the short land before the flexible wire is disconnected from the connector on the CD pickup unit. (If the flexible wire is disconnected without applying solder, the CDpickup may be destroyed by static electricity.) • In the assembly, be sure to remove solder from the short land after connecting the flexible wire. Damper bracket CD mechanism ass’y CD mechanism control board Front bracket FD screw Feed motor ass’y Soldering FD gear Pickup unit 1-3,

SECTION 2 Disassembly method

2.1 Main body 2.1.1 Removing the front panel assembly (See Fig.1) (1) Press the eject button in the lower right part of the front panel. Remove the front panel assembly from the body. Front panel assembly Eject button Fig.1 2.1.2 Removing the front chassis assembly (See Fig.2 and 3) • Prior to performing the following procedure, remove the front panel assembly. Tab a (1) Release the four joint tabs a on both sides of the front chassis assembly and remove the front chassis assembly toward the front. Tab a Front chassis assembly Fig.2 Heat sink Tab a Tab a Front chassis assembly Fig.3 1-4, 2.1.3 Removing the heat sink (See Fig.4) (1) Remove the three screws A on the left side of the body. Heat sink

A A

Fig.4 2.1.4 Removing the bottom cover (See Fig.5 and 6) • Prior to performing the following procedure, remove the front panel assembly, the front chassis assembly and the heat sink. Joints b (1) Turn over the body and unjoint the five joints b with the Bottom cover bottom cover and the body using a screwdriver. Joint b Joints b Rear panel Fig.5 Joints b Bottom cover Joint b Joints b Rear panel Fig.6 1-5, 2.1.5 Removing the main board (See Fig.7 and 8) CBC• Prior to performing the following procedure, remove the front panel assembly, the front chassis assembly, the heat sink and the bottom cover. (1) Remove the screw B, the two screws C and the three screws D attaching the rear bracket on the back of the D body. Remove the rear panel. D (2) Remove the two screws E attaching the main board on the bottom of the body. Disconnect connector CN501 on the main board in the direction of the arrow. Rear panel D Fig.7 Main board

E E

CN501 Fig.8 2.1.6 Removing the CD mechanism section (See Fig.9) • Prior to performing the following procedure, remove the front panel assembly, the front chassis assembly, the heat sink, the CD mechanism section bottom cover and the main board. F F (1) Remove the three screws F attaching the cassette mech- Top chassis anism section on the back of the top chassis.

F

Fig.9 1-6, 2.1.7 Removing the control switch board (See Fig.10 to 12) G G • Prior to performing the following procedure, remove the front panel assembly. (1) Remove the four screws G attaching the rear cover on the back of the front panel assembly. (2) Unjoint the ten joints c with the front panel and the rear cover. (3) Remove the control switch board on the back of the front panel

G Rear cover G

Fig.10 Joints c Front panel Joints c Joints c Rear cover Joints c Fig.11 Front panel Control switch board Fig.12 1-7, 2.2 CD Mechanism Assembly 2.2.1 Removing the CD mechanism control board 2.2.2 Removing the loading motor (See Fig.1 and 2) (See Fig.3 to 5) (1) Unsolder the part a and b on the CD mechanism control • Prior to performing the following procedure, remove the CD board. mechanism control board. (2) Remove the stator fixing the CD mechanism control board (1) Remove the two springs f attaching the CD mechanism and the damper bracket (To remove the stator smoothly, assembly and the front bracket. pick up the center part). (2) Remove the two screws B and the front bracket while (3) Remove the screw A attaching the CD mechanism control pulling the flame outward. board. (3) Remove the belt and the screw C from the loading motor. (4) Remove the CD mechanism control board in the direction of the arrow while releasing it from the two damper bracket CD mechanism control board slots d and the front bracket slot e. (5) Disconnect the flexible wire from connector on the pickup unit. ATTENTION: Turn the FD gear in the direction of the arrow to move the en- tire pickup unit to the appropriate position where the flexible wire of the CD mechanism unit can be disconnected easily. f f (Refer to Fig.2)

B

CD mechanism assembly Damper bracket

D D Ba

h h Loading motor Front bracket c Fig.3

D Front bracketPull outward Pull outward

d e CD mechanism Flame Front bracketAbcontrol board Fig.4 Fig.1 Loading motor Pickup unit Flexible wire

C

Shift the lock Belt Fig.5 FD gear Fig.2 1-8, 2.2.3 Removing the CD mechanism assembly (See Fig.1, 6 to 9) CD mechanism assembly Damper bracket • Prior to performing the following procedure, remove the CDDDamechanism control board and the front bracket (loadinghhmotor). (1) Remove the three screws D and the damper bracket. c (2) Raise the both sides fix arms and move the fix plates in the direction of the arrow to place the four shafts g as shown D in Fig.8 and 9. d (3) Remove the CD mechanism assembly and the two springs h attaching the flame. (4) Remove the two screws E and both sides rear damper brackets from the dampers. Detach the CD mechanism assembly from the left side to the right side. e CD mechanism ATTENTION: Front bracketAbcontrol board The CD mechanism assembly can be removed if only the rear Fig.1 damper bracket on the left side is removed. CD mechanism assembly Damper bracket

D

FlamehDDFig.6

D

Fig.7 Rear damper bracket Fix plate (L) E Fix arm (L) g g Damper Fig.8 Rear damper bracket Fix arm (R) E Fix plate(R) g g Damper Fig.9 1-9, 2.2.4 Removing the feed motor assembly (See Fig.10) • Prior to performing the following procedure, remove the CD mechanism control board, the front bracket (loading motor) FD screw Part iFeed motor assembly and the CD mechanism assembly. (1) Remove the two screws F and the feed motor assembly. 2.2.5 Removing the pickup unit Part j (See Fig.10 and 11) • Prior to performing the following procedure, remove the CD mechanism control board, the front bracket (loading motor), the CD mechanism assembly and the feed motor assembly. (1) Detach the FD gear part of the pickup unit upward. Then Pickup unit remove the pickup unit while pulling out the part i of the FD screw. ATTENTION: When reattaching the pickup unit, reattach the part j of FD gear Pickup unit the pickup unit, then the part i of the FD screw. Fig.10 (2) Remove the screw G attaching the nut push spring plate and the pickup mount nut from the pickup unit. Pull out the G FD screw. Nut push spring plate Pickup mount nut Pickup unit FD screw Fig.11 2.2.6 Removing the spindle motor (See Fig.12 and 13) • Prior to performing the following procedure, remove the CD mechanism control board, the front bracket (loading motor), the CD mechanism assembly and the feed motor assembly. (1) Turn up the CD mechanism assembly and remove the two k springs k on both sides of the clamper arms. Open the k clamper arm upward. (2) Turn the turn table, and remove the two screws H and the spindle motor. Fig.12 Spindle motor H

H

Fig.13 1-10,

SECTION 3 Adjustment method

Test instruments required for adjustment Standard volume position 1. Digital oscilloscope (100MHz) Balance and Bass &Treble volume : lndication"0" 2. AM Standard signal generator Loudness : OFF 3. FM Standard signal generator BBE : OFF 4. Stereo modulator Frequency Band 5. Electric voltmeter FM 87.5MHz ~ 108.0MHz 6. Digital tester MW 522kHz ~ 1620 kHz 7.Tracking offset meter LW 144kHz ~ 279kHz 8.Test Disc JVC :CTS-1000 9. Extension cable for check EXTGS004-26Px1Dummy load Exclusive dummy load should be used for AM,and FM. For FM dummy load,there is a loss of 6dB between SSG output and antenna input.The loss of 6dB need not be considered since direct reading of figures are applied in this working standard. Standard measuring conditions Power supply voltage: DC14.4V(11V to 16V allowance) Load impedance: 4 ohm (4ohm to 8ohm allowance) Line-Out Level/Impedance: 2.0V/20k ohm load(full scall) Output Impedance: 1k ohm How to connect the extension cable for adjusting EXTGS004-26P 1-11,

Flow of functional operation until TOC read

Power ON • When the pickup correctly moves Set Function to CD • When the laser diode correctly to the inner area of the disc emits Microprocessor $ 84 Microprocessor Disc inserted$ 83 $ 82 $ 81 commands commands 5V SEL 5V FMO 57 Hi-Z TC9462 0V TC9462 "53" 0V Pickup feed to the inner area 4VLD FEED MOTOR 6V CN501 7 +TETERRMMIINALL 4V YES 0V IC581 "5" 2V Laser emitted REST SW OFF

ON

• When correctly focused Focus search "No disc" FSO display TA2109 14 2.2V

YES

Focus Servo Loop ON Disc rotates • When the disc correctly rotates Microprocessor RF signal eye-pattern commands $ 8A $ 86 $ A200 remains closed 5V DMO 2.2V Tracking loop closed TC9462 55 0V RF signal eye-pattern opens Spindle 6V motor (-) 3.2V IC581 "7" 2V TOC readout Rough Acceleration Servo Servo CLV 0.5 Sec 0.5 Sec Jump to the first track Tracking Servo Loop ON Play • RF signal Rough Servo Mode CLV Servo Mode (ProgramArea) CLV Servo Mode (Lead-In Area; Digital: 0) 1-12,

Feed Section

Is the voltage output at NO Is the wiring for IC521 YES Is 5V present at IC581 NO Check CD 9V IC521 pin "53" 5V or 0V? (90) ~ (100) correct? pin "11"? and 5V. NO YES YES Check the vicinity of IC521. Is 4V present at both NO Is 6V or 2V present at YES Check the feed motor sides of the feed motor? IC581 "5" and "6"? connection wiring. YES NO Check the feed motor. Check IC581.

Focus Section NO

When the lens is Check the circuits in moving: the vicinity of IC581 pins "15" ~ "18". 4V

YES

Does the S-search waveform appear at IC581 pins "17" and "18"? YES Check the pickup and its connections.

Spindle Section

NO NO NO Is 4V present at IC521 Check IC501 and Is the disk rotated? Is 4V present at IC581 pins "7" and "8" ? pin "55" ? IC521. YES YES

YES

Check the vicinity of Does the RF signal Check the spindle motor IC581.appear at TP1? and its wiring. YES NO Is the RF waveform at Check the circuits in the TP1 distorted? NO vicinity of IC501 "19" ~ "24" or the pickup

YES

Proceed to the Tracking section

Tracking Section

When the disc is rotated at first: YES Check the circuit in the YES Check the pickup and vicinity of IC501 pins its connections. Approx. 1.2 V "2" ~ "12". Is the tracking error signal output at IC501 "12"?

YES

Check IC521. 1-13,

Maintenance of laser pickup

(1) Cleaning the pick up lens Before you replace the pick up, please try to clean the lens with a alcohol soaked cotton swab. (2) Life of the laser diode When the life of the laser diode has expired, the following symptoms will appear. (1) The level of RF output (EFM output:ampli tude of eye pattern) will be low. Is RF output NO Replace it. 1.0 0.35Vp-p?

YES

O.K

Replacement of laser pickup

Turn off the power switch and,disconnect the power cord from the ac outlet. (3) Semi-fixed resistor on the APC PC board The semi-fixed resistor on the APC printed circuit board which is attached to the pickup is used to adjust the laser power.Since this Replace the pickup with a normal one.(Refer adjustment should be performed to match the to "Pickup Removal" on the previous page) characteristics of the whole optical block, do not touch the semi-fixed resistor. If the laser power is lower than the specified value,the laser diode is almost worn out, and Plug the power cord in,and turn the power on. the laser pickup should be replaced. At this time,check that the laser emits for If the semi-fixed resistor is adjusted while about 3seconds and the objective lens moves the pickup is functioning normally,the laser up and down. pickup may be damaged due to excessive Note: Do not observe the laser beam directly. current. Play a disc. Check the eye-pattern at TP1. Finish. 1-14,

SECTION 4 Description of major ICs

4.1 HA13164A (IC961) : Regulator • Terminal layout12345678910 11 12 13 14 15 • Block diagram +B C1 C2 100u 0.1u

ACC

VCC 8 ACC3 BATT.DET OUT ANT OUT Surge Protector C3 0.1u EXT OUT COMPOUT 1 BIAS TSD 6 C4 0.1u VDD OUT ANT CTRL47C7 0.1u

CTRL

SW5VOUT CD OUT 5 C5 0.1u AUDIO OUT ILMOUT 10 14 C8 C6 0.1u 10u 15 TAB 13 R1 GND GND ILM AJ UNIT R: C:F note1) TAB (header of IC) connected to GND • Pin function Pin No. Symbol Function 1 EXTOUT Output voltage is VCC-1 V when M or H level applied to CTRL pin. 2 ANTOUT Output voltage is VCC-1 V when M or H level to CTRL pin and H level to ANT-CTRL. 3 ACCIN Connected to ACC. 4 VDDOUT Regular 5.7V. 5 SW5VOUT Output voltage is 5V when M or H level applied to CTRL pin. 6 COMPOUT Output for ACC detector. 7 ANT CTRL L:ANT output OFF, H:ANT output ON 8 VCC Connected to VCC. 9 BATT DET Low battery detect. 10 AUDIO OUT Output voltage is 9V when M or H level applied to CTRL pin. 11 CTRL L:BIAS OFF, M:BIAS ON, H:CD ON 12 CD OUT Output voltage is 8V when H level applied to CTRL pin. 13 ILM AJ Adjustment pin for ILM output voltage. 14 ILM OUT Output voltage is 10V when M or H level applied to CTRL pin. 15 GND Connected to GND. 1-15, 4.2 LA4743K (IC301) : Power amp. • Block diagram + 2200 F 0.022 F Vcc 1/2 Vcc 3/4 6 20 IN 1 + OUT 1+ 11 - 9 0.22 F OUT 1- + 7 TAB 1 PWR GND1 Protective circuit 8 OUT 2+ - 5 IN 2 + OUT 2- 12 + 3 0.22 F PWR GND2 ST BY Stand by +5V Switch ST ON Mute Ripple Mute 10K R.F + 10 22 47 F Filter circuit + 3.3 F Low Level IN 3 Mute ON+ OUT 3+ 15 - 17 0.22 F OUT 3- + 19 N.C 25 PWR GND3 Protective 18 circuit PRE GND 13 OUT 4+ - 21 IN 4 + 14 + OUT 4-23 0.22 F Muting & ON TIME C PWR GND4 + 16 ON Time Control 24 Circuit 22 F - + - + - + - + 1-16, • Terminal layout • Pin function Pin No. Symbol Function 1 TAB Header of IC 2 GND Power GND 3 FR- Outpur(-) for front Rch 4 STDBY Stand by input 5 FR+ Output (+) for front Rch 6 VP1 Power input 7 RR- Output (-) for rear Rch 8 GND Power GND 9 RR+ Output (+) for rear Rch 10 RIPPLE Ripple filter 11 RRIN Rear Rch input 12 FRIN Front Rch input 13 SGND Signal GND 14 FLIN Front Lch input 15 RLIN Rear Lch input 16 ONTIME Power on time control 17 RL+ Output (+) for rear Lch 18 GND Power GND 19 RL- Output (-) for rear Lch 20 VP3 Power input 21 FL+ Output (+) for front 22 MUTE Muting control input 23 FL- Output (-) for front 24 GND Power GND 25 NC Non connection

TAB GND

FR-

STDBY

FR+ VP1 RR-

GND

RR+

RIPPLE INRF INRR SGND FLIN RLIN DNTIME

RL+

GND

RL- VP3 FL+

MUTE

FL-

GND NC

1-17, 4.3 LA6567H-X (IC501) : CD driver • Pin layout & Blockdiagram

VCC2 1 CH 3,4,5 Thermal shutdown 28 REV

Power supply

V05- 2 27 FWD

CH5

V05+ 3 26 S-GND V04+ 4 25 VCONT

CH4 22K 11K

V04- 5 24 VIN4 V03+ 6 23 VIN4G

CH3

V03- 7 Signal system power supply 22 VCC-S FR FR FR FR V02+ 8 5VREG(PNPTr 21 VREF-IN

The outside putting) CH2

V02- 9 20 REG-OUT V01+ 10 19 REG-IN

22K CH1

V01- 11 18 VIN3G

11K CH1,2

VCC1 12 Power supply 22K 17 VIN3

22K 11K

VIN1 13 16 VIN2G

11K

VIN1G 14 15 VIN2

Level shift Level shift Level shift Level shift Output control Input 1-18, • Pin function Pin no. Symbol Function 1 VCC2 CH3,4,5 Power supply( It is short with VCC1,VCC-S) 2 V05- Loading output(-) 3 V05+ Loading terminal (+) 4 V04+ CH4 Output terminal(+) 5 V04- CH4 Output terminal(-) 6 V03+ CH3 Output terminal(+) 7 V03- CH3 Output terminal(-) 8 V02+ CH2 Output terminal(+) 9 V02- CH2 Output terminal(-) 10 V01+ CH1 Output terminal(+) 11 V01- CH1 Output terminal(-) 12 VCC1 CH1,2(BTL) Power supply(It is short with VCC-S,VCC2) 13 VIN1 CH1 Input terminal 14 VIN1G CH1 Input terminal(For gain adjustment) 15 VIN2 CH2 Input terminal 16 VIN2G CH2 Input terminal(For gain adjustment) 17 VIN3 CH3 Input terminal 18 VIN3G CH3 Input terminal(For gain adjustment) 19 REG-IN Regulator terminal(Outside putting PNP base) 20 REG-OUT Regulator terminal(Outside putting PNP collector) 21 VREF-IN Standard voltage input terminal 22 VCC-S Signal system power supply(It is short with VCC1,VCC2) 23 VIN4G CH4 Input terminal(For gain adjustment) 24 VIN4 CH4 Input terminal 25 VCONT 5CH(VLO) Output voltage set terminal 26 S-GND Signal system GND 27 FWD 5CH(VLO)Signal output switch terminal(FWD) ,Input of logic of loading part 28 REV 5CH(VLO)Signal output switch terminal(REV), Input of logic of loading part - Frame(FR)at the center becomes system GND. - Please be short-circuited on the outside and use the terminal of the power supply system and three teminals of VCC-S, VCC1,VCC2. 1-19, 4.4 LC75823W (IC601) : LCD driver • Pin Layout & Symbol 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 S1 1 48 S48 S2 2 47 S47 S3 3 46 S46 S4 4 45 S45 S5 5 44 S44 S6 6 43 S43 S7 7 42 S42 S8 8 41 S41 S9 9 40 S40 S10 10 39 S39 S11 11 38 S38 S12 12 37 S37 S13 13 36 S36 S14 14 35 S35 S15 15 34 S34 S16 16 33 S33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 • Pin function Pin No. Symbol I/O Functions 1 to 52 S1 to S52 O Segment output pins used to display data transferred by serial data input. 53 to 55 COM1 to COM3 O Common driver output pins. The frame frequency is given by : t0=(fosc/384)Hz. 56 VDD - Power supply connection. Provide a voltage of between 4.5 and 6.0V. 57 INH I Display turning off input pin. INT="L" (Vss) - off (S1 to S52, COM1 to COM3="L" INT="H" (VDD)- on Serial data can be transferred in display off mode. 58 VDD1 I Used for applying the LCD drive 2/3 bias voltage externally. Must be connected to VDD2 when a 1/2 bias drive scheme is used. 59 VDD2 I Used for applying the LCD drive 1/3 bias voltage externally. Must be connected to VDD1 when a 1/2 bias drive scheme is used. 60 VSS - Power supply connection. Connect to GND. 61 OSC I/O Oscillator connection. An oscillator circuit is formed by connecting an external resistor and capacitor at this pin. 62 CE I Serial data interface connection to the controller. CE : Chip enable 63 CL I Serial data interface connection to the controller. CL : Sync.clock 64 DI I Serial data interface connection to the controller. DI : Transfer data S17 DI S18 CL S19 CE S20 OSC S21 Vss S22 VDD2 S23 VDD1 S24 INH S25 VDD S26 COM3 S27 COM2 S28 COM1 S29 S52 S30 S51 S31 S50 S32 S49 1-20, 4.5 NJM4565M-WE (IC581) : Ope. amp A OUTPUT18V+ A - INPUT27BOUTPUT A + INPUT36B- INPUT V- 4 5 B+ INPUT 1-21, 4.6 TA2109F-X (IC521) : RF amp. • Pin layout 24 13 1 12 • Block diagram 15k ohm 30k ohm 15k ohm 10k ohm 7.67k ohm

SBAD

13 10k ohm

TEO

50k ohm 20uA 30k ohm 20pF FEO TEN 14 11 36pF 10k ohm 21k ohm 29k ohm 10k ohm FEN 7.96k ohm 2VRO 15 10 10k ohm 24k ohm 24k ohm VRO TEB 16 93 STATE 21k ohm 21k ohm DET. 20k ohm 50uARFRP SW1 SEL17 12k ohm 47k ohm 8 1.74k ohm LDC 12k ohm RFIS SW2 1k ohm LDO 18 7 20k ohm 680 ohm SW3

PEAK

RFGO BOTTOM 180k ohm MDI 19 6 20pF 13k ohm 2.12k ohm RFGC TNI 20 I-I 5 180k ohm 23.5k ohm 12k ohm 20pF AGCI TPI 21 I-I 4 re=130 ohm 20k ohm 180k ohm RFO FPI 22 340pF 60k ohm 20k ohm 20k ohm GND 60k ohm FNI 23 2 1.53k ohm 180k ohm 40pF 20k ohm RFN Vcc 24 1 3.3k ohm 3.3k ohm 10pF 20k ohm 65uA 1-22, • Pin function Pin No. Symbol I/O Pin function 1 Vcc - Power supply input terminal 2 FNI I Main beam I-V amp input terminal 3 FPI I Main beam I-V amp input terminal 4 TPI I Sub beam I-v input terminal 5 TNI I Sub beam I-V input terminal 6 MDI I Monitor photo diode amp input terminal 7 LDO O Laser diode amp output terminal 8 SEL I Laser diode control signal input terminal 9 TEB I T. error balance adj. signal input terminal 10 2VRO O Reference voltage output terminal 11 TEN I TE amp negative input terminal 12 TEO O TE error signal output terminal 13 SBAD O Sub beam adder signal output terminal 14 FEO O Focus error signal output terminal 15 FEN I FE amp negative input terminal 16 VRO O Reference voltage (VREF) output terminal 17 RFRP O Track count signal output terminal 18 RFIS I RFRP detect circuit input terminal 19 RFGO O RF gain signal output terminal 20 RFGC I RF amplitude adj. control signal input terminal 21 AGCI I RF signal amplitude adj. amp input terminal 22 RFO O RF signal output terminal 23 GND - Ground terminal 24 RFN I RF amp negative input terminal 1-23, 4.7 TC9462F (IC541) : DSP • Pin layout & Block Diagram 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DVSR 81 50 VREF RO 82 1bit Servo PWM D/A 49 TRO

LPF

DVDD 83 DAC Clock control 48 FOO DVR 84 generator + 47 TEZI LO 85 - 46 TEI DVSL 86 45 TSIN TEST1 87 44 SBAD

ROM

TEST2 88 Digital equalizer + 43 FEI Address circuit A/D TEST3 89 Automatic adjustment - 42 RFRP

RAM

BUS0 90 circuit + 41 RFZI Micon BUS1 91 - 40 RFCT interface BUS2 92 Correction 39 AVDD

CLV servo

BUS3 93 circuit Data 38 RFI VDD 94 16KRAM Synchronous slicer 37 SLCO guarantee VSS 95 EFM decode 36 AVSS BUCK 96 35 VCOF CCE 97 VCO 34 VCOREF TEST4 98 Audio out + 33 PVREF

Digital out Sub code

TSMOD 99 circuit decoder Status 32 LPFOPLL - RST 100 31 LPFN

TMAX

12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 TEST0 XVDD HSO XO UHSO XI EMPH XVSS LRCK VDD VSS PXO BCK PXI AOUT VSS DOUT TESIO1 MBOV TESIN IPF DACT SBOK CKSE CLCK DMOUT VDD IO3 VSS IO2 DATA IO1 SFSY IO0 SBSY VSS SPCK VDD SPDA FLGD COFS FLGC MONIT FLGB VDD FLGA TESIO0 SEL P2VREF 2VREF HSSW DMO ZDET FVO PDO FMO TMAXS TEBC TMAX RFGC 1-24, • Pin function PIN No. SYMBOL I/O FUNCTIONAL DESCRIPTION REMARKS 1 TEST0 I Test mode terminal.Normally, Keep at open. With pull-up resistor. 2 HSO 0 Playback speed mode flag output terminal. UHSO HSO PLAYBACK SPEEDHHNomal - 3 UHSO0HL2timesLH4timesLL- 4 EMPH 0 Subcode Q data emphasis flag output terminal.Emphasis ON at "H" level andOFF at "L" level.The output polarity can invert by command. - 5 LRCK 0 Channel clock output terminal.(44.1khz)L-ch at "L" level and R-ch at "H" level.the output polarity can invert by command. - 6 VSS - Digital GND terminal. - 7 BCK 0 Bit clock output terminal.(1.4112MHz) - 8 AOUT 0 Audio data output terminal. - 9 DOUT 0 Digital data output terminal. - 10 MBOV 0 Buffer memory over signal output terminal. Over at "H" level. - 11 IPF 0 Correction flag output terminal. At "H" level,AOUT output is made to correctionimpossibility by C2 correction processing. - 12 SBOK 0 Subcode Q data CRCC check adjusting result output terminal.The adjustingresult is OK at "H" level. - 13 CLCK I/O Subcode P~W data readout clock input/output terminal.This terminal can select by command bit. - 14 VDD - Digital power supply voltage terminal. - 15 VSS - Digital GND terminal. - 16 DATA 0 Subcode P~W data output terminal. - 17 SFSY 0 Play-back frame sync signal output terminal. - 18 SBSY 0 Subcode block sync signal output terminal. - 19 SPCK 0 Processor status signal readout clock output terminal. - 20 SPDA 0 Processor status signal output terminal. - 21 COFS 0 Correction frame clock output terminal. (7.35kHz) - 22 MONIT 0 Internal signal (DSP internal flag and PLL clock) output terminal.Selected bycommand.This terminal output the text data with serial by command. - 23 VDD - Digital power supply voltage terminal. - 24 TESIO0 I Test input/output terminal.Normally,keep at "L" level. The terminal that input-ted the clock for read of text data by command. - 25 P2VREF - PLL double reference voltage supply terminal. - 26 HSSW O 2/4 times speed at "VREF" voltage. 2-state output (PVREF,HiZ) 27 ZDETO1bit DA converter zero detect flag output terminal. - 28 PDO O Phase difference signal output terminal of EFM signal and PLCK signal. 3-state output. (P2VREF, PVR,VSS) 29 TMAXS O TMAX detection result output terminal. Selected by command bit (TMPS) 3-state output. (P2VREF,PVREF, VSS) 30 TMAX O TMAX detection result output terminal. Selected by command bit (TMPS) 3-state output. DIFFERENCE RESULT TMAX OUTPUT (P2VREF,HiZ,VSS) Longer than fixed freq. "P2VREF" Shorter than fixed freq. "VSS" Within the fixed freq. "Hiz" 31 LPFN I LPF amplifier inverting terminal for PLL. Analog input. 32 LPFO O LPF amplifier output terminal for PLL. Analog output. 33 PVREF - PLL reference voltage supply terminal. - 1-25, PIN No. SYMBOL I/O FUNCTIONAL DESCRIPTION REMARKS 34 VCOREF I VCO center frequency reference level terminal. Normallykeep at "PVREF" level. - 35 VCOF O VCO filter terminal. Analog output. 36 AVSS - Analog GND terminal. - 37 SLCO O Data slice level output terminal. Analog output. 38 RFI I RF signal input terminal. Analog input. (Zin:selected b command) 39 AVDD - Analog power supply voltage terminal. - 40 RFCT I RFRP signal center level input terminal Analog input (Zin : 50k OHM ) 41 RFZI I RFRP zero cross input terminal Analog input. 42 RFRP I RF ripple signal input terminal Analog input. 43 FEI I Focus error signal input terminal Analog input. 44 SBAD I Sub-beam adder signal input terminal Analog input. 45 TSIN I Test input terminal Normally, keep at "vref" level Analog input. 46 TEI I Tracking error signal input terminal. Take in at tracking servo ON. Analog input. 47 TEZI I Tracking error zero cross input terminal Analog input (Zin :10k OHM) 48 FOO O Focus servo equalizer output terminal Analog output. (2VREF ~ AVSS) 49 TRO O Tracking servo equalizer output terminal - 50 VREF - Analog reference voltage supply terminal 3-state PWM signal 51 RFGC O RF amplitude adjustment control signal output terminal outpu. (2VREF,VREF,VSS) 52 TEBC O Tracking balance control signal output terminal (PWM carrer=88.2kHz) 53 FMO O Feed equalizer output terminal 54 FVO O Speed error signal or feed search equalizer output terminal 55 DMO O Disk equalizer output terminal (PWM carrier=88.2kHz for DSP Synchronize to PXO) 3-state output. (2VREF,VREF,VSS) 56 2VREF - Analog double reference voltage supply terminal - 57 SEL O APC circuit ON/OFF indication signal output terminal - 58~61 FLGA~D O External flag output terminal for internal signal - 62 VDD - Digital power supply voltage terminal - 63 VSS - Digital GND terminal - 64~67 IO0~3 I/O General I/O terminal - 68 DMOUT I This terminal control IO0~IO3 terminal With pull-up resistor. 69 CKSE I Normally, keep at open With pull-up resistor. 70 DACT I DAC test mode terminal. Normally keep at open With pull-up resistor. 71 TESIN I Test input terminal, Normally, keep at "L" level Analog input. 72 TESIO1 I Test input/output terminal. Normally keep at "L" level Analog input. 73 VSS - Digital GND terminal - 74 PXI I Crystal oscillator connecting input terminal for DSP - 75 PXO O Crystal oscillator connecting output terminal for DSP - 76 VDD - Digital power supply voltage terminal - 77 XVSS - Oscillator GND terminal for system clock - 78 XI I Crystal oscillator connecting input terminal for system clock - 79 XO O Crystal oscillator connecting output terminal for system clock - 80 XVDD - Oscillator power supply voltage terminal for system clock - 81 DVSR - Analog GND terminal for DA converter (Rch) - 82 ROORchannel data forward output terminal - 1-26, PIN No. SYMBOL I/O FUNCTIONAL DESCRIPTION REMARKS 83 DVDD - Analog supply voltage terminal for DA converter - 84 DVR - Reference voltage terminal for DA converter - 85 LOOLchannel data forward output terminal - 86 DVSL - Analog GND terminal for DA converter (Lch) - 87~89 TEST1~3 I Test mode terminal . Normal keep at open With piull-up resis- tor. 90~93 BUS0~3 I/O Micon interface data input/output terminal Schmit input. With pull-up resis- tor. 94 VDD - Digital power supply voltage terminal - 95 VSS - Digital GND terminal - 96 BUCK I Micon interface clock input terminal Schmit input. 97 CCE I Command and data sending/receiving chip enable signal input terminal Schmit input. 98 TEST4 I Test mode terminal. Normal, keep at open With pull-up resistor. 99 TSMOD I Local test mode selection terminal With pull-up resistor. 100 RST I Reset signal input terminal. Reset at "L" level With pull-up resistor. 1-27, 4.8 SAA6579T-X(IC71):RDS detecter • Pin layout QUAL 1 16 CLK DATA 2 15 T57 Vref 3 14 OSCO MUX 4 13 OSCI Vdd 5 12 Vdd GND 6 11 GND CIN 7 10 TEST SCOUT89MODE • Block diagram 13 14 12 4 ANTI- 57 kHz OSCILLATOR ALIASING BAND PASS RECONSTRUCTION QUALITY BIT

AND

FILTER (8th ORDER) FILTER GENERATORDIVIDER 7 CLOCKED COSTAS LOOP BIPHASE DIFFERENTIAL 2 COMPARATOR VARIABLE AND SYMBOL DECODER FIXED DIVIDER DECODER 5 15 VP1 3 CLOCKREFERENCE REGERATION TEST LOGIC AND OUTPUT

VOLTAGE

AND SYNC SELECTOR SWITCH6910 11 • Pin function

Pin No. Symbol Description

1 QUAL Quality indication output 2 DATA RDS data output 3 Vref Reference voltage output (0.5VDDA) 4 MUX Multiolex signal input 5 Vdd +5V supply voltage for analog part 6 GND Ground for analog part (0V) 7 CIN Sub carrier input to comparator 8 SCOUT Sub carrier output of reconstruction filter 9 MODE Oscillator mode / test control input 10 TEST Test enable input 11 GND Ground for digital part (0V) 12 Vdd +5V supply voltage for digital part 13 OSCI Oscillator input 14 OSCO Oscillator output 15 T57 57 kHz clock signal output 16 CLK RDS clock output 1-28, 4.9 TEA6320T-X (IC161) : E.volume • Pin layout SDA 1 32 SCL GND 2 31 VCC OUTLR 3 30 OUTRR OUTLF 4 29 OUTRF TL 5 28 TR B2L 6 27 B2R B1L 7 26 B1R IVL 8 25 IVR ILL 9 24 ILR QSL 10 23 QSR IDL 11 22 IDR MUTE 12 21 Vref ICL 13 CD-CH 20 ICR IMD 14 19 CAP IBL 15 TAPE 18 IBR IAL 16 TUNER 17 IAR • Block diagram 108976512 MUTE VOLUME 2 FUNCTION 0 to 55 dB21 3 ZERO CROSS BALANCE 31 POWER DETECTOR FENDER REAR

SUPPLY

2 VOLUME 1

BASS

19 +20 to -31 dB

TREBLE

LEFT VOLUME 2 LOUDNESS LEFT +15 dB 0 to 55 dB LEFT +12 dB 4BALANCE FENDER FRONT 16 32 15 LOGIC HC BUSREC 13 1

SOURCE

SELECTOR VOLUME 2 14 VOLUME10to -55dB BASS TREBLE +20 to -31 dB BALANCE 29 RIGHT RIGHT 22 LOUDNESS FENDER FRONT+15 dB +12 dB

RIGHT

18 VOLUME20to -55dB 17 30BALANCE FENDER REAR 23 25 24 26 27 28 • Pin functions Pin Pin No. Symbol I/O Functions No. Symbol I/O Functions 1 SDA I/O Serial data input/output. 17 IAR I Input A right source. 2 GND - Ground. 18 IBR I Input B right source. 3 OUTLR O output left rear. 19 CAP - Electronic filtering for supply. 4 OUTLF O output left front. 20 ICR I Input C right source. 5 TL I Treble control capacitor left channel 21 Vref - Reference voltage (0.5Vcc) or input from an external equalizer. 22 IDR - Not used 6 B2L - Bass control capacitor left channel or 23 QSR O Output source selector right channel. output to an external equalizer. 24 ILR I Input loudness right channel. 7 B1L - Bass control capacitor left channel. 25 IVR I Input volume 1. right control part. 8 IVL I Input volume 1. left control part. 26 B1R - Bass control capacitor right channel 9 ILL I Input loudness. left control part. 27 B2R O Bass control capacitor right channel 10 QSL O Output source selector. left channel. or output to an external equalizer. 11 IDL - Not used 28 TR I Treble control capacitor right channel 12 MUTE - Not used or input from an external equalizer. 13 ICL I Input C left source. 29 OUTRF O Output right front. 14 IMO - Not used 30 OUTRR O Output right rear. 15 IBL I Input B left source. 31 Vcc - Supply voltage. 16 IAL I Input A left source. 32 SCL I Serial clock input. 1-29, 4.10 UPD178078GF-558 (IC701) : System CPU • Pin layout 80 ~ 51 81 50 ~ ~ 100 31 1 ~ 30 • Pin function Pin No. Symbol I/O FUNCTION 1 NC - No connection 2 BUSINT I JVC bus communication line 3 BUSSI I JVC bus communication line 4 BUSSO O JVC bus communication line 5 BUSSCK O JVC bus communication line 6,7 NC - No connection 8 I2CDAI I Serial data input 9 I2CDAO O Serial data output 10 I2CCLK O Serial clock output 11 NC - No connection 12 LCDDA O LCD driver serial data output 13 LCDSCK O LCD driver serial clock output 14 BUSI/O O JVC bus output select 15 NC - No connection 16 LCDCE O LCD driver communication line 17 SW2 I CD mech switch 18 SW3 I CD mech switch 19 SW4 I CD mech switch 20 RESTSW I Traverse mech rest switch 21 ENC1 I Encoder 1 input 22 ENC2 I Encoder 2 input 23 KEY0 I Key input 24 KEY1 I Key input 25 KEY2 I Key input 26 LEVEL I Audio level input 27 AVDD - Power supply 28 SM I Signal level meter input 29 SQ I Signal quality input 30,31 NC - Non connection 32 AVSS - Connect to GND 33 REGCPU - Connect to GND with capacitor 34 VDD - Power supply 35 REGOSC - Connect to GND with capacitor 36 X2 - System clock 37 X1 I System clock 38 GND0 - Connect to GND 39 SD/ST I Station detector & Stereo indicator 40 GND2 - Connect to GND 41 NC - No connection 42 IFC I IF count input 1-30, Pin No. Symbol I/O FUNCTION 43 VDDPLL - - 44 OSC I FM,AM osc input 45 NC - No connection 46 GNDPLL - - 47 AMEQ O PLL error output for AM 48 FMEQ O PLL error output for FM 49 IC(VPP) - Setting to write for flash 50 RESET I System reset 51 SW1 I CD mech switch 52 REMOCON I Remocon input 53 NC - Non connection 54 TEL_MUTE O TEL mute output 55 POWER O Power control 56 CDON O CD power control 57 MUTE O Mute control 58 STAGE 1 - - 59 BUZZER - Non connection 60 STAGE 2 - - 61~68 NC - Non connection 69 LM0 O CD mech driver control 70 LM1 O CD mech driver control 71 BUCK O CD LSI communication line 72 CCE O CD LSI communication line 73 BUS0 I/O CD LSI communication line 74 BUS1 I/O CD LSI communication line 75 BUS2 I/O CD LSI communication line 76 BUS3 I/O CD LSI communication line 77 RST O CD LSI communication line 78 PS1 I ACC detection input 79 PS2 I Memory detection 80 DETACH I Detach detection 81 RDSSCK I Clock input for RDS 82 GND1 - Connect to GND 83 MONO O Mono by force 84 SEEK/STOP O Switching SEEK & STOP 85 FM/AM O Band switch 86 AFCK O AFcheck output 87 RDSDA I RDS data input 88 PLLMONITOR - Non connection 89~98 NC - Non connection 99 VDDPORT - Vdd 100 GNDPORT - Connect to GND 1-31, VICTOR COMPANY OF JAPAN, LIMITED AV & MULTIMEDIA COMPANY 10-1,1chome,Ohwatari-machi,Maebashi-city,371-8543,Japan (No.49762) Printed in Japan 2002/12]

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