Download: a PrecisionInstrumentation Amplifier AD624

a PrecisionInstrumentation Amplifier

AD624

FEATURES FUNCTIONAL BLOCK DIAGRAM Low Noise: 0.2 V p-p 0.1 Hz to 10 Hz Low Gain TC: 5 ppm max (G = 1) 50 Low Nonlinearity: 0.001% max (G = 1 to 200) –INPUT High CMRR: 130 dB min (G = 500 to 1000) G = 100 AD624 Low Input Offset Voltage: 25 V, max 225.3 Low Input Offset Voltage Drift: 0.25 V/C max G = 200 4445.7 Gain Bandwidth Product: 25 MHz VB 10k G = 500 SENSE Pin Programmable Gains of 1, 100, 200, 500, 1000 80.2 20k 10k No External Components Required RG1 OUTPUT Internally Compensated 20k 10kRG2 10k

REF

+INPUT PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD624 is a high precision, low noise, instrumentation 1. The AD624 offers outstanding noise performance. Input amplifier designed primarily for use with low level transducers, noise is typically less than 4 nV/√Hz at 1 kHz. including load cells, strain gauges and pressure transducers. An 2. The AD624 is a functionally complete instrumentation am- outstanding combination of low noise, high gain accuracy, low plifier. Pin programmable gains of 1, 100, 200, 500 and 1000 gain temperature coefficient and high linearity make the AD624 are provided on the chip. Other gains are achieved through ideal for use in high resolution data acquisition systems. the use of a single external resistor. The AD624C has an input offset voltage drift of less than 3. The offset voltage, offset voltage drift, gain accuracy and gain 0.25 µV/°C, output offset voltage drift of less than 10 µV/°C, temperature coefficients are guaranteed for all pretrimmed CMRR above 80 dB at unity gain (130 dB at G = 500) and a gains. maximum nonlinearity of 0.001% at G = 1. In addition to these outstanding dc specifications, the AD624 exhibits superior ac 4. The AD624 provides totally independent input and output performance as well. A 25 MHz gain bandwidth product, 5 V/µs offset nulling terminals for high precision applications. slew rate and 15 µs settling time permit the use of the AD624 in This minimizes the effect of offset voltage in gain ranging high speed data acquisition applications. applications. The AD624 does not need any external components for pre- 5. A sense terminal is provided to enable the user to minimize trimmed gains of 1, 100, 200, 500 and 1000. Additional gains the errors induced through long leads. A reference terminal is such as 250 and 333 can be programmed within one percent also provided to permit level shifting at the output. accuracy with external jumpers. A single external resistor can also be used to set the 624’s gain to any value in the range of 1 to 10,000. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. which may result from its use. No license is granted by implication or Tel: 781/329-4700 www.analog.com otherwise under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 1999,

AD624–SPECIFICATIONS (@ VS = 15 V, RL = 2 k and TA = +25C, unless otherwise noted)

Model AD624A AD624B AD624C AD624S Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units

GAIN

Gain Equation (External Resistor Gain Programming) 40,000 40,000 40,000 40,000 + 1 ± 20% + 1 ± 20% + 1 ± 20% + 1 ± 20% RRRRGGGGGain Range (Pin Programmable) 1 to 1000 1 to 1000 1 to 1000 1 to 1000 Gain Error G = 1 ±0.05 ±0.03 ±0.02 ±0.05 % G = 100 ±0.25 ±0.15 ±0.1 ±0.25 % G = 200, 500 ±0.5 ±0.35 ±0.25 ±0.5 % Nonlinearity G = 1 ± 0.005 ± 0.003 ± 0.001 ± 0.005 % G = 100, 200 ± 0.005 ± 0.003 ± 0.001 ± 0.005 % G = 500 ± 0.005 ± 0.005 ± 0.005 ± 0.005 % Gain vs. Temperature G = 15555ppm/°C G = 100, 200 10 10 10 10 ppm/°C G = 500 25 15 15 15 ppm/°C VOLTAGE OFFSET (May be Nulled) Input Offset Voltage 200 75 25 75 µV vs. Temperature 2 0.5 0.25 2.0 µV/°C Output Offset Voltage5323mV vs. Temperature 50 25 10 50 µV/°C OOffUsTet Referred to the Input vs. Supply G = 1 70 75 80 75 dB G = 100, 200 95 105 110 105 dB G = 500 100 110 115 110 dB INPUT CURRENT Input Bias Current ±50 ±25 ±15 ±50 nA vs. Temperature ± 50 ± 50 ± 50 ± 50 pA/°C Input Offset Current ±35 ±15 ±10 ±35 nA vs. Temperature ± 20 ± 20 ± 20 ± 20 pA/°C

INPUT

Input Impedance Differential Resistance 109 109 109 109 Ω Differential Capacitance 10 10 10 10 pF Common-Mode Resistance 109 109 109 109 Ω Common-Mode Capacitance 10 10 10 10 pF Input Voltage Range1 Max Differ. Input Linear (VDL) ± 10 ± 10 ± 10 ± 10 VGGGGMax Common-Mode Linear (V 12 V − × V 12 V − × VCM) 2D2D12 V − × V2D12 V − × V2DVCommon-Mode Rejection dc to 60 Hz with 1 kΩ Source Imbalance G = 1 70 75 80 70 dB G = 100, 200 100 105 110 100 dB G = 500 110 120 130 110 dB OUTPUT RATING V , RL = 2 kΩ ± 10 ± 10 ± 10 ± 10 V DYNAMIC RESPONSE Small Signal –3 dB G = 11111MHz G = 100 150 150 150 150 kHz G = 200 100 100 100 100 kHz G = 500 50 50 50 50 kHz G = 1000 25 25 25 25 kHz Slew Rate 5.0 5.0 5.0 5.0 V/µs Settling Time to 0.01%, 20 V Step G = 1 to 200 15 15 15 15 µs G = 500 35 35 35 35 µs G = 1000 75 75 75 75 µs

NOISE

Voltage Noise, 1 kHz R.T.I. 4444nV/√Hz R.T.O. 75 75 75 75 nV/√Hz R.T.I., 0.1 Hz to 10 Hz G = 1 10 10 10 10 µV p-p G = 100 0.3 0.3 0.3 0.3 µV p-p G = 200, 500, 1000 0.2 0.2 0.2 0.2 µV p-p Current Noise 0.1 Hz to 10 Hz 60 60 60 60 pA p-p SENSE INPUT RIN 8 10 12 8 10 12 8 10 12 8 10 12 kΩ IIN 30 30 30 30 µA Voltage Range ± 10 ± 10 ± 10 ± 10 V Gain to Output1111% –2– REV. C, Model AD624A AD624B AD624C AD624S Min Typ Max Min Typ Max Min Typ Max Min Typ Max Units REFERENCE INPUT RIN 16 20 24 16 20 24 16 20 24 16 20 24 kΩ IIN 30 30 30 30 µA Voltage Range ± 10 ± 10 ± 10 ± 10 V Gain to Output1111% TEMPERATURE RANGE Specified Performance –25 +85 –25 +85 –25 +85 –55 +125 °C Storage –65 +150 –65 +150 –65 +150 –65 +150 °C POWER SUPPLY Power Supply Range 6 15 18 6 15 18 6 15 18 6 15 18 V Quiescent Current 3.5 5 3.5 5 3.5 5 3.5 5 mA

NOTES

1VDL is the maximum differential input voltage at G = 1 for specified nonlinearity, V DL at other gains = 10 V/G. VD = actual differential input voltage. 1Example: G = 10, VD = 0.50. VCM = 12 V – (10/2 × 0.50 V) = 9.5 V. Specifications subject to change without notice. Specifications shown in boldface are tested on all production unit at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

ABSOLUTE MAXIMUM RATINGS* CONNECTION DIAGRAM Supply Voltage .±18 V Internal Power Dissipation .420 mW Input Voltage .±V –INPUT 1 16 RG1S Differential Input Voltage .±V +INPUT 2 15 OUTPUT NULLS Output Short Circuit Duration .Indefinite RG2 3 14 OUTPUT NULL Storage Temperature Range .–65°C to +150°C INPUT NULL 4 AD624 13 G = 100 SHORT TO Operating Temperature Range TOP VIEWINPUT NULL 5 RG2 FOR(Not to Scale) 12 G = 200 AD624A/B/C .–25°C to +85°C DESIREDREF 6 11 G = 500 GAIN AD624S .–55°C to +125°C –VS 7 10 SENSE Lead Temperature (Soldering, 60 secs) .+300°C

+VS89OUTPUT *Stresses above those listed under Absolute Maximum Ratings may cause perma- nent damage to the device. This is a stress rating only; functional operation of the FOR GAINS OF 1000 SHORT RG1 TO PIN 12 device at these or any other conditions above those indicated in the operational AND PINS 11 AND 13 TO RG2 sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

METALIZATION PHOTOGRAPH

Contact factory for latest dimensions

ORDERING GUIDE Dimensions shown in inches and (mm).

Temperature Package Package Model Range Description Option AD624AD –25°C to +85°C 16-Lead Ceramic DIP D-16 AD624BD –25°C to +85°C 16-Lead Ceramic DIP D-16 AD624CD –25°C to +85°C 16-Lead Ceramic DIP D-16 AD624SD –55°C to +125°C 16-Lead Ceramic DIP D-16 AD624SD/883B* –55°C to +125°C 16-Lead Ceramic DIP D-16 AD624AChips –25°C to +85°C Die AD624SChips –25°C to +85°C Die *See Analog Devices’ military data sheet for 883B specifications.

REV. C –3–

,

AD624–Typical Characteristics

20 20 30 15 15 +25C 10 10550000510 15 200510 15 20 10 100 1k 10k SUPPLY VOLTAGE – V SUPPLY VOLTAGE – V LOAD RESISTANCE –

Figure 1. Input Voltage Range vs. Figure 2. Output Voltage Swing vs. Figure 3. Output Voltage Swing vs. Supply Voltage, G = 1 Supply Voltage Load Resistance

8.0 16 40 14 30 6.0 12 20 10 10 4.0806–10 2.0 4 –20 2 –3000–400510 15 200510 15 20 –125 –75 –25 25 75 125 SUPPLY VOLTAGE – V SUPPLY VOLTAGE – V TEMPERATURE – C

Figure 4. Quiescent Current vs. Figure 5. Input Bias Current vs. Figure 6. Input Bias Current vs. Supply Voltage Supply Voltage Temperature

16 –1 2 100 3 10000510 15 207110 100 1k 10k 100k 1M 10M INPUT VOLTAGE – V 0 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 FREQUENCY – Hz WARM-UP TIME – Minutes

Figure 7. Input Bias Current vs. CMV Figure 8. Offset Voltage, RTI, Turn Figure 9. Gain vs. Frequency On Drift

–4– REV. C INPUT BIAS CURRENT – nA AMPLIFIER QUIESCENT CURRENT – mA INPUT VOLTAGE RANGE – V VOS FROM FINAL VALUE – V INPUT BIAS CURRENT – nA OUTPUT VOLTAGE SWING – V GAIN – V/V INPUT BIAS CURRENT – nA OUTPUT VOLTAGE SWING – V p-p, –140 30 160 G = 500 –VS = –15V dc+ –120 140 G = 500 1V p-p SINEWAVEG = 100 –100 120 G = 1 100 –80 G = 500 G = 1, 100 –60 G = 100 –40 G = 100 - G = 1000 40 G = 1 –20 BANDWIDTH LIMITED 20000110 100 1k 10k 100k 1M 10M 1k 10k 100k 1M 10 100 1k 10k 100k FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz

Figure 10. CMRR vs. Frequency RTI, Figure 11. Large Signal Frequency Figure 12. Positive PSRR vs. Zero to 1k Source Imbalance Response Frequency

160 1000 100k –VS = –15V dc+ G = 500 1V p-p SINEWAVE 120 100 G = 1 10k 100 G = 10 80 10 1000 G = 100 60 G = 100, 1000 G = 1000 40 1 100 G = 1 0 0.1 10 10 100 1k 10k 100k 1 10 100 1k 10k 100k 0.1 1 10 100 10k 100k FREQUENCY – Hz FREQUENCY – Hz FREQUENCY – Hz

Figure 13. Negative PSRR vs. Figure 14. RTI Noise Spectral Figure 15. Input Current Noise Frequency Density vs. Gain

–12 TO 12 1% 0.1% 0.01% –8 TO 8 –4 TO 4

OUTPUT

STEP –V 4 TO –4 8 TO –8 1% 0.1% 0.01% 12 TO –120510 15 20 SETTLING TIME – s

Figure 16. Low Frequency Voltage Figure 17. Low Frequency Voltage Figure 18. Settling Time, Gain = 1 Noise, G = 1 (System Gain = 1000) Noise, G = 1000 (System Gain =

100,000)

REV. C –5–

POWER SUPPLY REJECTION – dB CMRR – dB VOLT NSD – nV/ Hz FULL-POWER RESPONSE – V p-p CURRENT NOISE SPECTRAL DENSITY – fA/ Hz POWER SUPPLY REJECTION – dB, –12 TO 12 1% 0.1% 0.01% –8 TO 8 –4 TO 4

OUTPUT

STEP –V 4 TO –4 8 TO –8 1% 0.01% 12 TO –12 0.1% 0 5 10 15 20 SETTLING TIME – s

Figure 19. Large Signal Pulse Figure 20. Settling Time Gain = 100 Figure 21. Large Signal Pulse Response and Settling Time, G = 1 Response and Settling Time, G = 100

–12 TO 12 1% 0.1% 0.01% –8 TO 8 –4 TO 4

OUTPUT

STEP –V 4 TO –4 8 TO –8 0.01% 1% 0.1%12 TO –120510 15 20 SETTLING TIME – s

Figure 22. Range Signal Pulse Figure 23. Settling Time Gain = 1000 Figure 24. Large Signal Pulse Response and Settling Time, Response and Settling Time, G = 500 G = 1000

–6– REV. C, 10k 1k 10k 1% 10T 1% INPUT +VS VOUT 20V p-p 100k 1% RG1 G = 100 G = 200 AD624 G = 500 1k 500 200 0.1% 0.1% 0.1% RG2 –VS

Figure 25. Settling Time Test Circuit

THEORY OF OPERATION The AD524 should be considered in applications that require The AD624 is a monolithic instrumentation amplifier based on protection from severe input overload. If this is not possible, a modification of the classic three-op-amp instrumentation external protection resistors can be put in series with the inputs amplifier. Monolithic construction and laser-wafer-trimming of the AD624 to augment the internal (50 Ω) protection resis- allow the tight matching and tracking of circuit components and tors. This will most seriously degrade the noise performance. the high level of performance that this circuit architecture is ca- For this reason the value of these resistors should be chosen to pable of. be as low as possible and still provide 10 mA of current limiting A preamp section (Q1–Q4) develops the programmed gain by under maximum continuous overload conditions. In selecting the use of feedback concepts. Feedback from the outputs of A1 the value of these resistors, the internal gain setting resistor and and A2 forces the collector currents of Q1–Q4 to be constant the 1.2 volt drop need to be considered. For example, to pro- thereby impressing the input voltage across R . tect the device from a continuous differential overload of 20 VG at a gain of 100, 1.9 kΩ of resistance is required. The internal The gain is set by choosing the value of RG from the equation, gain resistor is 404 Ω; the internal protect resistor is 100 Ω. 40 k Gain = R + 1. The value of RG also sets the transconduct- There is a 1.2 V drop across D1 or D2 and the base-emitter G junction of either Q1 and Q3 or Q2 and Q4 as shown in Figure ance of the input preamp stage increasing it asymptotically to 27, 1400 Ω of external resistance would be required (700 Ω in the transconductance of the input transistors as RG is reduced series with each input). The RTI noise in this case would be for larger gains. This has three important advantages. First, this approach allows the circuit to achieve a very high open loop gain 4 KTRext +(4 nV / Hz) 2 = 6.2 nV / Hz of 3 × 108 at a programmed gain of 1000 thus reducing gain +VS related errors to a negligible 3 ppm. Second, the gain bandwidth product which is determined by C3 or C4 and the input trans- I1 I2 50A VB 50A R52 conductance, reaches 25 MHz. Third, the input voltage noise 10k SENSE reduces to a value determined by the collector current of the A1 A2 input transistors for an RTI noise of 4 nV/√Hz at G ≥ 500. C3 C4 R5310k +VS R57 A3 VO 50 20k Q1, Q3 R56 Q2, R54+VS –IN RG RG 20k Q4 10k 10012R55 16.2k 10k 200 80.2AD624 1F 13 REF 500 1/2 50A 500 I4 AD712 RG 1F 1/2 124 50A 2 9.09k AD712 4445 200 50 16.2k 225.3 +IN G500 G1, 100, 200 1F 100–VS 1k –VS –V 100 S 1.62M 1.82k

Figure 27. Simplified Circuit of Amplifier; Gain Is Defined

as (R56 + R57)/(RG) + 1. For a Gain of 1, RG Is an Open

Figure 26. Noise Test Circuit Circuit.

INPUT CONSIDERATIONS INPUT OFFSET AND OUTPUT OFFSET Under input overload conditions the user will see RG + 100 Ω Voltage offset specifications are often considered a figure of and two diode drops (~1.2 V) between the plus and minus merit for instrumentation amplifiers. While initial offset may inputs, in either direction. If safe overload current under all be adjusted to zero, shifts in offset voltage due to temperature conditions is assumed to be 10 mA, the maximum overload variations will cause errors. Intelligent systems can often correct voltage is ~ ±2.5 V. While the AD624 can withstand this con- for this factor with an autozero cycle, but there are many small- tinuously, momentary overloads of ±10 V will not harm the signal high-gain applications that don’t have this capability. device. On the other hand the inputs should never exceed the Voltage offset and offset drift each have two components; input supply voltage. and output. Input offset is that component of offset that is

REV. C –7–

, directly proportional to gain i.e., input offset as measured at Table I. the output at G = 100 is 100 times greater than at G = 1. Output offset is independent of gain. At low gains, output offset TemperatureGain Coefficient Pin 3 drift is dominant, while at high gains input offset drift domi- (Nominal) (Nominal) to Pin Connect Pins nates. Therefore, the output offset voltage drift is normally specified as drift at G = 1 (where input effects are insignificant), 1 –0 ppm/°C – – while input offset voltage drift is given by drift specification at a 100 –1.5 ppm/°C 13 – high gain (where output offset effects are negligible). All input- 125 –5 ppm/°C 13 11 to 16 related numbers are referred to the input (RTI) which is to say 137 –5.5 ppm/°C 13 11 to 12 that the effect on the output is “G” times larger. Voltage offset 186.5 –6.5 ppm/°C 13 11 to 12 to 16 vs. power supply is also specified at one or more gain settings 200 –3.5 ppm/°C 12 – and is also RTI. 250 –5.5 ppm/°C 12 11 to 13 333 –15 ppm/°C 12 11 to 16 By separating these errors, one can evaluate the total error inde- 375 –0.5 ppm/°C 12 13 to 16 pendent of the gain setting used. In a given gain configura- 500 –10 ppm/°C 11 – tion both errors can be combined to give a total error referred to 624 –5 ppm/°C 11 13 to 16 the input (R.T.I.) or output (R.T.O.) by the following formula: 688 –1.5 ppm/°C 11 11 to 12; 13 to 16 Total Error R.T.I. = input error + (output error/gain) 831 +4 ppm/°C 11 16 to 12 Total Error R.T.O. = (Gain × input error) + output error 1000 0 ppm/°C 11 16 to 12; 13 to 11 As an illustration, a typical AD624 might have a +250 µV out- Pins 3 and 16 programs the gain according to the formula put offset and a –50 µV input offset. In a unity gain configura- tion, the total output offset would be 200 µV or the sum of the 40kRG = two. At a gain of 100, the output offset would be –4.75 mV G −1 or: +250 µV + 100 (–50 µV) = –4.75 mV. (see Figure 29). For best results RG should be a precision resis- tor with a low temperature coefficient. An external RG affects both The AD624 provides for both input and output offset adjust- gain accuracy and gain drift due to the mismatch between it and ment. This optimizes nulling in very high precision applications the internal thin-film resistors R56 and R57. Gain accuracy is and minimizes offset voltage effects in switched gain applica- determined by the tolerance of the external RG and the absolute tions. In such applications the input offset is adjusted first at the accuracy of the internal resistors (±20%). Gain drift is determined highest programmed gain, then the output offset is adjusted at by the mismatch of the temperature coefficient of RG and the tem- G = 1. perature coefficient of the internal resistors (–15 ppm/°C typ), GAIN and the temperature coefficient of the internal interconnections. The AD624 includes high accuracy pretrimmed internal +VS gain resistors. These allow for single connection program- –INPUT ming of gains of 1, 100, 200 and 500. Additionally, a variety RG1 1.5k of gains including a pretrimmed gain of 1000 can be achieved OR 2.105k AD624 VOUT through series and parallel combinations of the internal resis- 1k tors. Table I shows the available gains and the appropriate RG2 REFERENCE pin connections and gain temperature coefficients. +INPUT 40.000 The gain values achieved via the combination of internal –V G = + 1 = 20 20%S 2.105 resistors are extremely useful. The temperature coefficient of the Figure 29. Operating Connections for G = 20 gain is dependent primarily on the mismatch of the temperature coefficients of the various internal resistors. Tracking of these The AD624 may also be configured to provide gain in the out- resistors is extremely tight resulting in the low gain TCs shown put stage. Figure 30 shows an H pad attenuator connected to in Table I. the reference and sense lines of the AD624. The values of R1, R2 and R3 should be selected to be as low as possible to mini- If the desired value of gain is not attainable using the inter- mize the gain variation and reduction of CMRR. Varying R2 nal resistors, a single external resistor can be used to achieve will precisely set the gain without affecting CMRR. CMRR is any gain between 1 and 10,000. This resistor connected between determined by the match of R1 and R3. +VS

INPUT

OFFSET +VS R1 –INPUT 10k NULL –INPUT 6k RG1 RG1 R2 G = 100 G = 100 5k G = 200 AD624 VOUT G = 200 AD624 VOUT G = 500 OUTPUT G = 500

RL

RG2 SIGNAL RG2 +INPUT COMMON +INPUT R3 –VS –V 6kS (R2||20k) + R1 + R3) Figure 28. Operating Connections for G = 200 G = (R2||20k) (R1 + R2 + R3) || RL 2k Figure 30. Gain of 2500 –8– REV. C, NOISE +VS The AD624 is designed to provide noise performance near the theoretical noise floor. This is an extremely important design criteria as the front end noise of an instrumentation amplifier is the ultimate limitation on the resolution of the data acquisition AD624 system it is being used in. There are two sources of noise in an LOAD instrument amplifier, the input noise, predominantly generated by the differential input stage, and the output noise, generated –V TOS by the output amplifier. Both of these components are present POWER

SUPPLY

at the input (and output) of the instrumentation amplifier. At GROUND the input, the input noise will appear unaltered; the output c. AC-Coupled noise will be attenuated by the closed loop gain (at the output, the output noise will be unaltered; the input noise will be ampli- Figure 31. Indirect Ground Returns for Bias Currents fied by the closed loop gain). Those two noise sources must be Although instrumentation amplifiers have differential inputs, root sum squared to determine the total noise level expected at there must be a return path for the bias currents. If this is not the input (or output). provided, those currents will charge stray capacitances, causing The low frequency (0.1 Hz to 10 Hz) voltage noise due to the the output to drift uncontrollably or to saturate. Therefore, output stage is 10 µV p-p, the contribution of the input stage is when amplifying “floating” input sources such as transformers 0.2 µV p-p. At a gain of 10, the RTI voltage noise would be and thermocouples, as well as ac-coupled sources, there must 2 still be a dc path from each input to ground, (see Figure 31). 1021µV p-p, + (0.2 ) . The RTO voltage noise would beG COMMON-MODE REJECTION Common-mode rejection is a measure of the change in output 10.2 µV p-p, 102 + (0.2(G )) . These calculations hold for voltage when both inputs are changed by equal amounts. These applications using either internal or external gain resistors. specifications are usually given for a full-range input voltage change and a specified source imbalance. “Common-Mode INPUT BIAS CURRENTS Rejection Ratio” (CMRR) is a ratio expression while “Common- Input bias currents are those currents necessary to bias the input Mode Rejection” (CMR) is the logarithm of that ratio. For transistors of a dc amplifier. Bias currents are an additional example, a CMRR of 10,000 corresponds to a CMR of 80 dB. source of input error and must be considered in a total error In an instrumentation amplifier, ac common-mode rejection is budget. The bias currents when multiplied by the source resis- only as good as the differential phase shift. Degradation of ac tance imbalance appear as an additional offset voltage. (What is common-mode rejection is caused by unequal drops across of concern in calculating bias current errors is the change in bias differing track resistances and a differential phase shift due to current with respect to signal voltage and temperature.) Input varied stray capacitances or cable capacitances. In many appli- offset current is the difference between the two input bias cur- cations shielded cables are used to minimize noise. This tech- rents. The effect of offset current is an input offset voltage whose nique can create common-mode rejection errors unless the magnitude is the offset current times the source resistance. shield is properly driven. Figures 32 and 33 shows active data guards which are configured to improve ac common-mode +VS rejection by “bootstrapping” the capacitances of the input cabling, thus minimizing differential phase shift. +VS –INPUT AD624 LOAD G = 200 RG AD624 VOUT2 –V TO AD711S POWER SUPPLY REFERENCE GROUND +INPUT –VS a. Transformer Coupled Figure 32. Shield Driver, G ≥ 100 +VS +VS –INPUT 100 AD712 RG1 AD624 AD624 VOUT LOAD 100 –VS RG2

REFERENCE

+INPUT –V TOS POWER –V SUPPLY S GROUND Figure 33. Differential Shield Driver b. Thermocouple REV. C –9–, GROUNDING “inside the loop” of an instrumentation amplifier to provide the Many data-acquisition components have two or more ground required current without significantly degrading overall perfor- pins which are not connected together within the device. These mance. The effects of nonlinearities, offset and gain inaccuracies grounds must be tied together at one point, usually at the sys- of the buffer are reduced by the loop gain of the IA output tem power supply ground. Ideally, a single solid ground would amplifier. Offset drift of the buffer is similarly reduced. be desirable. However, since current flows through the ground wires and etch stripes of the circuit cards, and since these paths REFERENCE TERMINAL have resistance and inductance, hundreds of millivolts can be The reference terminal may be used to offset the output by up generated between the system ground point and the data acqui- to ±10 V. This is useful when the load is “floating” or does not sition components. Separate ground returns should be provided share a ground with the rest of the system. It also provides a to minimize the current flow in the path from the most sensitive direct means of injecting a precise offset. It must be remem- points to the system ground point. In this way supply currents bered that the total output swing is ±10 volts, from ground, to and logic-gate return currents are not summed into the same be shared between signal and reference offset. return path as analog signals where they would cause measure- ment errors (see Figure 34). +VS

SENSE

VIN+ ANALOG P.S. DIGITAL P.S. +15V C –15V C +5V AD624 REF LOAD VIN– 0.1 0.1 0.1 0.1FFFF1F 1F 1F –VS DIG AD711 VOFFSET COM + AD624 AD583 DIGITAL Figure 36. Use of Reference Terminal to Provide Output SAMPLE AD574A DATA AND HOLD OUTPUT Offset

ANALOG

GROUND* SIGNAL When the IA is of the three-amplifier configuration it is neces- OUTPUT GROUND REFERENCE sary that nearly zero impedance be presented to the reference *IF INDEPENDENT, OTHERWISE RETURN AMPLIFIER REFERENCE TO MECCA AT ANALOG P.S. COMMON terminal. Any significant resistance, including those caused by PC layouts or other connection techniques, which appears

Figure 34. Basic Grounding Practice between the reference pin and ground will increase the gain of

Since the output voltage is developed with respect to the poten- the noninverting signal path, thereby upsetting the common- tial on the reference terminal an instrumentation amplifier can mode rejection of the IA. Inadvertent thermocouple connections solve many grounding problems. created in the sense and reference lines should also be avoided as they will directly affect the output offset voltage and output SENSE TERMINAL offset voltage drift. The sense terminal is the feedback point for the instrument In the AD624 a reference source resistance will unbalance the amplifier’s output amplifier. Normally it is connected to the CMR trim by the ratio of 10 kΩ/RREF. For example, if the refer- instrument amplifier output. If heavy load currents are to be ence source impedance is 1 Ω, CMR will be reduced to 80 dB drawn through long leads, voltage drops due to current flowing (10 kΩ/1 Ω = 80 dB). An operational amplifier may be used to through lead resistance can cause errors. The sense terminal can provide that low impedance reference point as shown in Figure be wired to the instrument amplifier at the load thus putting the 36. The input offset voltage characteristics of that amplifier will IxR drops “inside the loop” and virtually eliminating this error add directly to the output offset voltage performance of the source. instrumentation amplifier. V+ An instrumentation amplifier can be turned into a voltage-to- (SENSE) current converter by taking advantage of the sense and reference OUTPUT terminals as shown in Figure 37. V + CURRENTIN BOOSTER AD624 X1 SENSE +INPUT RL R1 VIN– +VX– (REF) AD624 IL V– –INPUT AD711

Figure 35. AD624 Instrumentation Amplifier with Output REF A2 Current Booster

V V Typically, IC instrumentation amplifiers are rated for a full IL = X = IN 1 + 40.000 LOADR1 R1 RG ±10 volt output swing into 2 kΩ. In some applications, how- ever, the need exists to drive more current into heavier loads. Figure 37. Voltage-to-Current Converter Figure 35 shows how a current booster may be connected –10– REV. C, –IN 1 16

OUTPUT

50 OFFSET G = 100 G = 200 G = 500 +IN 2 80.2 15 TRIM K1 K2 K3

NC

3 14 R24445.7 10k

INPUT

OFFSET 4 13 TRIM 20k VB 20k 225.3 RELAY

SHIELDS

R1 5 12 10k 10k 10k 10k 124 6 11 +5V 10k –VS 7 10 K1 K2 K3 AD624 +VS89OUT D1 D2 D3 1F C1 C2 35V ANALOG K1 – K3 = COMMON THERMOSEN DM2C 4.5V COIL D1 – D3 = IN4148 INPUTS A GAIN Y0 RANGE B 74LS138 Y1 7407N DECODER BUFFER 10F GAIN TABLE Y2 DRIVERABGAIN001000150010200111+5V

LOGIC COMMON Figure 38. Gain Programmable Amplifier

By establishing a reference at the “low” side of a current setting symmetrical bipolar transmission is ideal in this application. The resistor, an output current may be defined as a function of input multiplying DAC’s advantage is that it can handle inputs of voltage, gain and the value of that resistor. Since only a small either polarity or zero without affecting the programmed gain. current is demanded at the input of the buffer amplifier A2, the The circuit shown uses an AD7528 to set the gain (DAC A) and forced current IL will largely flow through the load. Offset and to perform a fine adjustment (DAC B). drift specifications of A2 must be added to the output offset and drift specifications of the IA. (+INPUT) 50 –IN 1 16 OUTPUT PROGRAMMABLE GAIN (–INPUT) 50 OFFSET Figure 38 shows the AD624 being used as a software program- +IN 2 80.2 15 NULLTO –V mable gain amplifier. Gain switching can be accomplished with 3 14 10k mechanical switches such as DIP switches or reed relays. It INPUT 4445.7OFFSET should be noted that the “on” resistance of the switch in series NULL 4 1320k VB 20k 225.3 with the internal gain resistor becomes part of the gain equation 10k 5 12 and will have an effect on gain accuracy. 10k 10k 124 6 11 A significant advantage in using the internal gain resistors in a 10k 10k programmable gain configuration is the minimization of thermo- –VS 7 10 couple signals which are often present in multiplexed data AD624+VS89VOUT acquisition systems. 1F 35V If the full performance of the AD624 is to be achieved, the user 10pFVVGND must be extremely careful in designing and laying out his circuit SS DD to minimize the remaining thermocouple signals. +VS The AD624 can also be connected for gain in the output stage. 39.2k 1k Figure 39 shows an AD547 used as an active attenuator in the AD711 28.7k 1k output amplifier’s feedback loop. The active attenuation pre- –VS 316k 1k sents a very low impedance to the feedback resistors therefore AD7590 minimizing the common-mode rejection ratio degradation. Another method for developing the switching scheme is to use a A1 A2 A3 A4 WR DAC. The AD7528 dual DAC which acts essentially as a pair of switched resistive attenuators having high analog linearity and Figure 39. Programmable Output Gain

REV. C –11–

, 50 In many applications complex software algorithms for autozero+INPUT (–INPUT) applications are not available. For these applications Figure 42 provides a hardware solution. G = 100 AD624 225.3 +V G = 200 4445.7 SVB 10k 15 16 RG G = 500 1 80.2 20k 10k 14 RG AD624 V1 OUTV RG OUT 13 0.1F LOW 9 10 CH 2 20k 10k LEAKAGE 10k RG2 1k –INPUT 50 –V (+INPUT) S AD542 12 11 +VS 1/2 AD712 DAC A

VDD

DATA DB0 VSS AD7510DIKD INPUTS DB7 256:1 GND CS AD7528 A1 A2 A3 A4 WR 200s DAC A/DAC B 1/2 ZERO PULSE DAC B AD712

Figure 42. Autozero Circuit

The microprocessor controlled data acquisition system shown in Figure 43 includes includes both autozero and autogain capabil-

Figure 40. Programmable Output Gain Using a DAC ity. By dedicating two of the differential inputs, one to ground

and one to the A/D reference, the proper program calibration AUTOZERO CIRCUITS cycles can eliminate both initial accuracy errors and accuracy In many applications it is necessary to provide very accurate errors over temperature. The autozero cycle, in this application, data in high gain configurations. At room temperature the offset converts a number that appears to be ground and then writes effects can be nulled by the use of offset trimpots. Over the that same number (8 bit) to the AD624 which eliminates the operating temperature range, however, offset nulling becomes a zero error since its output has an inverted scale. The autogain problem. The circuit of Figure 41 shows a CMOS DAC operat- cycle converts the A/D reference and compares it with full scale. ing in the bipolar mode and connected to the reference terminal A multiplicative correction factor is then computed and applied to provide software controllable offset adjustments. to subsequent readings. +VS –INPUT

RG

RG 21 VREF G = 100 AD583 G = 200 AD624 VOUT AD7507 AD624 VIN AD574A G = 500 AGND RG2 +INPUT RG1 –V A0 A2 39kSVEN A1 –V –V REF

REF

S 20k 20k AD589 +VS R3 20k R5 R 20kMSB FB AD7524 DATA OUT1 C1 +VS R4 1/2 LATCH 10k INPUTS LSB 10k AD712 1/2 AD7524 1/2AD712 5k AD712 CS DECODE OUT2 1/2WR AD712 R6 5k CONTROL–VS GND MICRO- ADDRESS BUS PROCESSOR

Figure 41. Software Controllable Offset Figure 43. Microprocessor Controlled Data Acquisition System

–12– REV. C, WEIGH SCALE Figure 45 is an example of an ac bridge system with the AD630 Figure 44 shows an example of how an AD624 can be used to used as a synchronous demodulator. The oscilloscope photo- condition the differential output voltage from a load cell. The graph shows the results of a 0.05% bridge imbalance caused by 10% reference voltage adjustment range is required to accom- the 1 Meg resistor in parallel with one leg of the bridge. The top modate the 10% transducer sensitivity tolerance. The high trace represents the bridge excitation, the upper middle trace is linearity and low noise of the AD624 make it ideal for use in the amplified bridge output, the lower-middle trace is the out- applications of this type particularly where it is desirable to put of the synchronous demodulator and the bottom trace is the measure small changes in weight as opposed to the absolute filtered dc system output. value. The addition of an autogain/autotare cycle will enable the This system can easily resolve a 0.5 ppm change in bridge system to remove offsets, gain errors, and drifts making possible impedance. Such a change will produce a 6.3 mV change in the true 14-bit performance. low-pass filtered dc output, well above the RTO drifts and noise. +15V +15V The AC-CMRR of the AD624 decreases with the frequency of NOTE 2 the input signal. This is due mainly to the package-pin capaci-R3 +10V 10V 10% 10 tance associated with the AD624’s internal gain resistors. If R1 AD707 2N2219 AC-CMRR is not sufficient for a given application, it can be+5V 30k trimmed by using a variable capacitor connected to the amplifier’s AD584 +2.5V R2 SCALE RG2 pin as shown in Figure 45. 20k ERROR

ADJUST VBG

R3 1kHz +VS 10k BRIDGE

EXCITATION

10k 1k RG–INPUT 1 SENSE +10V FULL 1k G500 SCALE OUTPUT 1k AD624C G200 G = 1000 A/D 1k G100 AD624 CONVERTER OUT 1M RGRG 2 R5 2 3M REFERENCE 4–49pF +INPUT CERAMIC ac –VSR4 BALANCE 10k GAIN = 500 CAPACITOR ZERO R7 TRANSDUCER ADJUST 100k SEE NOTE 1 (FINE)

MODULATION

R6 INPUT 100k 2.5k ZERO ADJUST (COARSE)

PHASE

SHIFTER BA

NOTES

1. LOAD CELL TEDEA MODEL 1010 10kG. OUTPUT 2mV/V10%. 2.5k 2. R1, R2 AND R3 SELECTED FOR AD584. OUTPUT 10V 10%.

B

5k

Figure 44. AD624 Weigh Scale Application

10k MODULATED AC BRIDGE OUTPUT Bridge circuits which use dc excitation are often plagued by 10k SIGNAL–VS VOUT errors caused by thermocouple effects, l/f noise, dc drifts in the –V electronics, and line noise pickup. One way to get around these CARRIER

INPUT

problems is to excite the bridge with an ac waveform, amplify COMP AD630 +VS the bridge output with an ac amplifier, and synchronously demodulate the resulting signal. The ac phase and amplitude Figure 45. AC Bridge information from the bridge is recovered as a dc signal at the output of the synchronous demodulator. The low frequency system noise, dc drifts, and demodulator noise all get mixed to the carrier frequency and can be removed by means of a low- BRIDGE EXCITATION0V (20V/div) (A) pass filter. Dynamic response of the bridge must be traded off against the amount of attenuation required to adequately sup- AMPLIFIED BRIDGE0V OUTPUT (5V/div) (B) press these residual carrier components in the selection of the DEMODULATED BRIDGE filter. 0V OUTPUT (5V/div) (C) FILTER OUTPUT 2V 2V/div) (D) 0V

Figure 46. AC Bridge Waveforms REV. C –13–

, ERROR BUDGET ANALYSIS +VS To illustrate how instrumentation amplifier specifications are applied, we will now examine a typical case where an AD624 is +10V 10k required to amplify the output of an unbalanced transducer. RG1 Figure 47 shows a differential transducer, unbalanced by ≈5 Ω, 350 350 14-BITG = 100 ADC supplyinga0to 20 mV signal to an AD624C. The output of the AD624C 0 TO 2V IA feeds a 14-bit A to D converter witha0to 2 volt input volt- 350 350 F.S. age range. The operating temperature range is –25°C to +85°C. RG2 Therefore, the largest change in temperature ∆T within the –V operating range is from ambient to +85°C (85°C – 25°C = S 60°C.) In many applications, differential linearity and resolution are of prime importance. This would be so in cases where the absolute Figure 47. Typical Bridge Application value of a variable is less important than changes in value. In these applications, only the irreducible errors (20 ppm = 0.002%) are significant. Furthermore, if a system has an intelli- gent processor monitoring the A to D output, the addition of an autogain/autozero cycle will remove all reducible errors and may eliminate the requirement for initial calibration. This will also reduce errors to 0.002%. Table II. Error Budget Analysis of AD624CD in Bridge Application Effect on Effect on Absolute Absolute Effect AD624C Accuracy Accuracy on Error Source Specifications Calculation at TA = +25C at TA = +85C Resolution Gain Error ±0.1% ±0.1% = 1000 ppm 1000 ppm 1000 ppm – Gain Instability 10 ppm (10 ppm/°C) (60°C) = 600 ppm _ 600 ppm – Gain Nonlinearity ±0.001% ±0.001% = 10 ppm – – 10 ppm Input Offset Voltage ±25 µV, RTI ±25 µV/20 mV = ±1250 ppm 1250 ppm 1250 ppm – Input Offset Voltage Drift ±0.25 µV/°C (±0.25 µV/°C) (60°C)= 15 µV 15 µV/20 mV = 750 ppm – 750 ppm – Output Offset Voltage1 ±2.0 mV ±2.0 mV/20 mV = 1000 ppm 1000 ppm 1000 ppm – Output Offset Voltage Drift1 ±10 µV/°C (±10 µV/°C) (60°C) = 600 µV 600 µV/20 mV = 300 ppm – 300 ppm – Bias Current–Source ±15 nA (±15 nA)(5 Ω ) = 0.075 µV Imbalance Error 0.075 µV/20mV = 3.75 ppm 3.75 ppm 3.75 ppm – Offset Current–Source ±10 nA (±10 nA)(5 Ω) = 0.050 µV Imbalance Error 0.050 µV/20 mV = 2.5 ppm 2.5 ppm 2.5 ppm – Offset Current–Source ±10 nA (10 nA) (175 Ω) = 1.75 µV Resistance Error 1.75 µV/20 mV = 87.5 ppm 87.5 ppm 87.5 ppm – Offset Current–Source ±100 pA/°C (100 pA/°C) (175 Ω) (60°C) = 1 µV Resistance–Drift 1 µV/20 mV = 50 ppm – 50 ppm – Common-Mode Rejection 115 dB 115 dB = 1.8 ppm × 5 V = 9 µV5Vdc 9 µV/20 mV = 444 ppm 450 ppm 450 ppm – Noise, RTI (0.1 Hz–10 Hz) 0.22 µV p-p 0.22 µV p-p/20 mV = 10 ppm _ – 10 ppm Total Error 3793.75 ppm 5493.75 ppm 20 ppm

NOTE

1Output offset voltage and output offset voltage drift are given as RTI figures. For a comprehensive study of instrumentation amplifier design and applications, refer to the Instrumentation Amplifier Application Guide, available free from Analog Devices. –14– REV. C,

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm).

Side-Brazed Solder Lid Ceramic DIP

(D-16) 0.005 (0.13) MIN 0.080 (2.03) MAX 16 9 0.310 (7.87) 0.220 (5.59) 1 8 0.320 (8.13) PIN 1 0.290 (7.37) 0.840 (21.34) MAX 0.060 (1.52) 0.015 (0.38) 0.200 (5.08) MAX 0.150 0.200 (5.08) (3.81) 0.125 (3.18) MAX 0.015 (0.38) 0.023 (0.58) 0.100 0.070 (1.78) SEATING (2.54) PLANE 0.008 (0.20)0.014 (0.36) 0.030 (0.76)

BSC REV. C –15–

, –16– PRINTED IN U.S.A. C805d–0–7/99]

15