Download: a Loop-Powered 4–20 mASensor Transmitter AD693

a Loop-Powered 4–20 mASensor Transmitter

AD693

FEATURES FUNCTIONAL BLOCK DIAGRAM Instrumentation Amplifier Front End Loop-Powered Operation Precalibrated 30 mV or 60 mV Input Spans Independently Adjustable Output Span and Zero Precalibrated Output Spans: 4–20 mA Unipolar 0–20 mA Unipolar 1268mA Bipolar Precalibrated 100 V RTD Interface 6.2 V Reference with Up to 3.5 mA of Current Available Uncommitted Auxiliary Amp for Extra Flexibility Optional External Pass Transistor to Reduce Self-Heating Errors PRODUCT DESCRIPTION PRODUCT HIGHLIGHTS The AD693 is a monolithic signal conditioning circuit which 1. The AD693 is a complete monolithic low-level voltage-to- accepts low-level inputs from a variety of transducers to control a current loop signal conditioner. standard 4–20 mA, two-wire current loop. An on-chip voltage 2. Precalibrated output zero and span options include reference and auxiliary amplifier are provided for transducer 4–20 mA, 0–20 mA, and 12 ± 8 mA in two- and three-wire excitation; up to 3.5 mA of excitation current is available when the configurations. device is operated in the loop-powered mode. Alternatively, the device may be locally powered for three-wire applications when 3. Simple resistor programming adds a continuum of ranges 0–20 mA operation is desired. to the basic 30 mV and 60 mV input spans. Precalibrated 30 mV and 60 mV input spans may be set by 4. The common-mode range of the signal amplifier input simple pin strapping. Other spans from 1 mV to 100 mV may extends from ground to near the device’s operating voltage. be realized with the addition of external resistors. The auxiliary 5. Provision for transducer excitation includes a 6.2 V amplifier may be used in combination with on-chip voltages to reference output and an auxiliary amplifier which may be provide six precalibrated ranges for 100 Ω RTDs. Output span configured for voltage or current output and signal and zero are also determined by pin strapping to obtain the amplification. standard ranges: 4–20mA, 12 ± 8 mA and 0–20 mA. 6. The circuit configuration permits simple linearization of Active laser trimming of the AD693’s thin-film resistors result bridge, RTD, and other transducer signals. in high levels of accuracy without the need for additional 7. A monitored output is provided to drive an external pass adjustments and calibration. Total unadjusted error is tested on transistor. This feature off-loads power dissipation to every device to be less than 0.5% of full scale at +25°C, and less extend the temperature range of operation, enhance than 0.75% over the industrial temperature range. Residual reliability, and minimize self-heating errors. nonlinearity is under 0.05%. The AD693 also allows for the use of an external pass transistor to further reduce errors caused by 8. Laser-wafer trimming results in low unadjusted errors and self-heating. affords precalibrated input and output spans. For transmission of low-level signals from RTDs, bridges and 9. Zero and span are independently adjustable and noninteractive pressure transducers, the AD693 offers a cost-effective signal to accommodate transducers or user defined ranges. conditioning solution. It is recommended as a replacement for 10. Six precalibrated temperature ranges are available with a discrete designs in a variety of applications in process control, 100 Ω RTD via pin strapping. factory automation and system monitoring. The AD693 is packaged in a 20-pin ceramic side-brazed DIP, 20-pin Cerdip, and 20-pin LCCC and is specified over the –40°C to +85°C industrial temperature range. REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. otherwise under any patent or patent rights of Analog Devices. Tel: 617/329-4700 Fax: 617/326-8703, AD693–SPECIFICATIONS (@ +258C and VS = +24 V. Input Span = 30 mV or 60 mV. Output Span = 4–20 mA,RL = 250 V, VCM = 3.1 V, with external pass transistor unless otherwise noted.) Model AD693AD/AQ/AE Conditions Min Typ Max Units LOOP-POWERED OPERATION TOTAL UNADJUSTED ERROR1, 2 ±0.25 60.5 % Full Scale TMIN to TMAX ±0.4 60.75 % Full Scale 100 Ω RTD CALIBRATION ERROR3 (See Figure 17) ±0.5 ±2.0 °C LOOP POWERED OPERATION2 Zero Current Error4 Zero = 4 mA ±25 680 µA Zero = 12 mA ±40 6120 µA Zero = 0 mA5 +7 +35 +100 µA vs. Temp. Zero = 4 mA ±0.5 ±1.5 µA/°C Power Supply Rejection (RTI) 12 V ≤ VOP ≤ 36V6 ±3.0 65.6 µV/V0V≤ VCM ≤ 6.2 V Common-Mode Input Range (See Figure 3) 0 +VOP – 4 V6 V Common-Mode Rejection (RTI) 0 V ≤ VCM ≤ 6.2 V ±10 630 µV/V Input Bias Current7 +5 +20 nA TMIN to TMAX +7 +25 nA Input Offset Current7 VSIG = 0 ±0.5 63.0 nA Transconductance Nominal 30 mV Input Span 0.5333 A/V 60 mV Input Span 0.2666 A/V Unadjusted Error ±0.05 60.2 % vs. Common-Mode0V≤ VCM ≤ 6.2 V 30 mV Input Span ±0.03 ±0.04 %/V 60 mV Input Span ±0.05 ±0.06 %/V Error vs. Temp. ±20 ±50 ppm/°C Nonlinearity8 30 mV Input Span ±0.01 60.05 % of Span 60 mV Input Span ±0.02 60.07 % of Span OPERATIONAL VOLTAGE RANGE Operational Voltage, V 6OP +12 +36 V Quiescent Current Into Pin 9 +500 +700 µA OUTPUT CURRENT LIMIT +21 +25 +32 mA COMPONENTS OF ERROR SIGNAL AMPLIFIER9 Input Voltage Offset ±40 6200 µV vs. Temp ±1.0 ±2.5 µV/°C Power Supply Rejection 12 V ≤ VOP ≤ 36 V6 ±3.0 65.6 µV/V0V≤ VCM ≤ 6.2 V V/I CONVERTER9, 10 Zero Current Error Output Span = 4–20 mA ±30 ±80 µA Power Supply Rejection 12 V ≤ VOP ≤ 36 V6 ±1.0 ±3.0 µA/V Transconductance Nominal 0.2666 A/V Unadjusted Error ±0.05 ±0.2 % 6.200 V REFERENCE9, 12 Output Voltage Tolerance ±3 612 mV vs. Temp. ±20 ±50 ppm/°C Line Regulation 12 V ≤ VOP ≤ 36 V6 ±200 6300 µV/V Load Regulation11 0 mA ≤ IREF ≤ 3 mA ±0.3 60.75 mV/mA Output Current13 Loop Powered, (Figure 10) +3.0 +3.5 mA 3-Wire Mode, (Figure 15) +5.0 mA –2– REV. A,

Model AD693AD Conditions Min Typ Max Units AUXILIARY AMPLIFIER Common-Mode Range 0 +VOP – 4 V

6 V

Input Offset Voltage ±50 ±200 µV Input Bias Current +5 +20 nA Input Offset Current +0.5 ±3.0 nA Common-Mode Rejection 90 dB Power Supply Rejection 105 dB Output Current Range Pin IX OUT +0.01 +5 mA Output Current Error Pin VX – Pin IX ±0.005 % TEMPERATURE RANGE Case Operating14 TMIN to TMAX –40 +85 °C Storage –65 +150 °C NOTES

1 Total error can be significantly reduced (typically less than 0.1%) by trimming the zero current. The remaining unadjusted error sources are transconductance and nonlinearity. 2 The AD693 is tested as a loop powered device with the signal amp, V/I converter, voltage reference, and application voltages operating together. Specifications are valid for preset spans and spans between 30 mV and 60 mV. 3 Error from ideal output assuming a perfect 100 Ω RTD at 0 and +100°C. 4 Refer to the Error Analysis to calculate zero current error for input spans less than 30 mV. 5 By forcing the differential signal amplifier input sufficiently negative the 7 µA zero current can always be achieved. 6 The operational voltage (VOP) is the voltage directly across the AD693 (Pin 10 to 6 in two-wire mode, Pin 9 to 6 in local power mode). For example, VOP = VS – (ILOOP × RL) in two-wire mode (refer to Figure 10). 7Bias currents are not symmetrical with input signal level and flow out of the input pins. The input bias current of the inverting input increases with input signal volt- age, see Figure 2. 8 Nonlinearity is defined as the deviation of the output from a straight line connecting the endpoints as the input is swept over a 30 mV and 60 mV input span. 9 Specifications for the individual functional blocks are components of error that contribute to, and that are included in, the Loop Powered Operation specifications. 10 Includes error contributions of V/I converter and Application Voltages. 11Changes in the reference output voltage due to load will affect the Zero Current. A 1% change in the voltage reference output will result in an error of 1% in the value of the Zero Current. 12 If not used for external excitation, the reference should be loaded by approximately 1 mA (6.2 kΩ to common). 13 In the loop powered mode up to 5 mA can be drawn from the reference, however, the lower limit of the output span will be increased accordingly. 3.5 mA is the maximum current the reference can source while still maintaininga4mA zero. 14The AD693 is tested with a pass transistor so TA ≅ TC. Specifications subject to change without notice. Specifications shown in boldface are tested on all production units at final electrical test. Results from those tests are used to calculate outgoing quality levels. All min and max specifications are guaranteed, although only those shown in boldface are tested on all production units.

ABSOLUTE MAXIMUM RATINGS AD693 PIN CONFIGURATION Supply Voltage .+36 V (AD, AQ, AE Packages) Reverse Loop Current .200 mA Signal Amp Input Range .–0.3 V to VOP Reference Short Circuit to Common .Indefinite Auxiliary Amp Input Voltage Range .0.3 V to VOP Auxiliary Amp Current Output .10 mA Storage Temperature .–65°C to +150°C Lead Temperature, 10 sec Soldering .+300°C Max Junction Temperature .+150°C ORDERING GUIDE Package Package Model Description Option AD693AD Ceramic Side-Brazed DIP D-20 AD693AQ Cerdip Q-20 AD693AE Leadless Ceramic Chip E-20A Functional Diagram Carrier (LCCC) REV. A –3–

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AD693–Typical Characteristics

Figure 1. Maximum Load Resistance Figure 4. Bandwidth vs. Series Load Figure 7. Input Current Noise vs. vs. Power Supply Resistance Frequency Figure 2. Differential Input Current vs. Figure 5. Signal Amplifier PSRR vs. Figure 8. Input Voltage Noise vs. Input Signal Voltage Normalized to +IN Frequency Frequency Figure 3. Maximum Common-Mode Figure 6. CMRR (RTI) vs. Frequency Voltage vs. Supply –4– REV. A, FUNCTIONAL DESCRIPTION converter’s inverting input (Pin 12). Arranging the zero offset in The operation of the AD693 can be understood by dividing the this way makes the zero signal output current independent of circuit into three functional parts (see Figure 9). First, an input span. When the input to the signal amp is zero, the instrumentation amplifier front-end buffers and scales the low- noninverting input of the V/I is at 6.2 V. level input signal. This amplifier drives the second section, a V/I Since the standard offsets are laser trimmed at the factory, converter, which provides the 4-to-20mA loop current. The adjustment is seldom necessary except to accommodate the zero third section, a voltage reference and resistance divider, provides offset of the actual source. (See “Adjusting Zero.”) application voltages for setting the various “live zero” currents. In addition to these three main sections, there is an on-chip SIGNAL AMPLIFIER auxiliary amplifier which can be used for transducer excitation. The Signal Amplifier is an instrumentation amplifier used to buffer and scale the input to match the desired span. Inputs VOLTAGE-TO-CURRENT (V/I) CONVERTER applied to the Signal Amplifier (at Pins 17 and 18) are amplified The output NPN transistor for the V/I section sinks loop current and referred to the 6.2 V reference output in much the same way as when driven on by a high gain amplifier at its base. The input for the level translation occurs in the V/I converter. Signals from the this amplifier is derived from the difference in the outputs of the two preamplifiers are subtracted, the difference is amplified, and matched preamplifiers having gains, G2. This difference is caused the result is fed back to the upper preamp to minimize the to be small by the large gain, +A, and the negative feedback difference. Since the two preamps are identical, this minimum will through the NPN transistor and the loop current sampling resistor occur when the voltage at the upper preamp just matches the between IIN and Boost. The signal across this resistor is compared differential input applied to the Signal Amplifier at the left. to the input of the left preamp and servos the loop current until both signals are equal. Accurate voltage-to-current transformation Since the signal which is applied to the V/I is attenuated across is thereby assured. The preamplifiers employ a special design the two 800 Ω resistors before driving the upper preamp, it will which allows the active feedback amplifier to operate from the most necessarily be an amplified version of the signal applied between positive point in the circuit, I Pins 17 and 18. By changing this attenuation, you can controlIN. the span referred to the Signal Amplifier. To illustrate: a 75 mV The V/I stage is designed to have a nominal transconductance of signal applied to the V/I results in a 20 mA loop current. 0.2666 A/V. Thus, a 75 mV signal applied to the inputs of the Nominally, 15 mV is applied to offset the zero to 4 mA leaving a V/I (Pin 16, noninverting; Pin 12, inverting) results in a 60 mV range to correspond to the span. And, since the nominal full-scale output current of 20 mA. attenuation of the resistors connected to Pins 16, 15 and 14 is The current limiter operates as follows: the output of the feed- 2.00, a 30 mV input signal will be doubled to result in 20 mA of back preamp is an accurate indication of the loop current. This loop current. Shorting Pins 15 and 16 results in unity gain and output is compared to an internal setpoint which backs off the permits a 60 mV input span. Other choices of span may be drive to the NPN transistor when the loop current approaches implemented with user supplied resistors to modify the 25 mA. As a result, the loop and the AD693 are protected from the attenuation. (See section “Adjusting Input Span.”) consequences of voltage overdrive at the V/I input. The Signal Amplifier is specially designed to accommodate a VOLTAGE REFERENCE AND DIVIDER large common-mode range. Common-mode signals anywhere up A stabilized bandgap voltage reference and laser-trimmed to and beyond the 6.2 V reference are easily handled as long as resistor divider provide for both transducer excitation as well as VIN is sufficiently positive. The Signal Amplifier is biased with precalibrated offsets for the V/I converter. When not used for respect to VIN and requires about 3.5 volts of headroom. The external excitation, the reference should be loaded by approxi- extended range will be useful when measuring sensors driven, mately 1 mA (6.2 kΩ to common). for example, by the auxiliary amplifier which may go above the 6.2 V potential. In addition, the PNP input stage will continue The 4 mA and 12 mA taps on the resistor divider correspond to to operate normally with common-mode voltages of several –15 mV and –45 mV, respectively, and result in a live zero of hundred mV, negative, with respect to common. This feature 4 mA or 12 mA of loop current when connected to the V/I accommodates self-generating sensors, such as thermocouples, which may produce small negative normal-mode signals as well as common-mode noise on “grounded” signal sources. AUXILIARY AMPLIFIER The Auxiliary Amplifier is included in the AD693 as a signal conditioning aid. It can be used as an op amp in noninverting applications and has special provisions to provide a controlled current output. Designed with a differential input stage and an unbiased Class A output stage, the amplifier can be resistively loaded to common with the self-contained 100 Ω resistor or with a user supplied resistor. As a functional element, the Auxiliary Amplifier can be used in dynamic bridges and arrangements such as the RTD signal conditioner shown in Figure 17. It can be used to buffer, amplify and combine other signals with the main Signal Amplifier. The Figure 9. Functional Flock Diagram Auxiliary Amplifier can also provide other voltages for excitation REV. A –5–, if the 6.2 V of the reference is unsuitable. Configured as a simple USING AN EXTERNAL PASS TRANSISTOR follower, it can be driven from a user supplied voltage divider The emitter of the NPN output section, IOUT, of the AD693 is or the precalibrated outputs of the AD693 divider (Pins 3 and usually connected to common and the negative loop connection 4) to provide a stiff voltage output at less than the 6.2 level, or (Pins 7 to 6). Provision has been made to reconnect IOUT to the by incorporating a voltage divider as feedback around the amplifier, base of a user supplied NPN transistor as shown in Figure 11. one can gain-up the reference to levels higher than 6.2 V. If This permits the majority of the power dissipation to be moved large positive outputs are desired, IX, the Auxiliary Amplifier off chip to enhance performance, improve reliability, and extend output current supply, should be strapped to either VIN or the operating temperature range. An internal hold-down resistor Boost. Like the Signal Amplifier, the Auxiliary requires about of about 3k is connected across the base emitter of the external 3.5 V of headroom with respect to VIN at its input and about2Vtransistor. of difference between IX and the voltage to which VX is required The external pass transistor selected should have a BVCEO greaterto swing. than the intended supply voltage with a sufficient power rating for The output stage of the Auxiliary Amplifier is actually a high continuous operation with 25 mA current at the supply voltage. gain Darlington transistor where IX is the collector and VX is the Ft should be in the 10 MHz to 100 MHz range and β should be emitter. Thus, the Auxiliary Amplifier can be used as a V/I greater than 10 at a 20 mA emitter current. Some transistors converter when configured as a follower and resistively loaded. that meet this criteria are the 2N1711 and 2N2219A. Heat IX functions as a high-impedance current source whose current sinking the external pass transistor is suggested. is equal to the voltage at VX divided by the load resistance. For The pass transistor option may also be employed for other example, using the onboard 100 Ω resistor and the 75 mV or applications as well. For example, I 150 mV application voltages, either a 750 µA or 1.5 mA current OUT can be used to drive an LED connected to Common, thus providing a local monitor of source can be set up for transducer excitation. loop fault conditions without reducing the minimum compliance The IX terminal has voltage compliance within2Vof VX. If the voltage. Auxiliary Amplifier is not to be used, then Pin 2, the noninverting input, should be grounded. ADJUSTING ZERO In general, the desired zero offset value is obtained by REVERSE VOLTAGE PROTECTION FEATURE connecting an appropriate tap of the precision reference/voltage In the event of a reverse voltage being applied to the AD693 divider network to the inverting terminal of the V/I converter. through a current-limited loop (limited to 200 mA), an internal As shown in Figure 9, precalibrated taps at Pins 14, 13 and 11 shunt diode protects the device from damage. This protection result in zero offsets of 0 mA, 4 mA and 12 mA, respectively, mode avoids the compliance voltage penalty which results from when connected to Pin 12. The voltages which set the 4 mA and a series diode that must be added if reversal protection is 12 mA zero operating points are 15 mV and 45 mV negative required in high-current loops. with respect to 6.2 V, and they each have a nominal source resistance of 450 Ω. While these voltages are laser trimmed to

Applying the AD693 high accuracy, they may require some adjustment to

accommodate variability between sensors or to provide CONNECTIONS FOR BASIC OPERATION additional ranges. You can adjust zero by pulling up or down on Figure 10 shows the minimal connections for basic operation: the selected zero tap, or by making a separate voltage divider to 0–30 mV input span, 4–20 mA output span in the two-wire, drive the zero pin. loop-powered mode. If not used for external excitation, the 6.2 V reference should be loaded by approximately 1 mA The arrangement of Figure 12 will give an approximately linear (6.2 kΩ to common). adjustment of the precalibrated options with fixed limits. To find the proper resistor values, first select IA, the desired range Figure 10. Minimal Connection for 0–30 mV Unipolar Input, 4–20 mA Output –6– REV. A, Figure 11. Using an External Pass Transistor to Minimize Self-Heating Errors of adjustment of the output current from nominal. Substitute 0-to-75 mV signal in the 0-to-20 mA mode). The gain of this this value in the appropriate formula below for adjustment at the amplifier is trimmed to 2.00 so that an input signal ranging from 4 mA tap. 0-to-30 mV will drive the V/I section to produce 4-to -20 mA. R = (1.6 V/I ) – 400 Ω and Joining P1 and P2 (Pins 15 and 16) will reduce the Signal Ampli-Z1 A fier gain to one, thereby requiring a 60 mV signal to drive the V/I RZ2 = RZ1 × 3.1 V/(15 mV + IA × 3.75 Ω) to a full 20 mA span. Use a similar connection with the following resistances for To produce spans less than 30 mV, an external resistor, RS1, can adjustments at the 12 mA tap. be connected between P1 and 6.2 V. The nominal value is given RZ1 = (4.8 V/IA) – 400 Ω and by: RZ2 = RZ1 × 3.1 V/(45 mV + IA × 3.75 Ω) RS1 = 400 Ω ± 30 mVThese formulae take into account the 10% tolerance of tap −1 resistance and insure a minimum adjustment range of IA. For S example, choosing I = 200 µA will give a zero adjustment range where S is the desired span. For example, to change the span toA of ±1% of the 20 mA full-scale output. At the 4 mA tap the 6 mV a value of: maximum value of: RS1 = 400 Ω = 100ΩR30 mVZ1 = 1.6 V/200 µA – 400 Ω = 7.6 kΩ and −1 RZ2 = 7.6 kΩ × 3.1 V/(15 mV + 200 µA × 3.75Ω6mV ) = 1.49 MΩ is required. Since the internal, 800 Ω gain setting resistors exhibit an absolute tolerance of 10%, RS1 should be provided with up to ±10% range of adjustment if the span must be well controlled. For spans between 30 mV and 60 mV a resistor RS2 should be connected between P1 and P2. The nominal value is given by: 60 mV 400 Ω 1− S RS2 = 30 mV −1

S

For example, to change the span to 40 mV, a value of: 60 mV 400 Ω 1− 40 mV RS2 = = 800 Ω30 mV −1 40 mV Figure 12. Optional 4 mA Zero Adjustment (12 mA Trim Available Also) is required. Remember that this is a nominal value and may These can be rounded down to more convenient values of require adjustment up to ±10%. In many applications the span 7.5 kΩ and 1.3 MΩ, which will result in an adjustment range must be adjusted to accommodate individual variations in the comfortably greater than ±200 µA. sensor as well as the AD693. The span changing resistor should, therefore, include enough adjustment range to handle both the ADJUSTING INPUT SPAN sensor uncertainty and the absolute resistance tolerance of P1 Input Span is adjusted by changing the gain of the Signal and P2. Note that the temperature coefficient of the internal Amplifier. This amplifier provides a 0-to-60 mV signal to the resistors is nominally –17 ppm/°C, and that the external V/I section to produce the 4-to-20 mA output span (or a resistors should be comparably stable to insure good tempera- ture performance. REV. A –7–, An alternative arrangement, allowing wide range span adjust- ment between two set ranges, is shown in Figure 13. RS1 and S RE2 = RD − 1.0024R S2 are calculated to be 90% of the values determined from the S − 60 mV previous formulae. The smallest value is then placed in series with the wiper of the 1.5 kΩ potentiometer shown in the figure. and RE1 = 412 RE2 For example, to adjust the span between 25 mV and 40 mV, RS1 Figure 14 shows a scheme for adjusting the modified span and and RS2 are calculated to be 2000 Ω and 800 Ω, respectively. 4 mA offset via RE3 and RE4. The trim procedure is to first The smaller value, 800 Ω, is then reduced by 10% to cover the connect both signal inputs to the 6.2 V Reference, set RE4 to possible ranges of resistance in the AD693 and that value is put zero and then adjust RE3 so that 4 mA flows in the current loop. in place. This in effect, creates a divider with the same ratio as the internal divider that sets the 4 mA zero level (–15 mV with respect to 6.2 V). As long as the input signal remains zero the voltage at Pin 12, the zero adjust, will remain at –15 mV with respect to 6.2 V. Figure 13. Wide Range Span Adjustment A number of other arrangements can be used to set the span as long as they are compatible with the pretrimmed noninverting gain of two. The span adjustment can even include thermistors or other sensitive elements to compensate the span of a sensor. Figure 14. Adjusting for Spans between 60 mV and In devising your own adjustment scheme, remember that you 100 mV (RE1 and RE2) with Fine-Scale Adjust (RE3 and RE4) should adjust the gain such that the desired span voltage at the After adjusting RE3 place the desired full scale (S) across the Signal Amplifier input translates to 60 mV at the output. Note signal inputs and adjust RE4 so that 20 mA flows in the current also that the full differential voltage applied to the V/I converter loop. An attenuated portion of the input signal is now added is 75 mV; in the 4-20 mA mode, –15 mV is applied to the into the V/I zero to maintain the 75 mV maximum differential. inverting input (zero pin) by the Divider Network and +60 mV If there is some small offset at the input to the Signal Amplifier, is applied to the noninverting input by the Signal Amplifier. In it may be necessary to repeat the two adjustments. the 0–20 mA mode, the total 75 mV must be applied by the Signal Amplifier. As a result, the total span voltage will be 25% LOCAL-POWERED OPERATION FOR 0–20 mA OUTPUT larger than that calculated for a 4-20 mA output. The AD693 is designed for local-powered, three-wire systems as Finally, the external resistance from P2 to 6.2 V should not be well as two-wire loops. All its usual ranges are available in three- made less than 1 kΩ unless the voltage reference is loaded to at wire operation, and in addition, the 0–20 mA range can be used. least 1.0 mA. (A simple load resistor can be used to meet this The 0-20 mA convention offers slightly more resolution and requirement if a low value potentiometer is desired.) In no case may simplify the loop receiver, two reasons why it is sometimes should the resistance from P2 to 6.2 V be less than 200 Ω. preferred. Input Spans Between 60 mV and 100 mV The arrangement, illustrated in Figure 15, results in a 0–20 mA Input spans of up to 100 mV can be obtained by adding an transmitter where the precalibrated span is 37.5 mV. Con- offset proportional to the output signal into the zero pin of the necting P1 to P2 will double the span to 75 mV. Sensor input V/I converter. This can be accomplished with two resistors and and excitation is unchanged from the two-wire mode except for adjusted via the optional trim scheme shown in Figure 14. The the 25% increase in span. Many sensors are ratiometric so that resistor divider formed by RE1 and RE2 from the output of the an increase in excitation can be used instead of a span Signal Amplifier modifies the differential input voltage range adjustment. applied to the V/I converter. In the local-powered mode, increases in excitation are made In order to determine the fixed resistor values, RE1 and RE2, first easier. Voltage compliance at the IIN terminal is also improved; measure the source resistance (RD) of the internal divider network. the loop voltage may be permitted to fall to 6 volts at the This can be accomplished (power supply disconnected) by AD693, easing the trade-off between loop voltage and loop measuring the resistance between the 4 mA of offset (Pin 13) resistance. Note that the load resistor, RL, should meter the and common (Pin 6) with the 6.2 V reference (Pin 14) connected current into Pin 10, IIN, so as not to confuse the loop current to common. The measured value, RD, is then used to calculate with the local power supply current. RE1 and RE2 via the following formula: –8– REV. A,

Figure 15. Local Powered Operation with 0–20 mA Output

OPTIONAL INPUT FILTERING INTERFACING PLATINUM RTDS Input filtering is recommended for all applications of the The AD693 has been specially configured to accept inputs from AD693 due to its low input signal range. An RC filter network 100 Ω Platinum RTDs (Resistance Temperature Detectors). at each input of the signal amplifier is sufficient, as shown in Referring to Figure 17, the RTD and the temperature stable Figure 16. In the case of a resistive signal source it may be 100 Ω resistor form a feedback network around the Auxiliary necessary only to add the capacitors, as shown in Figure 18. Amplifier resulting in a noninverting gain of (1 + RT/100 Ω), The capacitors should be placed as close to the AD693 as where RT is the temperature dependent resistance of the RTD. possible. The value of the filter resistors should be kept low to The noninverting input of the Auxiliary Amplifier (Pin 2) is minimize errors due to input bias current. Choose the 3 dB then driven by the 75 mV signal from the Voltage Divider (Pin point of the filter high enough so as not to compromise the 4). When the RTD is at 0, its 100 Ω resistance results in an bandwidth of the desired signal. The RC time constant of the amplifier gain of +2 causing VX to be 150 mV. The Signal filter should be matched to preserve the ac common-mode Amplifier compares this voltage to the 150 mV output (Pin 3) so rejection. that zero differential signal results. As the temperature (and therefore, the resistance) of the RTD increases, VX will likewise increase according to the gain relationship. The difference between this voltage and the zero degree value of 150 mV drives the Signal Amp to modulate the loop current. The AD693 is precalibrated such that the full 4-20mA output span corresponds toa0to 104°C range in the RTD. (This assumes the European Standard of α = 0.00385.) A total of 6 precalibrated ranges for three-wire (or two-wire) RTDs are available using only the pin strapping options as shown in Table I. A variety of other temperature ranges can be realized by using different application voltages. For example, loading the Voltage Divider with a 1.5 kΩ resistor from Pin 3 to Pin 6 (common) will approximately halve the original application voltages and allow for a doubling of the range of resistance (and therefore,

Figure 16. Optional Input Filtering temperature) required to fill the two standard spans. Likewise,

Table I. Precalibrated Temperature Range Options Using a European Standard 100 Ω RTD and the AD693 Temperature Range Pin Connections 0 to + 104°C 12 to 13 0 to +211°C 12 to 13, and 15 to 16 +25°C to +130°C 12 to 14 +51°C to +266°C 12 to 14, and 15 to 16 –50°C to +51°C 12 to 11 –100°C to +104°C 12 to 11 and 15 to 16

Figure 17. 0-to-104°C Direct Three-Wire 100 Ω RTD lnterface, 4-20mA Output REV. A –9–

, increasing the application voltages by adding resistance between external voltage divider; the Aux-Amp is then used as a follower Pins 14 and 3 will decrease the temperature span. to make a stiff drive for the bridge. Similar applications with An external voltage divider may also be used in conjunction higher resistance sensors can use proportionally higher voltage. with the circuit shown to produce any range of temperature Finally, to accommodate the 2 mV/V sensitivity of the bridge, spans as well as providing zero output (4 mA) for a non 0 the full-scale span of the Signal Amplifier must be reduced. temperature input. For example, measuring VX with respect to a Using the load cell in both tension and compression with1Vof voltage 2.385 times the excitation (rather than 2 times) will excitation, therefore, dictates that the span be adjusted to 4 mV. result in zero input to the Signal Amplifier when the RTD is at By substituting in the expression, RS1 = 400 Ω/[(30 mV/S) – 1], 100°C (or 138.5 Ω). the nominal resistance required to achieve this span is found to As suggested in Table I, the temperature span may also be adjusted be 61.54 Ω. Calculate the minimum resistance required by by changing the voltage span of the Signal Amplifier. Changing the subtracting 10% from 61.54 Ω to allow for the internal resistor gain from 2 to 4, for example, will halve the temperature span to tolerance of the AD693, leaving 55.38 Ω (See “Adjusting Input about 52°C on the 4-20mA output configuration. (See section Span.”) The standard value of 54.9 Ω is used with a 20 Ω “Adjusting Input Span.”) potentiometer for full-scale adjustment. The configuration for a three-wire RTD shown in Figure 17 can If a load cell with a precalibrated sensitivity constant is to be accommodate two-wire sensors by simply joining Pins 1 and 5 used, the resultant full-scale span applied to the Signal Amplifier is of the AD693. found by multiplying that sensitivity by the excitation voltage. (In Figure 18, the excitation voltage is actually (10 kΩ/62.3 kΩ) INTERFACING LOAD CELLS AND METAL FOIL STRAIN (6.2 V) = 0.995 V).

GAGES

The availability of the on-chip Voltage Reference, Auxiliary THERMOCOUPLE MEASUREMENTS Amplifier and 3 mA of excitation current make it easy to adapt The AD693 can be used with several types of thermocouple the AD693 to a variety of load cells and strain gages. inputs to provide a 4-20 mA current loop output corresponding to a variety of measurement temperature ranges. Cold junction The circuit shown in Figure 18 illustrates a generalized approach in compensation (CJC) can be implemented using an AD592 or which the full flexibility of the AD693 is required to interface to a AD590 and a few external resistors as shown in Figure 19. low resistance bridge. For a high impedance transducer the bridge can be directly powered from the 6.2 V Reference. From Table II simply choose the type of thermocouple and the appropriate average reference junction temperature to select Component values in this example have been selected to match values for RCOMP and RZ. The CJC voltage is developed across the popular standard of 2 mV/V sensitivity and 350 Ω bridge RCOMP as a result of the AD592 1 µA/K output and is added to resistance. Load cells are generally made for either tension and the thermocouple loop voltage. The 50 Ω potentiometer is compression, or compression only; use of the 12 mA zero tap biased by RZ to provide the correct zero adjustment range allows for operation in the tension and compression mode. An appropriate for the divider and also translates the Kelvin scale of optional zero adjustment is provided with values selected for the AD592 to °Celsius. To calibrate the circuit, put the +2% FS adjustment range. thermocouple in an ice bath (or use a thermocouple simulator Because of the low resistance of most foil bridges, the excitation set to 0) and adjust the potentiometer fora4mA loop current. voltage must be low so as not to exceed the available 4 mA zero The span of the circuit in °C is determined by matching the current. About1Vis derived from the 6.2 V Reference and an signal amplifier input voltage range to its temperature equivalent Figure 18. Utilizing the Auxiliary Amplifier to Drive a Load Cell, 12 mA ± 8 mA Output –10– REV. A,

Figure 19. Thermocouple Inputs with Cold Junction Compensation Table II. Thermocouple Application—Cold Junction Compensation

30 mV 60 mV AMBIENT TEMP TEMP POLARITY MATERIAL TYPE TEMP RCOMP RZ RANGE RANGE + IRON J 25° 51.7 Ω 301K 546°C 1035°C – CONSTANTAN 75° 53.6 Ω 294K + NICKEL-CHROME 25° 40.2 Ω 392K 721°C — _ NICKEL-ALUMINUM K 75° 42.2 Ω 374K + NICKEL-CHROME 25° 60.4 Ω 261K E 413°C 787°C – COPPER-NICKEL 75° 64.9 Ω 243K + COPPER 25° 40.2 Ω 392K T USE WITH GAIN >2 – COPPER-NICKEL 75° 45.3 Ω 340K via a set of thermocouple tables referenced to °C. For example, Table III lists the expressions required to calculate the total the output of a properly referenced type J thermocouple is error. The AD693 is tested with a 250 Ω load, a 24 V loop supply 60 mV when the hot junction is at 1035°C. Table II lists the maximum measurement temperature for several thermocouple Table III. RTI Contributions to Span and Offset Error types using the preadjusted 30 mV and 60 mV input ranges. RTI Contributions to Offset Error

More convenient temperature ranges can be selected by deter- Error Source Expression for RTI Error at Zero

mining the full-scale input voltages via standard thermocouple IZE Zero Current Error IZE/XSPSRR Power Supply Rejection Ratio (|VLOOP – 24 V| + [|RL – 250 Ω| × IZ]) × PSRR tables and adjusting the AD693 span. For example, suppose CMRR Common-Mode Rejection Ratio |VCM – 3.1 V| × CMRR only a 300°C span is to be measured with a type K thermo- IOS Input Offset Current RS × IOS couple. From a standard table, the thermocouple output is RTI Contributions to Span Error 12.207 mV; since 60 mV at the signal amplifier corresponds to a Error Source Expression for RTI Error at Full Scale X Transconductance Error V 16 mA span at the output a gain of 5, or more precisely 60 mV/ SE SPAN × XSE XPSRR Transconductance PSRR1 |RL – 250 Ω| × IS × PSRR 12.207 mV = 4.915 will be needed. Using a 12.207 mV span in XCMRR Transconductance CMRR |VCM – 3.1 V| × VSPAN × XCMRR the gain resistor formula given in “Adjusting Input Span” yields XNL Nonlinearity VSPAN × XNL I Differential Input Current2DIFF RS × IDIFF a value of about 270 Ω as the minimum from P1 to 6.2 V. Adding Abbreviations a 50 Ω potentiometer will allow ample adjustment range. IZ Zero Current (usually 4 mA)

With the connection illustrated, the AD693 will give a full-scale IS Output span (usually 16 mA)

RS Input source impedanceindication with an open thermocouple. RL Load resistance VLOOP Loop supply voltage

ERROR BUDGET ANALYSIS VCM Input common-mode voltageVSPAN Input span Loop-Powered Operation specifications refer to parameters XS Nominal transconductance in A/V

tested with the AD693 operating as a loop-powered transmitter. 1The 4–20 mA signal, flowing through the metering resistor, modulates the power supply voltage seen The specifications are valid for the preset spans of 30 mV, by the AD693. The change in voltage causes a power supply rejection error that varies with the 60 mV and those spans in between. The section, “Components output current, thus it appears as a span error. of Error,” refers to parameters tested on the individual functional The input bias current of the inverting input increases with input signal voltage. The differentialinput current, IDIFF, equals the inverting input current minus the noninverting input current; see blocks, (Signal Amplifier, V/I Converter, Voltage Reference, and Figure 2. IDIFF, flowing into an input source impedance, will cause an input voltage error that var- Auxiliary Amplifier). These can be used to get an indication of ies with signal. If the change in differential input current with input signal is approximated as a linear function, then any error due to source impedance may be approximated as a span error. To device performance when the AD693 is used in local power calculate IDIFF, refer to Figure 2 and find the value for IDIFF/ + In corresponding to the full-scale mode or when it is adjusted to spans of less than 30 mV. input voltage for your application. Multiply by + In max to get IDlFF. Multiply IDIFF by the source impedance to get the input voltage error at full scale.

REV. A –11–

, and an input common-mode voltage of 3.1 V. The expressions Error it is necessary to add an error of only (5 – 2) × VOS to the below calculate errors due to deviations from these nominal error budget. Note that span error may by reduced to zero with conditions. the span trim, leaving only the offset and nonlinearity of the The total error at zero consists only of offset errors. The total AD693. error at full scale consists of the offset errors plus the span EXAMPLE I errors. Adding the above errors in this manner may result in an The AD693 is configured as a 4-20mA loop powered transmitter error as large as 0.8% of full scale, however, as a rule, the with a 60 mV FS input. The inputs are driven by a differential AD693 performs better as the span and offset errors do not tend voltage at2Vcommon mode with a 300 Ω balanced source to add worst case. The specification “Total Unadjusted Error,” resistance. A 24 V loop supply is used with a 500 Ω metering (TUE), reflects this and gives the maximum error as a % of full resistance. (See Table IV below.) scale for any point in the transfer function when the device is operated in one of its preset spans, with no external trims. The Trimming the offset and span for your application will remove TUE is less than the error you would get by adding the span all span and offset errors except the nonlinearity of the AD693. and offset errors worst case. Table IV. Example 1 Thus, an alternative way of calculating the total error is to start OFFSET ERRORS with the TUE and add to it those errors that result from IZ Already included in the TUE spec . 0.0 µV operation of the AD693 with a load resistance, loop supply PSRR PSRR = 5.6 µV/V; (|24 V – 24 V| + [| 500 Ω – 250 Ω × 4 mA]) × 5.6 µV/V =5.6 µV voltage, or common-mode input voltage different than specified. VLOOP = 24 V (See Example 1 below.) RL = 500 Ω IZ = 4 mA CMRR CMRR = 30 µV/V; |2 V –3.1 V| × 30 µV/V = 33.0 µV ERROR BUDGET FOR SPANS LESS THAN 30 mV VCM = 2 V An accommodation must be made to include the input voltage IOS IOS = 3 nA, RS = 300 Ω; 300 Ω × 3 nA = 0.9 µV offset of the signal amplifier when the span is adjusted to less Total Additional Error at 4 mA 39.5 µV than 30 mV. The TUE and the Zero Current Error include the As % of full scale; (39.5 µV × 0.2666 A/V)/20 mA × 100% = 0.053 % of FS input offset voltage contribution of the signal amplifier in a gain SPAN ERRORS of 2. As the input offset voltage is multiplied by the gain of the XSE Already included in the TUE spec 0.0 µV signal amplifier, one must include the additional error when the XPSRR PSRR = 5.6 µV/V; (|500 Ω – 250 Ω| × 16 mA) × 5.6 µV/V = 22.4 µV RL = 500 Ω, I = 16 mAsignal amplifier is set to gains greater than 2. S XCMRR XCMRR = 0.06%/V; |2 V – 3. 1 V| × 60 mV × 0.06%/V = 39.6 µV For example, the 300K span thermocouple application discussed VCM = 2 V, VSPAN = 60 mV previously requires a 12.207 mV input span; the signal amplifier IDIFF VSPAN = +60 mV; 300 Ω × 2 × 20 nA 12.0 µV must be adjusted to a gain of approximately 5. The loop trans- IDIFF/ + In = 2 conductance is now 1.333 A/V, (5 × 0.2666 A/V). Calculate the from Figure 2) total error by substituting the new values for the transconductance XNL Already included in the TUE 0.0 µV Total Additional Span Error at Full Scale 74.0 µV and span into the equations in Table III as was done in Example Total Additional Error at Full Scale; e × OFFSET + eSPAN = 39.5 µV + 74.0 µV = 113.5 µV I. The error contribution due to VOS is 5 VOS, however, since As % of Full Scale; (113.5 µV × 0.2666A V)/20 mA × 100% = 0.151% of FS 2 × VOS is already included in the TUE and the Zero Current New Total Unadjusted Error @ FS; eTUE + eADDITIONAL = 0.5% +0.151% = 0.651% of FS OUTLINE DIMENSIONS D-20 Dimensions shown in inches and (mm). Q-20 20-Lead Side Brazed Ceramic DIP 20-Lead Cerdip E-20A 20-Terminal Leadless Chip Carrier –12– REV. A PRINTED IN U.S.A. C1050a–9–10/87]

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