Download: a MicroConverter ADCs with Embedded 62 kB Flash MCU ADuC834

a MicroConverter ®, Dual 16-Bit/24-Bit -

ADCs with Embedded 62 kB Flash MCU ADuC834

FEATURES FUNCTIONAL BLOCK DIAGRAM High Resolution - ADCs 2 Independent ADCs (16-Bit and 24-Bit Resolution) AVDD AV ADuC834 24-Bit No Missing Codes, Primary ADC DD CURRENT IEXC1 21-Bit rms (18.5-Bit p-p) Effective Resolution @ 20 Hz AIN1 SOURCE IEXC2 Offset Drift 10 nV/C, Gain Drift 0.5 ppm/C AIN2 MUX BUF PGA PRIMARY24-BIT - ADC 12-BIT

BUF

Memory DAC DAC 62 Kbytes On-Chip Flash/EE Program Memory AIN3 AGND DUAL 4 Kbytes On-Chip Flash/EE Data Memory AIN4 MUX AUXILIARY 16-BIT AIN5 16-BIT - ADC - DAC PWM0 Flash/EE, 100 Year Retention, 100 Kcycles Endurance MUX TEMP DUAL PWM1 3 Levels of Flash/EE Program Memory Security SENSOR 16-BIT

PWM

In-Circuit Serial Download (No External Hardware) REFIN– EXTERNAL INTERNAL High Speed User Download (5 Seconds) VREFIN+ REF BAND GAPDETECT VREF 8051-BASED MCU WITH ADDITIONAL 2304 Bytes On-Chip Data RAM PERIPHERALS 8051-Based Core RESET 62 KBYTES FLASH/EE PROGRAM MEMORY4 KBYTES FLASH/EE DATA MEMORY DV POR 8051 Compatible Instruction Set DD 2304 BYTES USER RAM 32 kHz External Crystal DGND PLL AND PROG 3 16 BIT TIMERS POWER SUPPLY MON CLOCK DIV BAUD RATE TIMER WATCHDOG TIMER On-Chip Programmable PLL (12.58 MHz Max) 2 OSC WAKE-UP/ 4 PARALLEL UART, SPI, ANDIC316-Bit Timer/Counter RTC TIMER PORTS SERIAL I/O 26 Programmable I/O Lines XTAL1 XTAL2 11 Interrupt Sources, Two Priority Levels Dual Data Pointer, Extended 11-Bit Stack Pointer On-Chip Peripherals GENERAL DESCRIPTION Internal Power on Reset Circuit The ADuC834 is a complete smart transducer front end, 12-Bit Voltage Output DAC integrating two high resolution - ADCs, an 8-bit MCU, and Dual 16-Bit - DACs/PWMs program/data Flash/EE memory on a single chip. On-Chip Temperature Sensor Dual Excitation Current Sources The two independent ADCs (primary and auxiliary) include a Time Interval Counter (Wake-Up/RTC Timer) temperature sensor and a PGA (allowing direct measurement of UART, SPI®, and I2C® Serial I/O low level signals). The ADCs with on-chip digital filtering and High Speed Baud Rate Generator (Including 115,200) programmable output data rates are intended for the measurement Watchdog Timer (WDT) of wide dynamic range, low frequency signals, such as those in Power Supply Monitor (PSM) weigh scale, strain-gage, pressure transducer, or temperature Power measurement applications. Normal: 2.3 mA Max @ 3.6 V (Core CLK = 1.57 MHz) The device operates from a 32 kHz crystal with an on-chip PLL Power-Down: 20 A Max with Wake-Up Timer Running generating a high frequency clock of 12.58 MHz. This clock is Specified for3Vand5VOperation routed through a programmable clock divider from which the MCU Package and Temperature Range core clock operating frequency is generated. The microcontroller 52-Lead MQFP (14 mm 14 mm), –40C to +125C core is an 8052 and therefore 8051 instruction set compatible 56-Lead LFCSP (8 mm 8 mm), –40C to +85C with 12 core clock periods per machine cycle. APPLICATIONS 62 Kbytes of nonvolatile Flash/EE program memory, 4 Kbytes of Intelligent Sensors nonvolatile Flash/EE data memory, and 2304 bytes of data RAM Weigh Scales are provided on-chip. The program memory can be configured Portable Instrumentation, Battery-Powered Systems as data memory to give up to 60 Kbytes of NV data memory in 4–20 mA Transmitters data logging applications. Data Logging On-chip factory firmware supports in-circuit serial download and Precision System Monitoring debug modes (via UART), as well as single-pin emulation mode via the EA pin. The ADuC834 is supported by a QuickStart™ development system featuring low cost software and hardware development tools.

REV. A

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. under any patent or patent rights of Analog Devices. Trademarks and Tel: 781/329-4700 www.analog.com registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved., TABLE OF CONTENTS FEATURES .1 NONVOLATILE FLASH/EE MEMORY Flash/EE Memory Overview .28 APPLICATIONS .1 Flash/EE Memory and the ADuC834 .28 FUNCTIONAL BLOCK DIAGRAM .1 ADuC834 Flash/EE Memory Reliability .29 Flash/EE Program Memory .30 GENERAL DESCRIPTION .1 Serial Downloading .30 SPECIFICATIONS .3 Parallel Programming .30 User Download Mode (ULOAD) .30 ABSOLUTE MAXIMUM RATINGS .9 Flash/EE Program Memory Security .31 ORDERING GUIDE .9 Lock, Secure, and Serial Safe Modes .31 Using the Flash/EE Data Memory .31 PIN CONFIGURATIONS .9 ECON .32 DETAILED BLOCK DIAGRAM Programming the Flash/EE Data Memory .33 .10 Flash/EE Memory Timing .33 PIN FUNCTION DESCRIPTIONS .10 OTHER ON-CHIP PERIPHERALS MEMORY ORGANIZATION .13 DAC .34 Pulsewidth Modulator (PWM) .36 SPECIAL FUNCTION REGISTERS (SFRS) .14 On-Chip PLL .39 Accumulator (ACC) .14 Time Interval Counter (Wake-Up/RTC Timer) .40 B SFR (B) .14 Watchdog Timer .42 Data Pointer (DPTR) .14 Power Supply Monitor .43 Stack Pointer (SP and SPH) .15 Serial Peripheral Interface (SPI) .44 Program Status Word (PSW) .15 I2C Serial Interface .46 Power Control SFR (PCON) .15 Dual Data Pointer .48 ADuC834 Configuration SFR (CFG834) .15 Complete SFR Map .16 8052 COMPATIBLE ON-CHIP PERIPHERALS Parallel I/O Ports 0–3 .49 ADC SFR INTERFACE Timers/Counters .52 ADCSTAT .17 UART Serial Interface .57 ADCMODE .18 UART Operating Modes .57 ADC0CON .19 Baud Rate Generation Using Timer 1 and Timer 2 .59 ADC1CON .19 Baud Rate Generation Using Timer 3 .60 ADC0H/ADC0M/ADC0L/ADC1H/ADC1L .20 Interrupt System .61 OF0H/OF0M/OF0L/OF1H/OF1L .20 GN0H/GN0M/GN0L/GN1H/GN1L .20 HARDWARE DESIGN CONSIDERATIONS SF .21 External Memory Interface .63 ICON .21 Power Supplies .64 Power-On Reset (POR) Operation .64 PRIMARY AND AUXILIARY ADC NOISE Power Consumption .64 PERFORMANCE .22 Power Saving Modes .65 PRIMARY AND AUXILIARY ADC CIRCUIT Wake-Up from Power-Down Latency .65 DESCRIPTION Grounding and Board Layout Recommendations .65 Overview .23 ADuC834 System Self-Identification .66 Primary ADC .23 Clock Oscillator .66 Auxiliary ADC .24 OTHER HARDWARE CONSIDERATIONS Analog Input Channels .24 In-Circuit Serial Download Access .67 Primary and Auxiliary ADC Inputs .25 Embedded Serial Port Debugger .67 Analog Input Ranges .25 Single-Pin Emulation Mode .67 Programmable Gain Amplifier .25 Typical System Configuration .68 Bipolar/Unipolar Inputs .25 Reference Input .26 QUICKSTART DEVELOPMENT SYSTEM .69 Burnout Currents .26 TIMING SPECIFICATIONS .70 Excitation Currents .26 Reference Detect .26 OUTLINE DIMENSIONS .80 - Modulator .26 Digital Filter .27 ADC Chopping .28 Calibration .28 –2– REV. A, (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to SPECIFICATIONS1 5.25 V, REFIN(+) = 2.5 V, REFIN(–) = AGND; AGND = DGND = 0 V; XTAL1/XTAL2 =32.768 kHz Crystal; all specifications TMIN, to TMAX unless otherwise noted.) Parameter ADuC834 Test Conditions/Comments Unit ADC SPECIFICATIONS Conversion Rate 5.4 On Both Channels Hz min 105 Programmable in 0.732 ms Increments Hz max Primary ADC No Missing Codes2 24 20 Hz Update Rate Bits min Resolution 13.5 Range = ±20 mV, 20 Hz Update Rate Bits p-p typ 18.5 Range = ±2.56 V, 20 Hz Update Rate Bits p-p typ Output Noise See Tables X and XI Output Noise Varies with Selected in ADuC834 ADC Update Rate and Gain Range Description Integral Nonlinearity ±15 1 LSB16 ppm of FSR max Offset Error3 ±3 V typ Offset Error Drift ±10 nV/°C typ Full-Scale Error4 ±10 V typ Gain Error Drift5 ±0.5 ppm/°C typ ADC Range Matching ±2 AIN = 18 mV V typ Power Supply Rejection (PSR) 113 AIN = 7.8 mV, Range = ±20 mV dBs typ 80 AIN = 1 V, Range = ±2.56 V dBs min Common-Mode DC Rejection On AIN 95 At DC, AIN = 7.8 mV, Range = ±20 mV dBs min 113 At DC, AIN = 1 V, Range = ±2.56 V dBs typ On REFIN 125 At DC, AIN = 1 V, Range = ±2.56 V dBs typ Common-Mode 50 Hz/60 Hz Rejection2 20 Hz Update Rate On AIN 95 50 Hz/60 Hz ±1 Hz, AIN = 7.8 mV, dBs min Range = ±20 mV 90 50 Hz/60 Hz ±1 Hz, AIN = 1 V, dBs min Range = ±2.56 V On REFIN 90 50 Hz/60 Hz ±1 Hz, AIN = 1 V, dBs min Range = ±2.56 V Normal Mode 50 Hz/60 Hz Rejection2 On AIN 60 50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate dBs min On REFIN 60 50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate dBs min Auxiliary ADC No Missing Codes2 16 Bits min Resolution 16 Range = ±2.5 V, 20 Hz Update Rate Bits p-p typ Output Noise See Table XII in Output Noise Varies with Selected ADuC834 ADC Update Rate Description Integral Nonlinearity ±15 ppm of FSR max Offset Error3 –2 LSB typ Offset Error Drift 1 V/°C typ Full-Scale Error6 –2.5 LSB typ Gain Error Drift5 ±0.5 ppm/°C typ Power Supply Rejection (PSR) 80 AIN = 1 V, 20 Hz Update Rate dBs min Normal Mode 50 Hz/60 Hz Rejection2 On AIN 60 50 Hz/60 Hz ±1 Hz dBs min On REFIN 60 50 Hz/60 Hz ±1 Hz, 20 Hz Update Rate dBs min DAC PERFORMANCE DC Specifications7 Resolution 12 Bits Relative Accuracy ±3 LSB typ Differential Nonlinearity –1 Guaranteed 12-Bit Monotonic LSB max Offset Error ±50 mV max Gain Error8 ±1 AVDD Range % max ±1 VREF Range % typ AC Specifications2, 7 Voltage Output Settling Time 15 Settling Time to 1 LSB of Final Value s typ Digital-to-Analog Glitch Energy 10 1 LSB Change at Major Carry nVs typ REV. A –3–,

SPECIFICATIONS (continued)

Parameter ADuC834 Test Conditions/Comments Unit INTERNAL REFERENCE ADC Reference Reference Voltage 1.25 ± 1% Initial Tolerance @ 25°C, VDD = 5VVmin/max Power Supply Rejection 45 dBs typ Reference Tempco 100 ppm/°C typ DAC Reference Reference Voltage 2.5 ± 1% Initial Tolerance @ 25°C, VDD = 5VVmin/max Power Supply Rejection 50 dBs typ Reference Tempco ±100 ppm/°C typ ANALOG INPUTS/REFERENCE INPUTS Primary ADC Differential Input Voltage Ranges9, 10 External Reference Voltage = 2.5 V RN2, RN1, RN0 of ADC0CON Set to Bipolar Mode (ADC0CON3 = 0) ±20000(Unipolar Mode 0 mV to 20 mV) mV ±40001(Unipolar Mode 0 mV to 40 mV) mV ±80010(Unipolar Mode 0 mV to 80 mV) mV ±160011(Unipolar Mode 0 mV to 160 mV) mV ±320100(Unipolar Mode 0 mV to 320 mV) mV ±640101(Unipolar Mode 0 mV to 640 mV) mV ±1.28110(Unipolar Mode0Vto 1.28 V) V ±2.56111(Unipolar Mode0Vto 2.56 V) V Analog Input Current2 ±1 TMAX = 85°C nA max ±5 TMAX = 125°C nA max Analog Input Current Drift ±5 TMAX = 85°C pA/°C typ ±15 TMAX = 125°C pA/°C typ Absolute AIN Voltage Limits2 AGND + 100 mV V min AVDD – 100 mV V max Auxiliary ADC Input Voltage Range9, 10 0 to VREF Unipolar Mode, for Bipolar Mode V See Note 11 Average Analog Input Current 125 Input Current Will Vary with Input nA/V typ Average Analog Input Current Drift2 ±2 Voltage on the Unbuffered Auxiliary ADC pA/V/°C typ Absolute AIN Voltage Limits2, 11 AGND – 30 mV V min AVDD + 30 mV V max External Reference Inputs REFIN(+) to REFIN(–) Range21Vmin AVDD V max Average Reference Input Current 1 Both ADCs Enabled A/V typ Average Reference Input Current Drift ±0.1 nA/V/°C typ ‘NO Ext. REF’ Trigger Voltage 0.3 NOXREF Bit Active if VREF < 0.3VVmin 0.65 NOXREF Bit Inactive if VREF > 0.65VVmax ADC SYSTEM CALIBRATION Full-Scale Calibration Limit +1.05 FS V max Zero-Scale Calibration Limit –1.05 FS V min Input Span 0.8 FS V min 2.1 FS V max ANALOG (DAC) OUTPUT Voltage Range 0 to VREF DACRN = 0 in DACCON SFR V typ 0 to AVDD DACRN = 1 in DACCON SFR V typ Resistive Load 10 From DAC Output to AGND kΩ typ Capacitive Load 100 From DAC Output to AGND pF typ Output Impedance 0.5 Ω typ ISINK 50 A typ TEMPERATURE SENSOR Accuracy ±2 °C typ Thermal Impedance (JA) 90 MQFP Package °C/W typ 52 CSP Package (Base Floating)12 °C/W typ –4– REV. A, Parameter ADuC834 Test Conditions/Comments Unit TRANSDUCER BURNOUT CURRENT SOURCES AIN+ Current –100 AIN+ Is the Selected Positive Input to nA typ the Primary ADC AIN– Current +100 AIN– Is the Selected Negative Input to nA typ the Auxiliary ADC Initial Tolerance @ 25°C ±10 % typ Drift 0.03 %/°C typ EXCITATION CURRENT SOURCES Output Current –200 Available from Each Current Source A typ Initial Tolerance @ 25°C ±10 % typ Drift 200 ppm/°C typ Initial Current Matching @ 25°C ±1 Matching between Both Current Sources % typ Drift Matching 20 ppm/°C typ Line Regulation (AVDD) 1 AVDD = 5 V + 5% A/V typ Load Regulation 0.1 A/V typ Output Compliance2 AVDD – 0.6 V max AGND min LOGIC INPUTS All Inputs Except SCLOCK, RESET, and XTAL12 VINL, Input Low Voltage 0.8 DVDD = 5VVmax 0.4 DVDD = 3VVmax VINH, Input High Voltage 2.0 V min SCLOCK and RESET Only (Schmitt-Triggered Inputs)2 VT+ 1.3/3 DVDD = 5VVmin/V max 0.95/2.5 DVDD = 3VVmin/V max VT– 0.8/1.4 DVDD = 5VVmin/V max 0.4/1.1 DVDD = 3VVmin/V max VT+ – VT– 0.3/0.85 DVDD = 5VVmin/V max 0.3/0.85 DVDD = 3VVmin/V max Input Currents Port 0, P1.2–P1.7, EA ±10 VIN = 0 V or VDD A max SCLOCK, MOSI, MISO, SS13 –10 min, –40 max VIN = 0 V, DVDD = 5 V, Internal Pull-Up A min/A max ±10 VIN = VDD, DVDD = 5VAmax RESET ±10 VIN = 0 V, DVDD = 5VAmax 35 min, 105 max VIN = VDD, DVDD = 5 V, Internal Pull-Down A min/A max P1.0, P1.1, Ports 2 and 3 ±10 VIN = VDD, DVDD = 5VAmax –180 VIN = 2 V, DVDD = 5VAmin –660 A max –20 VIN = 450 mV, DVDD = 5VAmin –75 A max Input Capacitance 5 All Digital Inputs pF typ CRYSTAL OSCILLATOR (XTAL1 AND XTAL2) Logic Inputs, XTAL1 Only2 VINL, Input Low Voltage 0.8 DVDD = 5VVmax 0.4 DVDD = 3VVmax VINH, Input High Voltage 3.5 DVDD = 5VVmin 2.5 DVDD = 3VVmin XTAL1 Input Capacitance 18 pF typ XTAL2 Output Capacitance 18 pF typ REV. A –5–,

SPECIFICATIONS (continued)

Parameter ADuC834 Test Conditions/Comments Unit LOGIC OUTPUTS (Not Including XTAL2)2 VOH, Output High Voltage 2.4 VDD = 5 V, ISOURCE = 80AVmin 2.4 VDD = 3 V, ISOURCE = 20AVmin VOL, Output Low Voltage14 0.4 ISINK = 8 mA, SCLOCK, V max MOSI/SDATA 0.4 ISINK = 10 mA, P1.0 and P1.1 V max 0.4 ISINK = 1.6 mA, All Other Outputs V max Floating State Leakage Current2 ±10 A max Floating State Output Capacitance 5 pF typ POWER SUPPLY MONITOR (PSM) AVDD Trip Point Selection Range 2.63 Four Trip Points Selectable in This Range V min 4.63 Programmed via TPA1–0 in PSMCON V max AVDD Power Supply Trip Point Accuracy ±3.0 TMAX = 85°C % max ±4.0 TMAX = 125°C % max DVDD Trip Point Selection Range 2.63 Four Trip Points Selectable in This Range V min 4.63 Programmed via TPD1–0 in PSMCON V max DVDD Power Supply Trip Point Accuracy ±3.0 TMAX = 85C % max ±4.0 TMAX = 125C % max WATCHDOG TIMER (WDT) Timeout Period 0 Nine Timeout Periods in This Range ms min 2000 Programmed via PRE3–0 in WDCON ms max MCU CORE CLOCK RATE Clock Rate Generated via On-Chip PLL MCU Clock Rate2 98.3 Programmable via CD2–0 Bits in kHz min PLLCON SFR 12.58 MHz max START-UP TIME At Power-On 300 ms typ After External RESET in Normal Mode 3 ms typ After WDT Reset in Normal Mode 3 Controlled via WDCON SFR ms typ From Idle Mode 10 s typ From Power-Down Mode Oscillator Running OSC_PD Bit = 0 in PLLCON SFR Wake-Up with INT0 Interrupt 20 s typ Wake-Up with SPI Interrupt 20 s typ Wake-Up with TIC Interrupt 20 s typ Wake-Up with External RESET 3 ms typ Oscillator Powered Down OSC_PD Bit = 1 in PLLCON SFR Wake-Up with INT0 Interrupt 20 s typ Wake-Up with SPI Interrupt 20 s typ Wake-Up with External RESET 5 ms typ FLASH/EE MEMORY RELIABILITY CHARACTERISTICS15 Endurance16 100,000 Cycles min Data Retention17 100 Years min –6– REV. A, Parameter ADuC834 Test Conditions/Comments Unit POWER REQUIREMENTS DVDD and AVDD Can Be Set Independently Power Supply Voltages AVDD, 3 V Nominal Operation 2.7 V min 3.6 V max AVDD, 5 V Nominal Operation 4.75 V min 5.25 V max DVDD, 3 V Nominal Operation 2.7 V min 3.6 V max DVDD, 5 V Nominal Operation 4.75 V min 5.25 V max5VPOWER CONSUMPTION DVDD = 4.75 V to 5.25 V, AVDD = 5.25 V Power Supply Currents Normal Mode18, 19 DVDD Current 4 Core CLK = 1.57 MHz mA max DVDD Current 13 Core CLK = 12.58 MHz mA typ 16 Core CLK = 12.58 MHz mA max AVDD Current 180 Core CLK = 1.57 MHz or 12.58 MHz A max Typical Additional Power Supply Currents Core CLK = 1.57 MHz (AIDD and DIDD) PSM Peripheral 50 A typ Primary ADC 1 mA typ Auxiliary ADC 500 A typ DAC 150 A typ Dual Current Sources 400 A typ3VPOWER CONSUMPTION DVDD = 2.7 V to 3.6 V Power Supply Currents Normal Mode18, 19 DVDD Current 2.3 Core CLK = 1.57 MHz mA max DVDD Current 8 Core CLK = 12.58 MHz mA typ 10 Core CLK = 12.58 MHz mA max AVDD Current 180 AVDD = 5.25 V, Core CLK = 1.57 MHz or 12.58 MHz A max Power Supply Currents Power-Down Mode18, 19 Core CLK = 1.57 MHz or 12.58 MHz DVDD Current 20 TMAX = 85°C; Osc. On, TIC On A max 40 TMAX = 125°C; Osc. On, TIC On A max DVDD Current 10 Osc. Off A typ AVDD Current 1 AVDD = 5.25 V; TMAX = 85°C; Osc. On or Osc. Off A max 3 AVDD = 5.25 V; TMAX = 125°C; Osc. On or Osc. Off A max REV. A –7–,

NOTES

1 Temperature Range for ADuC834BS (MQFP package) is –40°C to +125°C. Temperature Range for ADuC834BCP (CSP package) is –40°C to +85°C. 2 These numbers are not production tested but are guaranteed by design and/or characterization data on production release. 3 System Zero-Scale Calibration can remove this error. 4 The primary ADC is factory calibrated at 25°C with AVDD = DVDD = 5 V yielding this full-scale error of 10 V. If user power supply or temperature conditions are significantly different from these, an Internal Full-Scale Calibration will restore this error to 10 V. A system zero-scale and full-scale calibration will remove this error altogether. 5 Gain Error Drift is a span drift. To calculate Full-Scale Error Drift, add the Offset Error Drift to the Gain Error Drift times the full-scale input. 6 The auxiliary ADC is factory calibrated at 25°C with AVDD = DVDD = 5 V yielding this full-scale error of –2.5 LSB. A system zero-scale and full-scale calibration will remove this error altogether. 7 DAC linearity and ac specifications are calculated using: reduced code range of 48 to 4095, 0 to V REF; reduced code range of 100 to 3950, 0 to VDD. 8 Gain Error is a measure of the span error of the DAC. 9 In general terms, the bipolar input voltage range to the primary ADC is given by RangeADC = ± (VREF 2RN)/125, where: VREF = REFIN(+) to REFIN(–) voltage and VREF = 1.25 V when internal ADC VREF is selected. RN = decimal equivalent of RN2, RN1, RN0, e.g., VREF = 2.5 V and RN2, RN1, RN0 = 1, 1, 0 the RangeADC = ± 1.28 V. In unipolar mode, the effective range is0Vto 1.28 V in our example. 10 1.25 V is used as the reference voltage to the ADC when internal VREF is selected via XREF0 and XREF1 bits in ADC0CON and ADC1CON, respectively. 11 In bipolar mode, the Auxiliary ADC can only be driven to a minimum of AGND – 30 mV as indicated by the Auxiliary ADC absolute AIN voltage limits. The bipolar range is still –VREF to +VREF; however, the negative voltage is limited to –30 mV. 12 The ADuC834BCP (CSP Package) has been qualified and tested with the base of the CSP Package floating. 13 Pins configured in SPI Mode, pins configured as digital inputs during this test. 14 Pins configured in I2C Mode only. 15 Flash/EE Memory Reliability Characteristics apply to both the Flash/EE program memory and Flash/EE data memory. 16 Endurance is qualified to 100 Kcycles as per JEDEC Std. 22 method A117 and measured at –40 °C, +25°C, +85°C, and +125°C. Typical endurance at 25°C is 700 Kcycles. 17 Retention lifetime equivalent at junction temperature (TJ) = 55°C as per JEDEC Std. 22, Method A117. Retention lifetime based on an activation energy of 0.6eV will derate with junction temperature as shown in Figure 16 in the Flash/EE Memory section of this data sheet. 18 Power Supply current consumption is measured in Normal, Idle, and Power-Down modes under the following conditions: Normal mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, Core Executing internal software loop. Idle mode: Reset = 0.4 V, Digital I/O pins = open circuit, Core Clk changed via CD bits in PLLCON, PCON.0 = 1, Core Execution suspended in idle mode. Power-Down mode: Reset = 0.4 V, All P0 pins and P1.2–P1.7 Pins = 0.4 V, All other digital I/O pins are open circuit, Core Clk changed via CD bits in PLLCON, PCON.1 = 1, Core Execution suspended in power-down mode, OSC turned ON or OFF via OSC_PD bit (PLLCON.7) in PLLCON SFR. 19 DVDD power supply current will increase typically by 3 mA (3 V operation) and 10 mA (5 V operation) during a Flash/EE memory program or erase cycle. Specifications subject to change without notice. –8– REV. A, ABSOLUTE MAXIMUM RATINGS1 PIN CONFIGURATION (TA = 25°C, unless otherwise noted.) 52-Lead MQFP AVDD to AGND .–0.3 V to +7 V 52 40 AVDD to DGND .–0.3 V to +7 V DVDD to AGND .–0.3 V to +7 V DVDD to DGND .–0.3 V to +7V1PIN 1 39

IDENTIFIER

AGND to DGND2 .–0.3 V to +0.3 V AVDD to DVDD .–2 V to +5 V Analog Input Voltage to AGND3 .–0.3 V to AVDD + 0.3 V ADuC834 Reference Input Voltage to AGND .–0.3 V to AVDD + 0.3 V TOP VIEW (Not To Scale) AIN/REFIN Current (Indefinite) .30 mA Digital Input Voltage to DGND .–0.3 V to DVDD + 0.3 V Digital Output Voltage to DGND .–0.3 V to DVDD + 0.3 V 13 27 Operating Temperature Range .–40°C to +125°C Storage Temperature Range .–65°C to +150°C 14 26 Junction Temperature .150°C JA Thermal Impedance (MQFP) .90°C/W 56-Lead LFCSP JA Thermal Impedance (LFCSP Base Floating) .52°C/W Lead Temperature, Soldering 56 43 Vapor Phase (60 sec) .215°C 1 PIN 1 42 Infrared (15 sec) .220°C IDENTIFIER

NOTES

1Stresses above those listed under Absolute Maximum Ratings may cause perma- ADuC834 nent damage to the device. This is a stress rating only; functional operation of the TOP VIEW (Not To Scale) device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. 2AGND and DGND are shorted internally on the ADuC834. 14 29 3Applies to P1.2 to P1.7 pins operating in analog or digital input modes. 15 28 ORDERING GUIDE Temperature Package Package Model Range Description Option ADuC834BS –40°C to +125°C 52-Lead Metric Quad Flat Package S-52 ADuC834BCP –40°C to +85°C 56-Lead Frame Chip Scale Package CP-56 EVAL-ADuC834QS QuickStart Development System

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADuC834 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.

REV. A –9–

, 43 44 45 46 49 50 51 521234910 11 12 28 29 30 31 36 37 38 39 16 17 18 19 22 23 24 25 ADuC834 12-BIT

DAC

CONTROL VOLTAGE BUF 3 DAC OUTPUT DAC AIN1 PRIMARY ADC ADCCONTROL AIN BUF PGA 24-BIT AIN2 ANDMUX - ADC CALIBRATION DUAL 16-BIT 1 PWM0 PWM - DAC AIN3 CONTROL MUX AIN AUXILIARY ADC ADC CONTROL DUALAIN4 MUX 16-BIT AND 16-BIT PWM1 AIN5 - ADC CALIBRATION PWM TEMP BAND GAP 2304 BYTES 22 T0 62 KBYTES PROGRAM/ SENSOR REFERENCE USER RAMFLASH/EE 16-BIT 23 T1

COUNTER

TIMERS 1 T2

WATCHDOG

4 KBYTES DATA TIMER 2 T2EX REFIN VREF FLASH/EE 8052 REFIN DETECT POWER SUPPLYMCU MONITOR 2 DATA POINTERS CORE 11-BIT STACK POINTER PLL WITH PROG. 200A 200A CLOCK DIVIDER 18 INT0 DOWNLOADER 19WAKE-UP/ INT1 DEBUGGER RTC TIMER IEXC 1 CURRENT

SOURCE

IEXC 2 MUX UART UART SPI/I2C SERIAL SERIAL PORT TIMER OSC POR INTERFACE5620 34 48 47 21 35 15 16 17 41 40 42 26 27 14 13 32 33 *PIN NUMBERS REFER TO THE 52-LEAD MQFP PACKAGE SHADED AREAS REPRESENT THE NEW FEATURES OF THE ADuC834 OVER THE ADuC824

Figure 1. Detailed Block Diagram PIN FUNCTION DESCRIPTIONS Pin No. Pin No.

52-Lead 56-Lead

MQFP CSP Mnemonic Type* Description

1, 2 56, 1 P1.0/P1.1 I/O P1.0 and P1.1 can function as a digital inputs or digital outputs and have a pull-up configuration as described below for Port 3. P1.0 and P1.1 have an increased current drive sink capability of 10 mA.

P1.0/T2/PWM0 I/O P1.0 and P1.1 also have various secondary functions as described below. P1.0 can also be used to provide a clock input to Timer 2. When enabled, counter

2 is incremented in response to a negative transition on the T2 input pin.

If the PWM is enabled, the PWM0 output will appear at this pin. P1.1/T2EX/PWM1 I/O P1.1 can also be used to provide a control input to Timer 2. When enabled, a

negative transition on the T2EX input pin will cause a Timer 2 capture or reload event. If the PWM is enabled, the PWM1 output will appear at this pin. –10– REV. A AV P0.0 (AD0)DD P0.1 (AD1)

AGND

P0.2 (AD2) P0.3 (AD3) DVDD P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) DGND P0.7 (AD7) P1.0 (T2)

RESET

P1.1 (T2EX) P1.2 (DAC/IEXC 1) RXD P1.3 (AIN5/IEXC 2) TXD P1.4 (AIN1) P1.5 (AIN2) P1.6 (AIN3) P1.7 (AIN4/DAC) P2.0 (A8/A16) P2.1 (A9/A17) PSEN P2.2 (A10/A18) EA SINGLE-PINEMULATOR P2.3 (A11/A19)

ALE

P2.4 (A12/A20) P2.5 (A13/A21) SCLOCK P2.6 (A14/A22) P2.7 (A15/A23) MOSI/SDATA P3.0 (RXD)

MISO

P3.1 (TXD) SS P3.2 (INT0) P3.3 (INT1) P3.4 (T0/PWMCLK) P3.5 (T1) XTAL1 P3.6 (WR) XTAL2 P3.7 (RD), PIN FUNCTION DESCRIPTIONS (continued) Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic Type* Description 3–4, 2–3, P1.2–P1.7 I Port 1.2 to Port 1.7 have no digital output driver; they can function as a digital 9–12 11–14 input for which ‘0’ must be written to the port bit. As a digital input, these pins must be driven high or low externally. These pins also have the following analog functionality: P1.2/DAC/IEXC1 I/O The voltage output from the DAC or one or both current sources (200 A or 2 200 A) can be configured to appear at this pin. P1.3/AIN5/IEXC2 I/O Auxiliary ADC Input or one or both current sources can be configured at this pin. P1.4/AIN1 I Primary ADC, Positive Analog Input P1.5/AIN2 I Primary ADC, Negative Analog Input P1.6/AIN3 I Auxiliary ADC Input or Muxed Primary ADC, Positive Analog Input P1.7/AIN4/DAC I/O Auxiliary ADC Input or Muxed Primary ADC, Negative Analog Input. The voltage output from the DAC can also be configured to appear at this pin. 5 4, 5 AVDD S Analog Supply Voltage, 3 V or5V66, 7, 8 AGND S Analog Ground. Ground reference pin for the analog circuitry. 7 9 REFIN(–) I Reference Input, Negative Terminal 8 10 REFIN(+) I Reference Input, Positive Terminal 13 15 SS I Slave Select Input for the SPI Interface. A weak pull-up is present on this pin. 14 16 MISO I/O Master Input/Slave Output for the SPI Interface. There is a weak pull-up on this input pin. 15 17 RESET I Reset Input. A high level on this pin for 16 core clock cycles while the oscillator is running resets the device. There is an internal weak pull-down and a Schmitt trigger input stage on this pin. 16–19, 18–21, P3.0–P3.7 I/O Bidirectional port pins with internal pull-up resistors. Port 3 pins that have 1s written 22–25 24–27 to them are pulled high by the internal pull-up resistors, and in that state can be used as inputs. As inputs, Port 3 pins being pulled externally low will source current because of the internal pull-up resistors. When driving a 0-to-1 output transition, a strong pull-up is active for two core clock periods of the instruction cycle. Port 3 pins also have various secondary functions including: P3.0/RXD I/O Receiver Data for UART Serial Port P3.1/TXD I/O Transmitter Data for UART Serial Port P3.2/INT0 I/O External Interrupt 0. This pin can also be used as a gate control input to Timer 0. P3.3/INT1 I/O External Interrupt 1. This pin can also be used as a gate control input to Timer 1. P3.4/T0/ I/O Timer/Counter 0 External Input. If the PWM is enabled, an external clock may be PWMCLK input at this pin. P3.5/T1 I/O Timer/Counter 1 External Input P3.6/WR I/O External Data Memory Write Strobe. Latches the data byte from Port 0 into an external data memory. P3.7/RD I/O External Data Memory Read Strobe. Enables the data from an external data memory to Port 0. 20, 34, 48 22, 36, 51 DVDD S Digital Supply, 3 V or 5 V. 21, 35, 23, 37, DGND S Digital Ground. Ground reference point for the digital circuitry. 47 38, 50 26 SCLOCK I/O Serial Interface Clock for Either the I2C or SPI Interface. As an input, this pin is a Schmitt-triggered input and a weak internal pull-up is present on this pin unless it is outputting logic low. This pin can also be directly controlled in software as a digital output pin. 27 MOSI/SDATA I/O Serial Data I/O for the I2C Interface or Master Output/Slave Input for the SPI Interface. A weak internal pull-up is present on this pin unless it is outputting logic low. This pin can also be directly controlled in software as a digital output pin. REV. A –11–, PIN FUNCTION DESCRIPTIONS (continued) Pin No. Pin No. 52-Lead 56-Lead MQFP CSP Mnemonic Type* Description 28–31 30–33 P2.0–P2.7 I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s 36–39 39–42 (A8–A15) written to them are pulled high by the internal pull-up resistors, and in that state can (A16–A23) be used as inputs. As inputs, Port 2 pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the 24-bit external data memory space. 32 34 XTAL1 I Input to the Crystal Oscillator Inverter 33 35 XTAL2 O Output from the Crystal Oscillator Inverter. (See “Hardware Design Considerations” for description.) 40 43 EA I/O External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations 0000h to F7FFh. When held low, this input enables the device to fetch all instructions from external program memory. To determine the mode of code execution, i.e., internal or external, the EA pin is sampled at the end of an external RESET assertion or as part of a device power cycle. EA may also be used as an external emulation I/O pin, and therefore the voltage level at this pin must not be changed during normal mode operation as it may cause an emulation interrupt that will halt code execution. 41 44 PSEN O Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. PSEN can also be used to enable serial download mode when pulled low through a resistor at the end of an external RESET assertion or as part of a device power cycle. 42 45 ALE O Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit data address space accesses) of the address to external memory during external code or data memory access cycles. It is activated every six oscillator periods except during an external data memory access. It can be disabled by setting the PCON.4 bit in the PCON SFR. 43–46 46–49 P0.0–P0.7 I/O P0.0–P0.7, these pins are part of Port0, which is an 8-bit, open-drain, bidirectional 49–52 52–55 (AD0–AD3) I/O port. Port 0 pins that have 1s written to them float and in that state can be used (AD4–AD7) as high impedance inputs. An external pull-up resistor will be required on P0 outputs to force a valid logic high level externally. Port 0 is also the multiplexed low-order address and databus during accesses to external program or data memory. In this application, it uses strong internal pull-ups when emitting 1s. *I = Input, O = Output, S = Supply. –12– REV. A, MEMORY ORGANIZATION 16 bytes (128 bits), locations 20H through 2FH above the register The ADuC834 contains four different memory blocks, namely: banks, form a block of directly addressable bit locations at bit • 62 Kbytes of On-Chip Flash/EE Program Memory addresses 00H through 7FH. The stack can be located anywhere in the internal memory address space, and the stack depth can • 4 Kbytes of On-Chip Flash/EE Data Memory be expanded up to 2048 bytes. • 256 bytes of General-Purpose RAM Reset initializes the stack pointer to location 07H. Any CALL • 2 Kbytes of Internal XRAM or PUSH pre-increments the SP before loading the stack. (1) Flash/EE Program Memory Therefore, loading the stack starts from locations 08H, which is

The ADuC834 provides 62 Kbytes of Flash/EE program also the first register (R0) of register bank 1. Thus, if one is

memory to run user code. The user can choose to run code from going to use more than one register bank, the stack pointer should this internal memory or run code from an external program be initialized to an area of RAM not used for data storage. memory. 7FH If the user applies power or resets the device while the EA pin is GENERAL-PURPOSE pulled low externally, the part will execute code from the external AREA program space; otherwise, if EA is pulled high externally, the 30H part defaults to code execution from its internal 62 Kbytes of BANKS 2FH Flash/EE program memory. SELECTED BIT-ADDRESSABLE

VIA

Unlike the ADuC824, where code execution can overflow from (BIT ADDRESSES)BITS IN PSW the internal code space to external code space once the PC 20H becomes greater than 1FFFH, the ADuC834 does not support 1FH the rollover from F7FFH in internal code space to F800H in 18H external code space. Instead, the 2048 bytes between F800H 17H and FFFFH will appear as NOP instructions to user code. 10 10H FOUR BANKS OF EIGHT

REGISTERS

Permanently embedded firmware allows code to be serially 0FH R0–R7 downloaded to the 62 Kbytes of internal code space via the 01 08H UART serial port while the device is in-circuit. No external 07H RESET VALUE OF hardware is required. 00 STACK POINTER 00H 56 Kbytes of the program memory can be reprogrammed during runtime; thus the code space can be upgraded in the field using Figure 2. Lower 128 Bytes of Internal Data Memory a user defined protocol or it can be used as a data memory. (4) Internal XRAM This will be discussed in more detail in the Flash/EE Memory The ADuC834 contains 2 Kbytes of on-chip extended data section of the data sheet. memory. This memory, although on-chip, is accessed via the (2) Flash/EE Data Memory MOVX instruction. The 2 Kbytes of internal XRAM are 4 Kbytes of Flash/EE Data Memory are available to the user mapped into the bottom 2 Kbytes of the external address space and can be accessed indirectly via a group of registers mapped if the CFG834.0 bit is set. Otherwise, access to the external into the Special Function Register (SFR) area. Access to the data memory will occur just like a standard 8051. Flash/EE Data memory is discussed in detail later as part of the Even with the CFG834.0 bit set, access to the external XRAM Flash/EE Memory section in this data sheet. will occur once the 24-bit DPTR is greater than 0007FFH. (3) General-Purpose RAM The general-purpose RAM is divided into two separate memories, FFFFFFH FFFFFFH namely the upper and the lower 128 bytes of RAM. The lower 128 bytes of RAM can be accessed through direct or indirect addressing; the upper 128 bytes of RAM can only be accessed through indirect addressing as it shares the same address space EXTERNAL EXTERNAL as the SFR space, which can only be accessed through direct DATA DATAMEMORY MEMORY addressing. SPACE SPACE (24-BIT (24-BIT The lower 128 bytes of internal data memory are mapped as ADDRESS ADDRESSSPACE) SPACE) shown in Figure 2. The lowest 32 bytes are grouped into four banks of eight registers addressed as R0 through R7. The next 000800H 0007FFH 2 KBYTES GENERAL NOTES PERTAINING TO THIS DATA SHEET ON-CHIP 1. SET implies a Logic 1 state and CLEARED implies a Logic 0 state unless XRAM 000000H 000000H otherwise stated. 2. SET and CLEARED also imply that the bit is set or automatically cleared by CFG834.0 = 0 CFG834.0 = 1 the ADuC834 hardware unless otherwise stated. 3. User software should not write 1s to reserved or unimplemented bits as they may Figure 3. Internal and External XRAM be used in future products. 4. Any pin numbers used throughout this data sheet refer to the 52-lead MQFP package, unless otherwise stated.

REV. A –13–

, When accessing the internal XRAM, the P0 and P2 port pins, SPECIAL FUNCTION REGISTERS (SFRS) as well as the RD and WR strobes, will not be output as per a The SFR space is mapped into the upper 128 bytes of internal standard 8051 MOVX instruction. This allows the user to use data memory space and accessed by direct addressing only. It these port pins as standard I/O. provides an interface between the CPU and all on-chip periph- The upper 1792 bytes of the internal XRAM can be configured erals. A block diagram showing the programming model of the to be used as an extended 11-bit stack pointer. By default, the ADuC834 via the SFR area is shown in Figure 5. stack will operate exactly like an 8052 in that it will roll over from FFH to 00H in the general-purpose RAM. On the ADuC834 62 KBYTE ELECTRICALLY 4 KBYTEELECTRICALLY however, it is possible (by setting CFG834.7) to enable the 11-bit REPROGRAMMABLE NONVOLATILE FLASH/EE REPROGRAMMABLE extended stack pointer. In this case, the stack will roll over from PROGRAM MEMORY NONVOLATILEFLASH/EE DATA FFH in RAM to 0100H in XRAM. The 11-bit stack pointer is MEMORY visible in the SP and SPH SFRs. The SP SFR is located at 81H 128-BYTE as with a standard 8052. The SPH SFR is located at B7H. The 8051 SPECIAL 3 LSBs of this SFR contain the three extra bits necessary to extend COMPATIBLE FUNCTION DUAL - ADCsCORE REGISTER the 8-bit stack pointer into an 11-bit stack pointer. AREA OTHER ON-CHIP 07FFH PERIPHERALS 256 BYTES RAM TEMP SENSOR 2K XRAM CURRENT SOURCES 12-BIT DAC SERIAL I/O WDT, PSM UPPER 1792 TIC, PLL BYTES OF ON-CHIP XRAM (DATA + STACK Figure 5. Programming Model FOR EXSP = 1, DATA ONLY All registers, except the Program Counter (PC) and the four FOR EXSP = 0) general-purpose register banks, reside in the SFR area. The SFR CFG834.7 = 0 CFG834.7 = 1 registers include control, configuration, and data registers that provide an interface between the CPU and all on-chip peripherals. 100H FFH Accumulator SFR (ACC) 256 BYTES OF LOWER 256 ON-CHIP DATA ACC is the Accumulator Register and is used for math operationsBYTES OF RAM ON-CHIP XRAM including addition, subtraction, integer multiplication and division, (DATA + (DATA ONLY) STACK) 00H and Boolean bit manipulations. The mnemonics for accumulator-00H specific instructions refer to the Accumulator as A.

Figure 4. Extended Stack Pointer Operation B SFR (B)

External Data Memory (External XRAM) The B Register is used with the ACC for multiplication and Just like a standard 8051 compatible core, the ADuC834 can division operations. For other instructions, it can be treated as access external data memory using a MOVX instruction. The a general-purpose scratchpad register. MOVX instruction automatically outputs the various control Data Pointer (DPTR) strobes required to access the data memory. The Data Pointer is made up of three 8-bit registers, named DPP The ADuC834 however, can access up to 16 Mbytes of external (page byte), DPH (high byte) and DPL (low byte). These are data memory. This is an enhancement of the 64 Kbytes external used to provide memory addresses for internal and external data memory space available on a standard 8051 compatible core. code access and external data access. It may be manipulated as a 16-bit register (DPTR = DPH, DPL), although INC DPTR The external data memory is discussed in more detail in the instructions will automatically carry over to DPP, or as three ADuC834 Hardware Design Considerations section. independent 8-bit registers (DPP, DPH, DPL). The ADuC834 supports dual data pointers. Refer to the Dual Data Pointer section in this data sheet. –14– REV. A, Stack Pointer (SP and SPH) Table II. PCON SFR Bit Designations The SP SFR is the stack pointer and is used to hold an internal RAM address that is called the ‘top of the stack.’ The SP Register Bit Name Description is incremented before data is stored during PUSH and CALL 7 SMOD Double UART Baud Rate executions. While the Stack may reside anywhere in on-chip 6 SERIPD SPI Power-Down Interrupt Enable RAM, the SP Register is initialized to 07H after a reset. This 5 INT0PD INT0 Power-Down Interrupt Enable causes the stack to begin at location 08H. 4 ALEOFF Disable ALE Output As mentioned earlier, the ADuC834 offers an extended 11-bit 3 GF1 General-Purpose Flag Bit stack pointer. The three extra bits to make up the 11-bit stack 2 GF0 General-Purpose Flag Bit pointer are the 3 LSBs of the SPH byte located at B7H. 1 PD Power-Down Mode Enable 0 IDL Idle Mode Enable Program Status Word (PSW) The PSW SFR contains several bits reflecting the current status of the CPU as detailed in Table I. ADuC834 CONFIGURATION SFR (CFG834) SFR Address D0H The CFG834 SFR contains the necessary bits to configure the Power-On Default Value 00H internal XRAM and the extended SP. By default it configures Bit Addressable Yes the user into 8051 mode, i.e., extended SP is disabled, internal XRAM is disabled. Table I. PSW SFR Bit Designations SFR Address AFH Power-On Default Value 00H Bit Name Description Bit Addressable No 7 CY Carry Flag 6 AC Auxiliary Carry Flag Table III. CFG834 SFR Bit Designations 5 F0 General-Purpose Flag Bit Name Description 4 RS1 Register Bank Select Bits 3 RS0 RS1 RS0 Selected Bank 7 EXSP Extended SP Enable. If this bit is set, the000stack will roll over from SPH/SP = 00FFH011to 0100H. If this bit is clear, the SPH SFR102will be disabled and the stack will roll113over from SP = FFH to SP = 00H 2 OV Overflow Flag 6 ––– Reserved for Future Use 1 F1 General-Purpose Flag 5 ––– Reserved for Future Use0PParity Bit 4 ––– Reserved for Future Use 3 ––– Reserved for Future Use Power Control SFR (PCON) 2 ––– Reserved for Future Use The PCON SFR contains bits for power-saving options and 1 ––– Reserved for Future Use general-purpose status flags as shown in Table II. 0 XRAMEN XRAM Enable Bit. If this bit is set, the The TIC (wake-up/RTC timer) can be used to accurately wake up internal XRAM will be mapped into the the ADuC834 from power-down at regular intervals. To use the lower 2 Kbytes of the external address TIC to wake up the ADuC834 from power-down, the OSC_PD space. If this bit is clear, the internal bit in the PLLCON SFR must be clear and the TIC must be XRAM will not be accessible and the enabled. external data memory will be mapped into the lower 2 Kbytes of external data SFR Address 87H memory. (See Figure 3.) Power-On Default Value 00H Bit Addressable No REV. A –15–,

COMPLETE SFR MAP implemented; i.e., no register exists at this location. If an unoccu- Figure 6 shows a full SFR memory map and the SFR contents pied location is read, an unspecified value is returned. SFR locations

after RESET. NOT USED indicates unoccupied SFR loca- that are reserved for future use are shaded (RESERVED) and tions. Unoccupied locations in the SFR address space are not should not be accessed by user software. ISPI WCOL SPE SPIM CPOL CPHA SPR1 SPICON DACL DACH DACCONSPR0 BITS RESERVED RESERVED RESERVED RESERVED FFH 0 FEH 0 FDH 0 FCH 0 FBH 0 FAH 1 F9H 0 F8H 0 F8H 04H FBH 00H FCH 00H FDH 00H B SPIDAT BITS RESERVED RESERVED NOT USED RESERVED RESERVED RESERVED F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H 0 F1H 0 F0H 0 F0H 00H F7H 00H11111I2CCON GN0L GN0M GN0H GN1L GN1H MDO MDE MCO MDI I2CM I2CRS I2CTX I2CI BITS RESERVED RESERVED EFH 0 EEH 0 EDH 0 ECH 0 EBH 0 EAH 0 E9H 0 E8H 0 E8H 00H E9H 55H EAH 55H EBH 53H ECH 9AH EDH 59H ACC OF0L OF0M OF0H OF1L OF1H BITS RESERVED RESERVED E7H 0 E6H 0 E5H 0 E4H 0 E3H 0 E2H 0 E1H 0 E0H 0 E0H 00H E1H 00H E2H 00H E3H 80H E4H 00H E5H 80H RDY0 RDY1 CAL NOXREF ERR0 ERR1 ADCSTAT ADC0L ADC0M ADC0H ADC1L ADC1H PSMCON BITS RESERVED DFH 0 DEH 0 DDH 0 DCH 0 DBH 0 DAH 0 D9H 0 D8H 0 D8H 00H D9H 00H DAH 00H DBH 00H DCH 00H DDH 00H DFH DEH CY AC F0 RSI RS0 OV FI P PSW ADCMODE ADC0CON ADC1CON SF ICON PLLCON BITS RESERVED D7H 0 D6H 0 D5H 0 D4H 0 D3H 0 D2H 0 D1H 0 D0H 0 D0H 00H D1H 00H D2H 07H D3H 00H D4H 45H D5H 00H D7H 03H TF2 EXF2 RCLK TCLK EXEN2 TR2 CNT2 CAP2 T2CON RCAP2L RCAP2H TL2 TH2 BITS RESERVED RESERVED RESERVED CFH 0 CEH 0 CDH 0 CCH 0 CBH 0 CAH 0 C9H 0 C8H 0 C8H 00H CAH 00H CBH 00H CCH 00H CDH 00H PRE3 PRE2 PRE1 PRE0 WDIR WDS WDE WDWR WDCON CHIPID EADRL EADRH BITS RESERVED RESERVED RESERVED RESERVED C7H 0 C6H 0 C5H 0 C4H 1 C3H 0 C2H 0 C1H 0 C0H 0 C0H 10H C2H 2H C6H 00H C7H 00H PADC PT2 PS PT1 PX1 PT0 PX0 IP ECON EDATA1 EDATA2 EDATA3 EDATA4 BITS RESERVED RESERVED BFH 0 BEH 0 BDH 0 BCH 0 BBH 0 BAH B9H 0 B8H 0 B8H 00H B9H 00H BCH 00H BDH 00H BEH 00H BFH 00H RD WR T1 T0 INT1 INT0 TXD RXD P3 PWM0L PWM0H PWM1L PWM1H SPH BITS RESERVED RESERVED B7H 1 B6H 1 B5H 1 B4H 1 B3H 1 B2H 1 B1H 1 B0H 1 B0H FFH B1H 00H B2H 00H B3H 00H B4H 00H B7H 00H EA EADC ET2 ES ET1 EX1 ET0 EX0 IE IEIP2 PWMCON CFG834 BITS RESERVED RESERVED RESERVED RESERVED AFH 0 AEH 0 ADH 0 ACH 0 ABH 0 AAH 0 A9H 0 A8H 0 A8H 00H A9H A0H AEH 00H AFH 00H2222P2 TIMECON HTHSEC SEC MIN HOUR INTVAL DPCON

BITS

A7H 1 A6H 1 A5H 1 A4H 1 A3H 1 A2H 1 A1H 1 A0H 1 A0H FFH A1H 00H A2H 00H A3H 00H A4H 00H A5H 00H A6H 00H A7H 00H SM0 SM1 SM2 REN TB8 RB8 T1 R1 SCON SBUF T3FD T3CON BITS RESERVED RESERVED NOT USED RESERVED 9FH 0 9EH 0 9DH 0 9CH 0 9BH 0 9AH 0 99H 0 98H 0 98H 00H 99H 00H 9DH 00H 9EH 00H T2EX T2 P1 BITS RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED 97H 1 96H 1 95H 1 94H 1 93H 1 92H 1 91H 1 90H 1 90H FFH TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TCON TMOD TL0 TL1 TH0 TH1BITS RESERVED RESERVED 8FH 0 8EH 0 8DH 0 8CH 0 8BH 0 8AH 0 89H 0 88H 0 88H 00H 89H 00H 8AH 00H 8BH 00H 8CH 00H 8DH 00H P0 SP DPL DPH DPP PCON BITS RESERVED RESERVED 87H 1 86H 1 85H 1 84H 1 83H 1 82H 1 81H 1 80H 1 80H FFH 81H 07H 82H 00H 83H 00H 84H 00H 87H 00H

NOTES

1CALIBRATION COEFFICIENTS ARE PRECONFIGURED AT POWER-UP TO FACTORY CALIBRATED VALUES. 2THESE SFRS MAINTAIN THEIR PRERESET VALUES AFTER A RESET IF TIMECON.0 = 1.

SFR MAP KEY: THESE BITS ARE CONTAINED IN THIS BYTE. BIT MNEMONIC IE0 IT0 TCON MNEMONIC BIT BIT ADDRESS 89H 0 88H 0 88H 00H RESET DEFAULT VALUE RESET DEFAULT SFR ADDRESS BIT VALUE SFR NOTE: SFRs WHOSE ADDRESSES END IN 0H OR 8H ARE BIT-ADDRESSABLE. Figure 6. Special Function Register Locations and Their Reset Default Values

–16– REV. A, ADC SFR INTERFACE Both ADCs are controlled and configured via a number of SFRs that are mentioned here and described in more detail in the following pages. ADCSTAT ADC Status Register. Holds general status of ADC0L/M/H Primary ADC 24-bit conversion result is held the primary and auxiliary ADCs. in these three 8-bit registers. ADCMODE ADC Mode Register. Controls general modes ADC1L/H Auxiliary ADC 16-bit conversion result is held of operation for primary and auxiliary ADCs. in these two 8-bit registers. ADC0CON Primary ADC Control Register. Controls OF0L/M/H Primary ADC 24-bit Offset Calibration specific configuration of primary ADC. Coefficient is held in these three 8-bit registers. ADC1CON Auxiliary ADC Control Register. Controls OF1L/H Auxiliary ADC 16-bit Offset Calibration specific configuration of auxiliary ADC. Coefficient is held in these two 8-bit registers. SF Sinc Filter Register. Configures the decimation GN0L/M/H Primary ADC 24-bit Gain Calibration factor for the Sinc3 filter and thus the primary Coefficient is held in these three 8-bit registers. and auxiliary ADC update rates. GN1L/H Auxiliary ADC 16-bit Gain Calibration ICON Current Source Control Register. Allows Coefficient is held in these two 8-bit registers. user control of the various on-chip current source options. ADCSTAT—(ADC Status Register) This SFR reflects the status of both ADCs including data ready, calibration, and various (ADC-related) error and warning conditions including reference detect and conversion overflow/underflow flags. SFR Address D8H Power-On Default Value 00H Bit Addressable Yes Table IV. ADCSTAT SFR Bit Designations Bit Name Description 7 RDY0 Ready Bit for primary ADC. Set by hardware on completion of ADC conversion or calibration cycle. Cleared directly by the user or indirectly by write to the mode bits to start another primary ADC conversion or calibration. The primary ADC is inhibited from writing further results to its data or calibration registers until the RDY0 bit is cleared. 6 RDY1 Ready Bit for auxiliary ADC. Same definition as RDY0 referred to the auxiliary ADC. 5 CAL Calibration Status Bit. Set by hardware on completion of calibration. Cleared indirectly by a write to the mode bits to start another ADC conversion or calibration. 4 NOXREF No External Reference Bit (only active if primary or auxiliary ADC is active). Set to indicate that one or both of the REFIN pins is floating or the applied voltage is below a specified threshold. When Set, conversion results are clamped to all ones, if using external reference. Cleared to indicate valid VREF. 3 ERR0 Primary ADC Error Bit. Set by hardware to indicate that the result written to the primary ADC data registers has been clamped to all zeros or all ones. After a calibration, this bit also flags error conditions that caused the calibration registers not to be written. Cleared by a write to the mode bits to initiate a conversion or calibration. 2 ERR1 Auxiliary ADC Error Bit. Same definition as ERR0 referred to the auxiliary ADC. 1 ––– Reserved for Future Use 0 ––– Reserved for Future Use REV. A –17–, ADCMODE (ADC Mode Register) Used to control the operational mode of both ADCs. SFR Address D1H Power-On Default Value 00H Bit Addressable No Table V. ADCMODE SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 ––– Reserved for Future Use 5 ADC0EN Primary ADC Enable. Set by the user to enable the primary ADC and place it in the mode selected in MD2–MD0 below. Cleared by the user to place the primary ADC in power-down mode. 4 ADC1EN Auxiliary ADC Enable. Set by the user to enable the auxiliary ADC and place it in the mode selected in MD2–MD0 below. Cleared by the user to place the auxiliary ADC in power-down mode. 3 ––– Reserved for Future Use 2 MD2 Primary and auxiliary ADC Mode bits. 1 MD1 These bits select the operational mode of the enabled ADC as follows: 0 MD0 MD2 MD1 MD0000ADC Power-Down Mode (Power-On Default) 001Idle Mode. In Idle Mode, the ADC filter and modulator are held in a reset state although the modulator clocks are still provided. 010Single Conversion Mode. In Single Conversion Mode, a single conversion is performed on the enabled ADC. On completion of the conversion, the ADC data registers (ADC0H/M/L and/or ADC1H/L) are updated, the relevant flags in the ADCSTAT SFR are written, and power-down is re-entered with the MD2–MD0 accordingly being written to 000. 011Continuous Conversion. In Continuous Conversion Mode, the ADC data registers are regularly updated at the selected update rate (see SF Register). 100Internal Zero-Scale Calibration. Internal short automatically connected to the enabled ADC input(s). 101Internal Full-Scale Calibration Internal or External VREF (as determined by XREF0 and XREF1 bits in ADC0/1CON) is automatically connected to the enabled ADC input(s) for this calibration. 110System Zero-Scale Calibration. User should connect system zero-scale input to the enabled ADC input(s) as selected by CH1/CH0 and ACH1/ACH0 bits in the ADC0/1CON Register. 111System Full-Scale Calibration. User should connect system full-scale input to the enabled ADC input(s) as selected by CH1/CH0 and ACH1/ACH0 bits in the ADC0/1CON Register.

NOTES

1. Any change to the MD bits will immediately reset both ADCs. A write to the MD2–0 Bits with no change is also treated as a reset. (See exception to this in Note 3 below.) 2. If ADC0CON is written when ADC0EN = 1, or if ADC0EN is changed from 0 to 1, then both ADCs are also immediately reset. In other words, the primary ADC is given priority over the auxiliary ADC and any change requested on the primary ADC is immediately responded to. 3. On the other hand, if ADC1CON is written or if ADC1EN is changed from 0 to 1, only the auxiliary ADC is reset. For example, if the primary ADC is continuously converting when the auxiliary ADC change or enable occurs, the primary ADC continues undisturbed. Rather than allow the auxiliary ADC to operate with a phase difference from the primary ADC, the auxiliary ADC will fall into step with the outputs of the primary ADC. The result is that the first conversion time for the auxiliary ADC will be delayed up to three outputs while the auxiliary ADC update rate is synchronized to the primary ADC. 4. Once ADCMODE has been written with a calibration mode, the RDY0/1 bits (ADCSTAT) are immediately reset and the calibration commences. On completion, the appropriate calibration registers are written, the relevant bits in ADCSTAT are written, and the MD2–0 bits are reset to 000 to indicate the ADC is back in power-down mode. 5. Any calibration request of the auxiliary ADC while the temperature sensor is selected will fail to complete. Although the RDY1 bit will be set at the end of the calibration cycle, no update of the calibration SFRs will take place and the ERR1 bit will be set. 6. Calibrations are performed at maximum SF (see SF SFR) value guaranteeing optimum calibration operation. –18– REV. A, ADC0CON (Primary ADC Control Register) and ADC1CON (Auxiliary ADC Control Register) The ADC0CON and ADC1CON SFRs are used to configure the primary and auxiliary ADC for reference and channel selection, unipolar or bipolar coding and, in the case of the primary ADC, for range (the auxiliary ADC operates on a fixed input range of ±VREF). ADC0CON Primary ADC Control SFR ADC1CON Auxiliary ADC Control SFR SFR Address D2H SFR Address D3H Power-On Default Value 07H Power-On Default Value 00H Bit Addressable No Bit Addressable No Table VI. ADC0CON SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 XREF0 Primary ADC External Reference Select Bit. Set by user to enable the primary ADC to use the external reference via REFIN(+)/REFIN(–). Cleared by user to enable the primary ADC to use the internal band gap reference (VREF = 1.25 V). 5 CH1 Primary ADC Channel Selection Bits 4 CH0 Written by the user to select the differential input pairs used by the primary ADC as follows: CH1 CH0 Positive Input Negative Input00AIN1 AIN201AIN3 AIN410AIN2 AIN2 (Internal Short) 1 1 AIN3 AIN2 3 UNI0 Primary ADC Unipolar Bit. Set by user to enable unipolar coding, i.e., zero differential input will result in 000000H output. Cleared by user to enable bipolar coding, i.e., zero differential input will result in 800000H output. 2 RN2 Primary ADC Range Bits. 1 RN1 Written by the user to select the primary ADC input range as follows: 0 RN0 RN2 RN1 RN0 Selected Primary ADC Input Range (VREF = 2.5 V) 000±20 mV (0 mV–20 mV in Unipolar Mode) 001±40 mV (0 mV–40 mV in Unipolar Mode) 010±80 mV (0 mV–80 mV in Unipolar Mode) 011±160 mV (0 mV–160 mV in Unipolar Mode) 100±320 mV (0 mV–320 mV in Unipolar Mode) 101±640 mV (0 mV–640 mV in Unipolar Mode) 110±1.28 V (0 V–1.28 V in Unipolar Mode) 111±2.56 V (0 V–2.56 V in Unipolar Mode) Table VII. ADC1CON SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 XREF1 Auxiliary ADC External Reference Bit. Set by user to enable the auxiliary ADC to use the external reference via REFIN(+)/REFIN(–). Cleared by user to enable the auxiliary ADC to use the internal band gap reference. 5 ACH1 Auxiliary ADC Channel Selection Bits. 4 ACH0 Written by the user to select the single-ended input pins used to drive the auxiliary ADC as follows: ACH1 ACH0 Positive Input Negative Input00AIN3 AGND01AIN4 AGND10Temp Sensor AGND (Temp Sensor routed to the ADC input) 1 1 AIN5 AGND 3 UNI1 Auxiliary ADC Unipolar Bit. Set by user to enable unipolar coding, i.e., zero input will result in 0000H output. Cleared by user to enable bipolar coding, i.e., zero input will result in 8000H output. 2 ––– Reserved for Future Use 1 ––– Reserved for Future Use 0 ––– Reserved for Future Use

NOTES

1. When the temperature sensor is selected, user code must select internal reference via XREF1 bit above and clear the UNI1 bit (ADC1CON.3) to select bipolar coding. 2. The temperature sensor is factory calibrated to yield conversion results 8000H at 0 °C. 3. A +1°C change in temperature will result in a +1 LSB change in the ADC1H Register ADC conversion result.

REV. A –19–

, ADC0H/ADC0M/ADC0L (Primary ADC Conversion Result Registers) These three 8-bit registers hold the 24-bit conversion result from the primary ADC. SFR Address ADC0H High Data Byte DBH ADC0M Middle Data Byte DAH ADC0L Low Data Byte D9H Power-On Default Value 00H ADC0H, ADC0M, ADC0L Bit Addressable No ADC0H, ADC0M, ADC0L ADC1H/ADC1L (Auxiliary ADC Conversion Result Registers) These two 8-bit registers hold the 16-bit conversion result from the auxiliary ADC. SFR Address ADC1H High Data Byte DDH ADC1L Low Data Byte DCH Power-On Default Value 00H ADC1H, ADC1L Bit Addressable No ADC1H, ADC1L OF0H/OF0M/OF0L (Primary ADC Offset Calibration Registers*) These three 8-bit registers hold the 24-bit offset calibration coefficient for the primary ADC. These registers are configured at power-on with a factory default value of 800000H. However, these bytes will be automatically overwritten if an internal or system zero-scale calibration of the primary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register. SFR Address OF0H Primary ADC Offset Coefficient High Byte E3H OF0M Primary ADC Offset Coefficient Middle Byte E2H OF0L Primary ADC Offset Coefficient Low Byte E1H Power-On Default Value 800000H OF0H, OF0M, OF0L, respectively Bit Addressable No OF0H, OF0M, OF0L OF1H/OF1L (Auxiliary ADC Offset Calibration Registers*) These two 8-bit registers hold the 16-bit offset calibration coefficient for the auxiliary ADC. These registers are configured at power-on with a factory default value of 8000H. However, these bytes will be automatically overwritten if an internal or system zero-scale cali- bration of the auxiliary ADC is initiated by the user via the MD2–0 bits in the ADCMODE Register. SFR Address OF1H Auxiliary ADC Offset Coefficient High Byte E5H OF1L Auxiliary ADC Offset Coefficient Low Byte E4H Power-On Default Value 8000H OF1H and OF1L, respectively Bit Addressable No OF1H, OF1L GN0H/GN0M/GN0L (Primary ADC Gain Calibration Registers*) These three 8-bit registers hold the 24-bit gain calibration coefficient for the primary ADC. These registers are configured at power-on with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these bytes will be automatically overwritten if an internal or system full-scale calibration of the primary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register. SFR Address GN0H Primary ADC Gain Coefficient High Byte EBH GN0M Primary ADC Gain Coefficient Middle Byte EAH GN0L Primary ADC Gain Coefficient Low Byte E9H Power-On Default Value Configured at Factory Final Test; see Notes above. Bit Addressable No GN0H, GN0M, GN0L GN1H/GN1L (Auxiliary ADC Gain Calibration Registers*) These two 8-bit registers hold the 16-bit gain calibration coefficient for the auxiliary ADC. These registers are configured at power-on with a factory-calculated internal full-scale calibration coefficient. Every device will have an individual coefficient. However, these bytes will be automatically overwritten if an internal or system full-scale calibration of the auxiliary ADC is initiated by the user via MD2–0 bits in the ADCMODE Register. SFR Address GN1H Auxiliary ADC Gain Coefficient High Byte EDH GN1L Auxiliary ADC Gain Coefficient Low Byte ECH Power-On Default Value Configured at Factory Final Test; see Notes above. Bit Addressable No GN1H, GN1L *These registers can be overwritten by user software only if Mode bits MD0–2 (ADCMODE SFR) are zero. –20– REV. A, SF (Sinc Filter Register) value for the SF Register is 45H, resulting in a default ADC The number in this register sets the decimation factor and thus update rate of just under 20 Hz. Both ADC inputs are chopped the output update rate for the primary and auxiliary ADCs. to minimize offset errors, which means that the settling time for This SFR cannot be written by user software while either ADC a single conversion, or the time to a first conversion result in is active. The update rate applies to both primary and auxiliary Continuous Conversion mode, is 2 tADC. As mentioned earlier, ADCs and is calculated as follows: all calibration cycles will be carried out automatically witha11maximum, i.e., FFH, SF value to ensure optimum calibration fADC = × × fMOD performance. Once a calibration cycle has completed, the value3 8 × SF in the SF Register will be that programmed by user software. Where: fADC = ADC Output Update Rate Table VIII. SF SFR Bit Designations fMOD = Modulator Clock Frequency = 32.768 kHz SF = Decimal Value of SF Register SF(dec) SF(hex) fADC(Hz) tADC(ms) The allowable range for SF is 0DH to FFH. Examples of SF values 13 0D 105.3 9.52 and corresponding conversion update rates (fADC) and conversion 69 45 19.79 50.34 times (tADC) are shown in Table VIII. The power-on default 255 FF 5.35 186.77 ICON (Current Sources Control Register) Used to control and configure the various excitation and burnout current source options available on-chip. SFR Address D5H Power-On Default Value 00H Bit Addressable No Table IX. ICON SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 BO Burnout Current Enable Bit. Set by user to enable both transducer burnout current sources in the primary ADC signal paths. Cleared by user to disable both transducer burnout current sources. 5 ADC1IC Auxiliary ADC Current Correction Bit. Set by user to allow scaling of the auxiliary ADC by an internal current source calibration word. 4 ADC0IC Primary ADC Current Correction Bit. Set by user to allow scaling of the primary ADC by an internal current source calibration word. 3 I2PIN* Current Source-2 Pin Select Bit. Set by user to enable current source-2 (200 A) to external Pin 3 (P1.2/DAC/IEXC1). Cleared by user to enable current source-2 (200 A) to external Pin 4 (P1.3/AIN5/IEXC2). 2 I1PIN* Current Source-1 Pin Select Bit. Set by user to enable current source-1 (200 A) to external Pin 4 (P1.3/AIN5/IEXC2). Cleared by user to enable current source-1 (200 A) to external Pin 3 (P1.2/DAC/IEXC1). 1 I2EN Current Source-2 Enable Bit. Set by user to turn on excitation current source-2 (200 A). Cleared by user to turn off excitation current source-2 (200 A). 0 I1EN Current Source-1 Enable Bit. Set by user to turn on excitation current source-1 (200 A). Cleared by user to turn off excitation current source-1 (200 A). *Both current sources can be enabled to the same external pin, yielding a 400 A current source. REV. A –21–, PRIMARY AND AUXILIARY ADC NOISE selected via the Sinc Filter (SF) SFR. It is important to note PERFORMANCE that the peak-to-peak resolution figures represent the resolution Tables X, XI, and XII show the output rms noise in V and for which there will be no code flicker within a six-sigma limit. output peak-to-peak resolution in bits (rounded to the nearest The QuickStart Development system PC software comes 0.5 LSB) for some typical output update rates on both the primary complete with an ADC noise evaluation tool. This tool can be and auxiliary ADCs. The numbers are typical and are generated easily used with the evaluation board to see these figures from at a differential input voltage of 0 V. The output update rate is silicon. Table X. Primary ADC, Typical Output RMS Noise (V) Typical Output RMS Noise vs. Input Range and Update Rate; Output RMS Noise in V SF Data Update Input Range Word Rate (Hz) 20 mV 40 mV 80 mV 160 mV 320 mV 640 mV 1.28 V 2.56 V 13 105.3 1.50 1.50 1.60 1.75 3.50 4.50 6.70 11.75 69 19.79 0.60 0.65 0.65 0.65 0.65 0.95 1.40 2.30 255 5.35 0.35 0.35 0.37 0.37 0.37 0.51 0.82 1.25 Table XI. Primary ADC, Peak-to-Peak Resolution (Bits) Peak-to-Peak Resolution vs. Input Range and Update Rate; Peak-to-Peak Resolution in Bits SF Data Update Input Range Word Rate (Hz) 20 mV 40 mV 80 mV 160 mV 320 mV 640 mV 1.28 V 2.56 V 13 105.3 12 13 14 15 15 15.5 16 16 69 19.79 13.5 14 15 16 17 17.5 18 18.5 255 5.35 14 15 16 17 18 18.5 19 19.5 Typical RMS Resolution vs. Input Range and Update Rate: RMS Resolution in Bits* SF Data Update Input Range Word Rate (Hz) 20 mV 40 mV 80 mV 160 mV 320 mV 640 mV 1.28 V 2.56 V 13 105.3 14.7 15.7 16.7 17.7 17.7 18.2 18.7 18.7 69 19.79 16.2 16.7 17.7 18.7 19.7 20.2 20.7 21.2 255 5.35 16.7 17.7 18.7 19.7 20.7 21.2 21.7 22.2 *Based on a six-sigma limit, the rms resolution is 2.7 bits greater than the peak-to-peak resolution. Table XII. Auxiliary ADC Typical Output RMS Noise vs. Update Rate* Peak-to-Peak Resolution vs. Update Rate1 Output RMS Noise in V Peak-to-Peak Resolution in Bits SF Data Update Input Range SF Data Update Input Range Word Rate (Hz) 2.5 V Word Rate (Hz) 2.5 V 13 105.3 10.75 13 105.3 162 69 19.79 2.00 69 19.79 16 255 5.35 1.15 255 5.35 16 *ADC converting in Bipolar mode NOTES 1ADC converting in Bipolar mode 2In Unipolar mode, peak-to-peak resolution at 105 Hz is 15 bits. –22– REV. A,

PRIMARY AND AUXILIARY ADC CIRCUIT DESCRIPTION allowing R/C filtering (for noise rejection or RFI reduction) to be Overview placed on the analog inputs if required. On-chip burnout currents The ADuC834 incorporates two independent - ADCs (primary can also be turned on. These currents can be used to check that

and auxiliary) with on-chip digital filtering intended for the measure- a transducer on the selected channel is still operational before ment of wide dynamic range, low frequency signals such as those attempting to take measurements. in weigh-scale, strain gage, pressure transducer, or temperature The ADC employs a - conversion technique to realize up to measurement applications. 24 bits of no missing codes performance. The - modulator con-

Primary ADC verts the sampled input signal into a digital pulse train whose duty This ADC is intended to convert the primary sensor input. The cycle contains the digital information. A Sinc3 programmable low-

input is buffered and can be programmed for one of eight input pass filter is then employed to decimate the modulator output data ranges from ±20 mV to ±2.56 V being driven from one of three stream to give a valid data conversion result at programmable differential input channel options AIN1/2, AIN3/4, or AIN3/2. output rates from 5.35 Hz (186.77 ms) to 105.03 Hz (9.52 ms).

The input channel is internally buffered, allowing the part to A chopping scheme is also employed to minimize ADC offset errors.

handle significant source impedances on the analog input and A block diagram of the primary ADC is shown in Figure 7.

DIFFERENTIAL REFERENCE

PROGRAMMABLE GAIN AMPLIFIER THE EXTERNAL REFERENCE ANALOG INPUT CHOPPING INPUT TO THE ADuC834 IS THE PROGRAMMABLE DIFFERENTIAL AND THE INPUTS ARE - ADCGAIN AMPLIFIER ALLOWS FACILITATES RATIOMETRIC OUTPUT AVERAGE ALTERNATELY REVERSED EIGHT UNIPOLAR AND OPERATION. THE EXTERNAL THE - ARCHITECTURE THROUGH THE EIGHT BIPOLAR INPUT AS PART OF THE CHOPPINGREFERENCE VOLTAGE IS CONVERSION CYCLE. ENSURES 24 BITS NOBURNOUT CURRENTS RANGES FROM 20mV TO IMPLEMENTATION, EACHSELECTED VIA THE XREF0 BIT CHOPPING YIELDS MISSING CODES. THE2.56V (EXT VREF = 2.5V). DATA-WORD OUTPUT IN ADC0CON. TWO 100nA BURNOUT EXCELLENT ADC OFFSET ENTIRE - ADC IS FROM THE FILTER ISREFERENCE DETECT CURRENTS ALLOW THE AND OFFSET DRIFT CHOPPED TO REMOVE SUMMED AND AVERAGEDCIRCUITRY TESTS FOR OPEN OR USER TO EASILY DETECT PERFORMANCE. DRIFT ERROR. WITH ITS PREDECESSORSHORTED REFERENCE INPUTS. IF A TRANSDUCER HAS TO NULL ADC CHANNEL BURNED OUT OR GONE OFFSET ERRORS . OPEN-CIRCUIT. REFIN(–) REFIN(+) AVDD DIGTAL OUTPUT - ADC RESULT WRITTEN TO ADC0H/M/L AIN1 SFRSBUFFER PROGRAMMABLE - OUTPUTDIGITAL OUTPUT AIN2 MODULATOR AVERAGE SCALING MUX PGA FILTER AIN3

CHOP

AIN4

CHOP AGND

OUTPUT SCALING THE OUPUT WORD FROM THE ANALOG MULTIPLEXER DIGITAL FILTER IS SCALED BY THE CALIBRATION A DIFFERENTIAL MULTIPLEXER - MODULATOR PROGRAMMABLE COEFFICIENTS BEFORE ALLOWS SELECTION OF THREE DIGITAL FILTER BEING PROVIDED AS FULLY DIFFERENTIAL PAIR OPTIONS AND BUFFER AMPLIFIER ADDITIONAL INTERNAL SHORT OPTION THE MODULATOR PROVIDES THE CONVERSION RESULT. (AIN2–AIN2). THE MULTIPLEXER IS THE BUFFER AMPLIFIER A HIGH FREQUENCY 1-BIT THE SINC FILTER REMOVES CONTROLLED VIA THE CHANNEL PRESENTS A HIGH DATA STREAM (THE OUTPUT QUANTIZATION NOISE INTRODUCED BY THE MODULATOR. THE UPDATE SELECTION BITS IN ADC0CON. IMPEDANCE INPUT STAGE OF WHICH IS ALSO CHOPPED) FOR THE ANALOG INPUTS, TO THE DIGITAL FILTER, RATE AND BANDWIDTH OF THIS ALLOWING SIGNIFICANT THE DUTY CYCLE OF WHICH FILTER ARE PROGRAMMABLE EXTERNAL SOURCE REPRESENTS THE SAMPLED VIA THE SF SFR. IMPEDANCES. ANALOG INPUT VOLTAGE .

Figure 7. Primary ADC Block Diagram REV. A –23–

,

Auxiliary ADC The auxiliary ADC has three external input pins (labelled AIN3 to The auxiliary ADC is intended to convert supplementary inputs AIN5) as well as an internal connection to the on-chip temperature

such as those from a cold junction diode or thermistor. This ADC sensor. All inputs to the auxiliary ADC are single-ended inputs is not buffered and has a fixed input range of0Vto 2.5 V referenced to the AGND on the part. Channel selection bits in (assuming an external 2.5 V reference). The single-ended inputs the ADC1CON SFR previously detailed in Table VII allow can be driven from AIN3, AIN4, or AIN5 Pins, or directly from selection of one of four inputs. the on-chip temperature sensor voltage. A block diagram of the Two input multiplexers switch the selected input channel to the auxiliary ADC is shown in Figure 8. on-chip buffer amplifier in the case of the primary ADC and

Analog Input Channels directly to the - modulator input in the case of the auxiliary The primary ADC has four associated analog input pins (labelled ADC. When the analog input channel is switched, the settling AIN1 to AIN4) that can be configured as two fully differential input time of the part must elapse before a new valid word is available

channels. Channel selection bits in the ADC0CON SFR detailed from the ADC. in Table VI allow three combinations of differential pair selection as well as an additional shorted input option (AIN2–AIN2). DIFFERENTIAL REFERENCE THE EXTERNAL REFERENCE INPUT TO THE ADuC834 IS DIFFERENTIAL AND FACILITATES RATIOMETRIC OPERATION. THE EXTERNAL REFERENCE VOLTAGE IS SELECTED - ADC OUTPUT AVERAGE ANALOG INPUT CHOPPING VIA THE XREF1 BIT IN ADC1CON. AS PART OF THE CHOPPING REFERENCE DETECT THE - ARCHITECTURE CIRCUITRY TESTS FOR OPEN OR ENSURES 16 BITS NO MISSING IMPLEMENTATION, EACH THE INPUTS ARE ALTERNATELY DATA-WORD OUTPUTCODES. THE ENTIRE - ADC REVERSED THROUGH THE SHORTED REFERENCE INPUTS. FROM THE FILTER ISIS CHOPPED TO REMOVE CONVERSION CYCLE. CHOPPING SUMMED AND AVERAGEDDRIFT ERRORS. YIELDS EXCELLENT ADC WITH ITS PREDECESSOR OFFSET AND OFFSET DRIFT TO NULL ADC CHANNEL PERFORMANCE. OFFSET ERRORS. REFIN(–) REFIN(+) - ADC DIGTAL OUTPUT AIN3 RESULT WRITTENTO ADC1H/L SFRs - PROGRAMMABLE OUTPUT OUTPUT AIN4 MODULATOR DIGITAL FILTER AVERAGE SCALING

MMUUX

AIN5 X ON-CHIP CHOP TEMPERATURE CHOP

SENSOR

OUTPUT SCALING THE OUPUT WORD FROM THE ANALOG MULTIPLEXER DIGITAL FILTER IS SCALED BYTHE CALIBRATION A DIFFERENTIAL MULTIPLEXER PROGRAMMABLE DIGITAL COEFFICIENTS BEFORE ALLOWS SELECTION OF THREE - MODULATOR FILTER BEING PROVIDED AS EXTERNAL SINGLE ENDED INPUTS THE CONVERSION RESULT. OR THE ON-CHIP TEMP. SENSOR. THE MODULATOR PROVIDES A THE SINC3 FILTER REMOVES THE MULTIPLEXER IS CONTROLLED HIGH FREQUENCY 1-BIT DATA QUANTIZATION NOISE INTRODUCED VIA THE CHANNEL SELECTION STREAM (THE OUTPUT OF WHICH BY THE MODULATOR. THE UPDATE BITS IN ADC1CON. IS ALSO CHOPPED) TO THE RATE AND BANDWIDTH OF THIS DIGITAL FILTER, FILTER ARE PROGRAMMABLE THE DUTY CYCLE OF WHICH VIA THE SF SFR. REPRESENTS THE SAMPLED ANALOG INPUT VOLTAGE.

Figure 8. Auxiliary ADC Block Diagram

–24– REV. A, Primary and Auxiliary ADC Inputs 19.372 The output of the primary ADC multiplexer feeds into a high 19.371 impedance input stage of the buffer amplifier. As a result, the pri- mary ADC inputs can handle significant source impedances and 19.370 are tailored for direct connection to external resistive-type sensors like strain gages or Resistance Temperature Detectors (RTDs). 19.369 The auxiliary ADC, however, is unbuffered, resulting in higher 19.368 analog input current on the auxiliary ADC. It should be noted that this unbuffered input path provides a dynamic load to the 19.367 driving source. Therefore, resistor/capacitor combinations on 19.366 the input pins can cause dc gain errors depending on the output impedance of the source that is driving the ADC inputs. 19.365 Analog Input Ranges 19.364 The absolute input voltage range on the primary ADC is restricted SAMPLE COUNT 0 100 200 300 400 500 600 700 800 to between AGND + 100 mV to AVDD – 100 mV. Care must be ADC RANGE taken in setting up the common-mode voltage and input voltage range so that these limits are not exceeded; otherwise there will be a degradation in linearity performance. Figure 9. Primary ADC Range Matching The absolute input voltage range on the auxiliary ADC is restricted Bipolar/Unipolar Inputs to between AGND – 30 mV to AVDD + 30 mV. The slightly The analog inputs on the ADuC834 can accept either unipolar or negative absolute input voltage limit does allow the possibility bipolar input voltage ranges. Bipolar input ranges do not imply that of monitoring small signal bipolar signals using the single-ended the part can handle negative voltages with respect to system AGND. auxiliary ADC front end. Unipolar and bipolar signals on the AIN(+) input on the primary Programmable Gain Amplifier ADC are referenced to the voltage on the respective AIN(–) The output from the buffer on the primary ADC is applied to the input. For example, if AIN(–) is 2.5 V and the primary ADC is input of the on-chip programmable gain amplifier (PGA). The configured for an analog input range of 0 mV to 20 mV, the input PGA can be programmed through eight different unipolar input voltage range on the AIN(+) input is 2.5 V to 2.52 V. If AIN(–) ranges and bipolar ranges. The PGA gain range is programmed is 2.5 V and the ADuC834 is configured for an analog input via the range bits in the ADC0CON SFR. With the external range of 1.28 V, the analog input range on the AIN(+) input is reference select bit set in the ADC0CON SFR and an external 1.22 V to 3.78 V (i.e., 2.5 V ± 1.28 V). 2.5 V reference, the unipolar ranges are 0 mV to 20 mV, 0 mV to As mentioned earlier, the auxiliary ADC input is a single-ended 40 mV, 0 mV to 80 mV, 0 mV to 160 mV, 0 mV to 320 mV, 0 mV input with respect to the system AGND. In this context, a bipolar to 640 mV, 0 V to 1.28 V, and 0 to 2.56 V; the bipolar ranges are signal on the auxiliary ADC can only span 30 mV negative with ±20 mV, ±40 mV, ±80 mV, ±160 mV, ±320 mV, ±640 mV, respect to AGND before violating the voltage input limits for ±1.28 V, and ±2.56 V. These are the nominal ranges that should this ADC. appear at the input to the on-chip PGA. An ADC range match- ing specification of2V(typ) across all ranges means that Bipolar or unipolar options are chosen by programming the calibration need only be carried out at a single gain range and primary and auxiliary Unipolar enable bits in the ADC0CON does not have to be repeated when the PGA gain range is changed. and ADC1CON SFRs respectively. This programs the relevant ADC for either unipolar or bipolar operation. Programming for Typical matching across ranges is shown in Figure 9. Here, the either unipolar or bipolar operation does not change any of the primary ADC is configured in bipolar mode with an external input signal conditioning; it simply changes the data output coding 2.5 V reference, while just greater than 19 mV is forced on its and the points on the transfer function where calibrations occur. inputs. The ADC continuously converts the dc input voltage at When an ADC is configured for unipolar operation, the output an update rate of 5.35 Hz, i.e., SF = FFH. In total, 800 conver- coding is natural (straight) binary with a zero differential input sion results are gathered. The first 100 results are gathered with voltage resulting in a code of 000 .000, a midscale voltage the primary ADC operating in the ±20 mV range. The ADC resulting in a code of 100 .000, and a full-scale input voltage range is then switched to ±40 mV, 100 more conversion results resulting in a code of 111 .111. When an ADC is configured are gathered, and so on until the last group of 100 samples is for bipolar operation, the coding is offset binary with a negative gathered with the ADC configured in the ±2.56 V range. From full-scale voltage resulting in a code of 000 .000, a zero Figure 9, the variation in the sample mean through each range, differential voltage resulting in a code of 100 .000, and a i.e., the range matching, is seen to be of the order of 2 V. positive full-scale voltage resulting in a code of 111 .111. The auxiliary ADC does not incorporate a PGA and is configured for a fixed single input range of 0 to VREF. REV. A –25– ADC INPUT VOLTAGE – mV 20mV 40mV 80mV 160mV 320mV 640mV 1.28V 2.56V, Reference Input If the voltage measured is 0 V, it indicates that the transducer The ADuC834’s reference inputs, REFIN(+) and REFIN(–), has short circuited. For normal operation, these burnout currents provide a differential reference input capability. The common- are turned off by writinga0to the BO bit in the ICON SFR. mode range for these differential inputs is from AGND to AVDD. The current sources work over the normal absolute input voltage The nominal reference voltage, VREF (REFIN(+) – REFIN(–)), range specifications. for specified operation is 2.5 V with the primary and auxiliary Excitation Currents reference enable bits set in the respective ADC0CON and/or The ADuC834 also contains two identical, 200 A constant ADC1CON SFRs. current sources. Both source current from AVDD to Pin 3 (IEXC1) The part is also functional (although not specified for performance) or Pin 4 (IEXC2). These current sources are controlled via bits when the XREF0 or XREF1 bits are 0, which enables the on-chip in the ICON SFR shown in Table IX. They can be configured internal band gap reference. In this mode, the ADCs will see the to source 200 A individually to both pins or a combination of internal reference of 1.25 V, therefore halving all input ranges. both currents, i.e., 400 A, to either of the selected pins. These As a result of using the internal reference voltage, a noticeable current sources can be used to excite external resistive bridge or degradation in peak-to-peak resolution will result. Therefore, RTD sensors. for best performance, operation with an external reference is Reference Detect strongly recommended. The ADuC834 includes on-chip circuitry to detect if the part has In applications where the excitation (voltage or current) for the a valid reference for conversions or calibrations. If the voltage transducer on the analog input also drives the reference voltage between the external REFIN(+) and REFIN(–) pins goes below for the part, the effect of the low frequency noise in the excitation 0.3 V or either the REFIN(+) or REFIN(–) inputs is open circuit, source will be removed as the application is ratiometric. If the the ADuC834 detects that it no longer has a valid reference. In ADuC834 is not used in a ratiometric application, a low noise this case, the NOXREF bit of the ADCSTAT SFR is set to a 1. reference should be used. Recommended reference voltage sources If the ADuC834 is performing normal conversions and the for the ADuC834 include the AD780, REF43, and REF192. NOXREF bit becomes active, the conversion results revert to all It should also be noted that the reference inputs provide a high 1s. It is not necessary to continuously monitor the status of the impedance, dynamic load. Because the input impedance of each NOXREF bit when performing conversions. It is only necessary reference input is dynamic, resistor/capacitor combinations on to verify its status if the conversion result read from the ADC these inputs can cause dc gain errors depending on the output Data Register is all 1s. impedance of the source that is driving the reference inputs. If the ADuC834 is performing either an offset or gain calibration Reference voltage sources, like those recommended above and the NOXREF bit becomes active, the updating of the respec- (e.g., AD780), will typically have low output impedances and tive calibration registers is inhibited to avoid loading incorrect therefore decoupling capacitors on the REFIN(+) input would coefficients to these registers, and the appropriate ERR0 or be recommended. Deriving the reference input voltage across an ERR1 bits in the ADCSTAT SFR are set. If the user is concerned external resistor, as shown in Figure 66, will mean that the refer- about verifying that a valid reference is in place every time a ence input sees a significant external source impedance. External calibration is performed, the status of the ERR0 or ERR1 bit decoupling on the REFIN(+) and REFIN(–) pins would not be should be checked at the end of the calibration cycle. recommended in this type of circuit configuration. - Modulator Burnout Currents A - ADC generally consists of two main blocks, an analog The primary ADC on the ADuC834 contains two 100 nA constant modulator and a digital filter. In the case of the ADuC834 current generators, one sourcing current from AVDD to AIN(+), ADCs, the analog modulators consist of a difference amplifier, and one sinking from AIN(–) to AGND. The currents are switched an integrator block, a comparator, and a feedback DAC as to the selected analog input pair. Both currents are either on or illustrated in Figure 10. off, depending on the Burnout Current Enable (BO) bit in the ICON SFR (see Table IX). These currents can be used to verify ANALOG DIFFERENCE COMPARATOR that an external transducer is still operational before attempting INPUT AMP HIGH

FREQUENCY

to take measurements on that channel. Once the burnout cur- INTEGRATOR BITSTREAM rents are turned on, they will flow in the external transducer TO DIGITALFILTER circuit, and a measurement of the input voltage on the analog input channel can be taken. If the resultant voltage measured is DAC full-scale, it indicates that the transducer has gone open-circuit. Figure 10. - Modulator Simplified Block Diagram –26– REV. A, In operation, the analog signal sample is fed to the difference The response of the filter, however, will change with SF word as amplifier along with the output of the feedback DAC. The can be seen in Figure 12, which shows >90 dB NMR at 50 Hz difference between these two signals is integrated and fed to the and >70 dB NMR at 60 Hz when SF = 255 dec. comparator. The output of the comparator provides the input to the feedback DAC so the system functions as a negative feedback 0 loop that tries to minimize the difference signal. The digital –10 data that represents the analog input voltage is contained in the –20 duty cycle of the pulse train appearing at the output of the com- –30 parator. This duty cycle data can be recovered as a data-word –40 using a subsequent digital filter stage. The sampling frequency of –50 the modulator loop is many times higher than the bandwidth –60 of the input signal. The integrator in the modulator shapes the –70 quantization noise (which results from the analog-to-digital conversion) so that the noise is pushed toward one-half of the –80 modulator frequency. –90 –100 Digital Filter –110 The output of the - modulator feeds directly into the digital filter. The digital filter then band-limits the response to a fre- –1200 10 20 30 40 50 60 70 80 90 110 quency significantly lower than one-half of the modulator frequency. FREQUENCY – Hz In this manner, the 1-bit output of the comparator is translated Figure 12. Filter Response, SF = 255 dec into a band-limited, low noise output from the ADuC834 ADCs. 3 Figures 13 and 14 show the NMR for 50 Hz and 60 Hz acrossThe ADuC834 filter is a low-pass, Sinc or (SIN x/x)3 filter the full range of SF word, i.e., SF = 13 dec to SF = 255 dec. whose primary function is to remove the quantization noise introduced at the modulator. The cutoff frequency and decimated 0 output data rate of the filter are programmable via the SF (Sinc –10 Filter) SFR as described in Table VIII. –20 Figure 11 shows the frequency response of the ADC channel at –30 the default SF word of 69 dec or 45H, yielding an overall output –40 update rate of just under 20 Hz. –50 It should be noted that this frequency response allows frequency –60 components higher than the ADC Nyquist frequency to pass –70 through the ADC, in some cases without significant attenuation. –80 These components may, therefore, be aliased and appear –90 in-band after the sampling process. –100 It should also be noted that rejection of mains-related frequency –110 components, i.e., 50 Hz and 60 Hz, is seen to be at a level of –120 >65 dB at 50 Hz and >100 dB at 60 Hz. This confirms the data 10 30 50 70 90 110 130 150 170 190 210 230 250 SF – Decimal sheet specifications for 50 Hz/60 Hz Normal Mode Rejection (NMR) at a 20 Hz update rate. Figure 13. 50 Hz Normal Mode Rejection vs. SF00–10 –10 –20 –20 –30 –30 –40 –40 –50 –50 –60 –60 –70 –70 –80 –80 –90 –90 –100 –100 –110 –110 –120 –120 0 10 20 30 40 50 60 70 80 90 100 110 10 30 50 70 90 110 130 150 170 190 210 230 250 FREQUENCY – Hz SF – Decimal

Figure 11. Filter Response, SF = 69 dec Figure 14. 60 Hz Normal Mode Rejection vs. SF REV. A –27–

GAIN – dB GAIN – dB GAIN – dB GAIN – dB, ADC Chopping input voltages provided to the input of the modulator during Both ADCs on the ADuC834 implement a chopping scheme calibration. The result of the zero-scale calibration conversion is whereby the ADC repeatedly reverses its inputs. The decimated stored in the Offset Calibration Registers for the appropriate digital output words from the Sinc3 filters therefore have a ADC. The result of the full-scale calibration conversion is stored positive offset and negative offset term included. in the Gain Calibration Registers for the appropriate ADC. As a result, a final summing stage is included in each ADC so With these readings, the calibration logic can calculate the offset that each output word from the filter is summed and averaged and the gain slope for the input-to-output transfer function of with the previous filter output to produce a new valid output the converter. result to be written to the ADC data SFRs. In this way, while During an internal zero-scale or full-scale calibration, the respective the ADC throughput or update rate is as discussed earlier and zero-scale input and full-scale input are automatically connected illustrated in Table VIII, the full settling time through the ADC to the ADC input pins internally to the device. A system calibra- (or the time to a first conversion result), will actually be given tion, however, expects the system zero-scale and system full-scale by 2 tADC. voltages to be applied to the external ADC pins before the cali- The chopping scheme incorporated in the ADuC834 ADC bration mode is initiated. In this way, external ADC errors are results in excellent dc offset and offset drift specifications and is taken into account and minimized as a result of system calibration. extremely beneficial in applications where drift, noise rejection, It should also be noted that to optimize calibration accuracy, all and optimum EMI rejection are important factors. ADuC834 ADC calibrations are carried out automatically at the slowest update rate. Calibration The ADuC834 provides four calibration modes that can be Internally in the ADuC834, the coefficients are normalized programmed via the mode bits in the ADCMODE SFR detailed before being used to scale the words coming out of the digital in Table V. In fact, every ADuC834 has already been factory filter. The offset calibration coefficient is subtracted from the calibrated. The resultant Offset and Gain calibration coeffi- result prior to the multiplication by the gain coefficient. cients for both the primary and auxiliary ADCs are stored From an operational point of view, a calibration should be on-chip in manufacturing-specific Flash/EE memory locations. treated like another ADC conversion. A zero-scale calibration At power-on or after reset, these factory calibration coefficients (if required) should always be carried out before a full-scale are automatically downloaded to the calibration registers in the calibration. System software should monitor the relevant ADC ADuC834 SFR space. Each ADC (primary and auxiliary) has RDY0/1 bit in the ADCSTAT SFR to determine end of calibra- dedicated calibration SFRs, these have been described earlier as tion via a polling sequence or interrupt driven routine. part of the general ADC SFR description. However, the factory calibration values in the ADC calibration SFRs will be overwrit- NONVOLATILE FLASH/EE MEMORY ten if any one of the four calibration options are initiated and Flash/EE Memory Overview that ADC is enabled via the ADC enable bits in ADCMODE. The ADuC834 incorporates Flash/EE memory technology on-chip Even though an internal offset calibration mode is described to provide the user with nonvolatile, in-circuit reprogrammable, below, it should be recognized that both ADCs are chopped. code and data memory space. Flash/EE memory is a relatively This chopping scheme inherently minimizes offset and means recent type of nonvolatile memory technology and is based on a that an internal offset calibration should never be required. Also, single transistor cell architecture. This technology is basically an because factory 5 V/25°C gain calibration coefficients are auto- outgrowth of EPROM technology and was developed through matically present at power-on, an internal full-scale calibration the late 1980s. Flash/EE memory takes the flexible in-circuit will only be required if the part is being operated at3Vor at reprogrammable features of EEPROM and combines them with temperatures significantly different from 25°C. the space efficient/density features of EPROM. (See Figure 15). The ADuC834 offers internal or system calibration facilities. For Because Flash/EE technology is based on a single transistor cell full calibration to occur on the selected ADC, the calibration architecture, a Flash memory array, like EPROM, can be imple- logic must record the modulator output for two different input mented to achieve the space efficiencies or memory densities conditions. These are zero-scale and full-scale points. These required by a given design. points are derived by performing a conversion on the different –28– REV. A, Like EEPROM, Flash memory can be programmed in-system at In reliability qualification, every byte in both the program and a byte level, although it must first be erased; the erase being data Flash/EE memory is cycled from 00H to FFH until a first performed in page blocks. Thus, Flash memory is often and fail is recorded, signifying the endurance limit of the on-chip more correctly referred to as Flash/EE memory. Flash/EE memory. As indicated in the specification pages of this data sheet, the EPROM EEPROM ADuC834 Flash/EE memory endurance qualification has been TECHNOLOGY TECHNOLOGY carried out in accordance with JEDEC Specification A117 over the industrial temperature range of –40°C, +25°C, +85°C, and SPACE EFFICIENT/ IN-CIRCUIT DENSITY REPROGRAMMABLE +125°C. The results allow the specification of a minimum endurance figure over supply and temperature of 100,000 FLASH/EE MEMORY cycles, with an endurance figure of 700,000 cycles being typical

TECHNOLOGY

of operation at 25°C. Figure 15. Flash/EE Memory Development Retention quantifies the ability of the Flash/EE memory to retain Overall, Flash/EE memory represents a step closer to the ideal its programmed data over time. Again, the ADuC834 has been memory device that includes nonvolatility, in-circuit program- qualified in accordance with the formal JEDEC Retention Life- mability, high density, and low cost. Incorporated in the time Specification (A117) at a specific junction temperature ADuC834, Flash/EE memory technology allows the user to (TJ = 55°C). As part of this qualification procedure, the update program code space in-circuit, without the need to replace Flash/EE memory is cycled to its specified endurance limit onetime programmable (OTP) devices at remote operating nodes. described above, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data Flash/EE Memory and the ADuC834 for its full specified retention lifetime every time the Flash/EE The ADuC834 provides two arrays of Flash/EE memory for memory is reprogrammed. It should also be noted that retention user applications. 62 Kbytes of Flash/EE Program space are lifetime, based on an activation energy of 0.6 eV, will derate provided on-chip to facilitate code execution without any exter- with TJ as shown in Figure 16. nal discrete ROM device requirements. The program memory can be programmed in-circuit, using the serial download mode 300 provided, using conventional third party memory programmers, or via any user defined protocol in User Download (ULOAD) Mode. 250A4Kbyte Flash/EE Data Memory space is also provided on-chip. This may be used as a general-purpose, nonvolatile scratchpad 200 area. User access to this area is via a group of seven SFRs. This ADI SPECIFICATION100 YEARS MIN. space can be programmed at a byte level, although it must first AT TJ = 55C150 be erased in 4-byte pages. ADuC834 Flash/EE Memory Reliability 100 The Flash/EE Program and Data Memory arrays on the ADuC834 are fully qualified for two key Flash/EE memory characteristics, 50 namely Flash/EE Memory Cycling Endurance and Flash/EE Memory Data Retention. 0 Endurance quantifies the ability of the Flash/EE memory to be 40 50 60 70 80 90 100 110TJ JUNCTION TEMPERATURE – C cycled through many Program, Read, and Erase cycles. In real terms, a single endurance cycle is composed of four independent, Figure 16. Flash/EE Memory Data Retention sequential events. These events are defined as: a. initial page erase sequence b. read/verify sequence A single Flash/EE Memory Endurance c. byte program sequence Cycle d. second read/verify sequence REV. A –29– RETENTION – Years, Flash/EE Program Memory (2) Parallel Programming The ADuC834 contains a 64 Kbyte array of Flash/EE program The parallel programming mode is fully compatible with conven- memory. The lower 62 Kbytes of this program memory is avail- tional third party Flash or EEPROM device programmers. A block able to the user, and can be used for program storage or indeed diagram of the external pin configuration required to support parallel as additional NV data memory. programming is shown in Figure 18. In this mode, Ports 0, and 2 The upper 2 Kbytes of this Flash/EE program memory array operate as the external address bus interface, P3 operates as the contain permanently embedded firmware, allowing in circuit serial external data bus interface and P1.0 operates as the Write Enable download, serial debug and nonintrusive single pin emulation. strobe. Port 1.1, P1.2, P1.3, and P1.4 are used as a general These 2 Kbytes of embedded firmware also contain a power-on configuration port that configures the device for various program configuration routine that downloads factory calibrated coeffi- and erase operations during parallel programming. cients to the various calibrated peripherals (ADC, temperature sensor, current sources, bandgap references and so on). Table XIII. Flash/EE Memory Parallel Programming Modes This 2 Kbyte embedded firmware is hidden from user code. Port 1 Pins Attempts to read this space will read 0s, i.e., the embedded firmware P1.4 P1.3 P1.2 P1.1 Programming Mode appears as NOP instructions to user code. 0000Erase Flash/EE Program, In normal operating mode (power up default) the 62 Kbytes of Data, and Security Modes user Flash/EE program memory appear as a single block. This1001Read Device Signature/ID block is used to store the user code as shown in Figure 17. 1010Program Code Byte0010Program Data Byte EMBEDDED DOWNLOAD/DEBUG KERNEL1011Read Code Byte PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE FFFFH TO BE DOWNLOADED TO ANY OF THE 62 KBYTES OF 2 KBYTE0011Read Data Byte ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM F800H1100Program Security Modes APPEARS AS ‘NOP’ INSTRUCTIONS TO USER CODE. F7FFH1101Read/Verify Security Modes All other codes Redundant USER PROGRAM MEMORY 62 KBYTES OF FLASH/EE PROGRAM MEMORY IS AVAILABLE TO THE USER. ALL OF THIS SPACE CAN 62 KBYTE 5V BE PROGRAMMED FROM THE PERMANENTLY ADuC834 EMBEDDED DOWNLOAD/DEBUG KERNEL OR IN VDD PROGRAM PARALLEL PROGRAMMING MODE. P3 DATAGND (D0–D7) PROGRAM MODE (SEE TABLE XIII) P1.1 -> P1.4 P0 PROGRAM 0000H ADDRESS (A0–A13)

COMMAND

P1.0 (P2.0 = A0)

Figure 17. Flash/EE Program Memory Map in ENABLE P2 (P1.7 = A13) Normal Mode

GND EA In Normal Mode, the 62 Kbytes of Flash/EE program memory ENTRY SEQUENCE GND PSEN P1.5 -> P1.7 TIMING can be programmed programmed in two ways, namely: VDD RESET (1) Serial Downloading (In-Circuit Programming) The ADuC834 facilitates code download via the standard UART Figure 18. Flash/EE Memory Parallel Programming serial port. The ADuC834 will enter Serial Download mode User Download Mode (ULOAD) after a reset or power cycle if the PSEN pin is pulled low through In Figure 17 we can see that it was possible to use the 62 Kbytes an external 1 kΩ resistor. Once in serial download mode, the of Flash/EE program memory available to the user as one single hidden embedded download kernel will execute. This allows the block of memory. In this mode all of the Flash/EE memory is user to download code to the full 62 Kbytes of Flash/EE program read only to user code. memory while the device is in circuit in its target application hardware. However, the Flash/EE program memory can also be written to during runtime simply by entering ULOAD mode. In ULOAD A PC serial download executable is provided as part of the mode, the lower 56 Kbytes of program memory can be erased ADuC834 QuickStart development system. Appliction Note and reprogrammed by user software as shown in Figure 19. uC004 fully describes the serial download protocol that is used ULOAD mode can be used to upgrade your code in the field via by the embedded download kernel. This Appliction Note is any user defined download protocol. Configuring the SPI port on available at www.analog.com/microconverter. the ADuC834 as a slave, it is possible to completely reprogram the 56 Kbytes of Flash/EE program memory in only 5 seconds. See Application Note uC007. –30– REV. A, Alternatively ULOAD Mode can be used to save data to the Flash/EE Program Memory Security 56 Kbytes of Flash/EE memory. This can be extremely useful in The ADuC834 facilitates three modes of Flash/EE program datalogging applications where the ADuC834 can provide up to memory security. These modes can be independently activated, 60 Kbytes of NV data memory on-chip (4 Kbytes of dedicated restricting access to the internal code space. These security Flash/EE data memory also exist). modes can be enabled as part of serial download protocol, as The upper 6 Kbytes of the 62 Kbytes of Flash/EE program described in Application Note uC004, or via parallel program- memory is only programmable via serial download or parallel ming. The ADuC834 offers the following security modes: programming. This means that this space appears as read only Lock Mode to user code. Therefore, it cannot be accidently erased or repro- This mode locks the code memory, disabling parallel program- grammed by erroneous code execution. This makes it very ming of the program memory. However, reading the memory in suitable to use the 6 Kbytes as a bootloader. A Bootload Enable Parallel Mode and reading the memory via a MOVC command option exists in the serial downloader to “Always RUN from from external memory are still allowed. This mode is deactivated E000h after Reset.” If using a bootloader, this option is recom- by initiating an “erase code and data” command in Serial Down- mended to ensure that the bootloader always executes correct load or Parallel Programming modes. code after reset. Secure Mode Programming the Flash/EE program memory via ULOAD This mode locks the code memory, disabling parallel program- mode is described in more detail in the description of ECON ming of the program memory. Reading/Verifying the memory in and also in Application Note uC007. Parallel Mode and reading the internal memory via a MOVC command from external memory is also disabled. This mode is EMBEDDED DOWNLOAD/DEBUG KERNEL deactivated by initiating an “erase code and data” command in PERMANENTLY EMBEDDED FIRMWARE ALLOWS CODE TO BE DOWNLOADED TO ANY OF THE 62 KBYTES OF FFFFH Serial Download or Parallel Programming Modes. ON-CHIP PROGRAM MEMORY. THE KERNEL PROGRAM 2 KBYTE APPEARS AS ‘NOP’ INSTRUCTIONS TO USER CODE. F800H Serial Safe Mode F7FFH This mode disables serial download capability on the device. IfUSER BOOTLOADER SPACE THE USER BOOTLOADER SPACE Serial Safe mode is activated and an attempt is made to reset CAN BE PROGRAMMED IN 6 KBYTE the part into Serial Download mode, i.e., RESET asserted and DOWNLOAD/DEBUG MODE VIA THE KERNEL BUT IS READ ONLY WHEN E000H deasserted with PSEN low, the part will interpret the serial 62 KBYTES EXECUTING USER CODE DFFFH download reset as a normal reset only. It will therefore not enter OF USER CODE USER DOWNLOAD SPACE Serial Download mode, but only execute a normal reset sequence. MEMORY EITHER THE DOWNLOAD/DEBUG KERNEL 56 KBYTE Serial Safe mode can only be disabled by initiating an “erase OR USER CODE (IN ULOAD MODE) CAN PROGRAM THIS SPACE. code and data” command in parallel programming mode. 0000H

Figure 19. Flash/EE Program Memory Map in ULOAD Mode REV. A –31–

, Using the Flash/EE Data Memory BYTE 13FFH BYTE 2 BYTE 3 BYTE 4(0FFCH) The 4 Kbytes of Flash/EE data memory is configured as 1024 pages, (0FFDH) (0FFEH) (0FFFH) BYTE 1 BYTE 2 BYTE 3 BYTE 4 each of 4 bytes. As with the other ADuC834 peripherals, the 3FEH (0FF8H) (0FF9H) (0FFAH) (0FFBH) interface to this memory space is via a group of registers mapped in the SFR space. A group of four data registers (EDATA1–4) is used to hold the 4 bytes of data at each page. The page is BYTE 1 BYTE 2 BYTE 3 addressed via the two registers EADRH and EADRL. Finally, BYTE 403H (000CH) (000DH) (000EH) (000FH) ECON is an 8-bit control register that may be written with one 02H BYTE 1 BYTE 2 BYTE 3 BYTE 4 (0009H) of nine Flash/EE memory access commands to trigger various (0008H) (000AH) (000BH) 01H BYTE 1 BYTE 2 BYTE 3 BYTE 4 read, write, erase, and verify functions. (0004H) (0005H) (0006H) (0007H) 00H A block diagram of the SFR interface to the Flash/EE data BYTE 1 BYTE 2 BYTE 3 BYTE 4(0000H) (0001H) (0002H) (0003H) memory array is shown in Figure 20. ECON—Flash/EE Memory Control SFR BYTE Programming of either the Flash/EE data memory or the Flash/EE ADDRESSESARE GIVEN IN program memory is done through the Flash/EE Memory Control BRACKETS SFR (ECON). This SFR allows the user to read, write, erase or verify the 4 Kbytes of Flash/EE data memory or the 56 Kbytes Figure 20. Flash/EE Data Memory Control and Configuration of Flash/EE program memory. Table XIV. ECON—Flash/EE Memory Commands Command Description Command Description ECON Value (Normal Mode) (Power-On Default) (ULOAD Mode) 01H Results in 4 bytes in the Flash/EE data memory, Not Implemented. Use the MOVC instruction. READ addressed by the page address EADRH/L, being read into EDATA 1 to 4. 02H Results in 4 bytes in EDATA1–4 being written to the Results in bytes 0–255 of internal XRAM being written WRITE Flash/EE data memory, at the page address given by to the 256 bytes of Flash/EE program memory at the page EADRH. (0 ≤ EADRH < 0400H) address given by EADRH/L (0 ≤ EADRH/L < E0H) Note: The 4 bytes in the page being addressed must Note: The 256 bytes in the page being addressed must be pre-erased. be pre-erased. 03H Reserved Command Reserved Command 04H Verifies if the data in EDATA1–4 is contained in the Not Implemented. Use the MOVC and MOVX instructions VERIFY page address given by EADRH/L. A subsequent read to verify the WRITE in software. of the ECON SFR will result ina0being read if the verification is valid, or a nonzero value being read to indicate an invalid verification. 05H Results in the erase of the 4 bytes page of Flash/EE data Results in the 64-bytes page of Flash/EE program memory, ERASE PAGE memory addressed by the page address EADRH/L addressed by the byte address EADRH/L being erased. EADRL can equal any of 64 locations within the page. A new page starts whenever EADRL is equal to 00H, 40H, 80H, or C0H 06H Results in the erase of entire 4 Kbytes of Flash/EE Results in the erase of the entire 56 Kbytes of ULOAD ERASE ALL data memory. Flash/EE program memory 81H Results in the byte in the Flash/EE data memory, Not Implemented. Use the MOVC command. READBYTE addressed by the byte address EADRH/L, being read into EDATA1. (0 ≤ EADRH/L ≤ 0FFFH). 82H Results in the byte in EDATA1 being written into Results in the byte in EDATA1 being written into WRITEBYTE Flash/EE data memory, at the byte address EADRH/L. Flash/EE program memory at the byte address EADRH/L (0 ≤ EADRH/L ≤ DFFFH) 0FH Leaves the ECON instructions to operate on the Enters normal mode directing subsequent ECON EXULOAD Flash/EE data memory. instructions to operate on the Flash/EE data memory F0H Enters ULOAD mode, directing subsequent ECON Leaves the ECON Instructions to operate on the Flash/EE ULOAD instructions to operate on the Flash/EE program memory. program memory. –32– REV. A PAGE ADDRESS (EADRH/L) EDATA1 SFR EDATA2 SFR EDATA3 SFR EDATA4 SFR, Programming the Flash/EE Data Memory Note: although the 4 Kbytes of Flash/EE data memory is shipped A user wishes to program F3H into the second byte on Page 03H from the factory pre-erased, i.e., Byte locations set to FFH, it is of the Flash/EE data memory space while preserving the other nonetheless good programming practice to include an erase-all three bytes already in this page. routine as part of any configuration/setup code running on the A typical program of the Flash/EE data array will involve: ADuC834. An “ERASE-ALL” command consists of writing “06H” to the ECON SFR, which initiates an erase of the 4-Kbyte 1. setting EADRH/L with the page address Flash/EE array. This command coded in 8051 assembly would 2. writing the data to be programmed to the EDATA1–4 appear as: 3. writing the ECON SFR with the appropriate command MOV ECON,#06H ; Erase all Command Step 1: Set Up the Page Address ; 2 ms Duration The two address registers EADRH and EADRL hold the high byte address and the low byte address of the page to be addressed. Flash/EE Memory Timing The assembly language to set up the address may appear as: Typical program and erase times for the ADuC834 are as follows: MOV EADRH,#0 ; Set Page Address Pointer Normal Mode (operating on Flash/EE data memory) MOV EADRL,#03H READPAGE (4 bytes) – 5 machine cycles Step 2: Set Up the EDATA Registers WRITEPAGE (4 bytes) – 380 s The four values to be written into the page into the 4 SFRs VERIFYPAGE (4 bytes) – 5 machine cycles EDATA1–4. Unfortunately we do not know three of them. Thus it ERASEPAGE (4 bytes) – 2 ms is necessary to read the current page and overwrite the second byte. ERASEALL (4 Kbytes) – 2 ms MOV ECON,#1 ; Read Page into EDATA1-4 READBYTE (1 byte) – 3 machine cycles MOV EDATA2,#0F3H ; Overwrite byte 2 WRITEBYTE (1 byte) – 200 s ULOAD Mode (operating on Flash/EE program memory) Step 3: Program Page WRITEPAGE (256 bytes) – 15 ms A byte in the Flash/EE array can only be programmed if it has ERASEPAGE (64 bytes) – 2 ms previously been erased. To be more specific, a byte can only be ERASEALL (56 Kbytes) – 2 ms programmed if it already holds the value FFH. Because of the WRITEBYTE (1 byte) – 200 s Flash/EE architecture, this erase must happen at a page level. Therefore, a minimum of 4 bytes (1 page) will be erased when It should be noted that a given mode of operation is initiated as an erase command is initiated. Once the page is erased, we can soon as the command word is written to the ECON SFR. The program the 4 bytes in-page and then perform a verification of core microcontroller operation on the ADuC834 is idled until the data. the requested Program/Read or Erase mode is completed. MOV ECON,#5 ; ERASE Page In practice, this means that even though the Flash/EE memory MOV ECON,#2 ; WRITE Page mode of operation is typically initiated with a two-machine cycle MOV ECON,#4 ; VERIFY Page MOV instruction (to write to the ECON SFR), the next instruction MOV A,ECON ; Check if ECON=0 (OK!) will not be executed until the Flash/EE operation is complete. JNZ ERROR This means that the core will not respond to interrupt requests until the Flash/EE operation is complete, although the core peripheral functions like Counter/Timers will continue to count and time as configured throughout this period. REV. A –33–, DAC programmed to appear at Pin 3 or Pin 12. It should be noted The ADuC834 incorporates a 12-bit, voltage output DAC that in 12-bit mode, the DAC voltage output will be updated as on-chip. It has a rail-to-rail voltage output buffer capable of driving soon as the DACL data SFR has been written; therefore, the 10 kΩ/100 pF. It has two selectable ranges, 0 V to VREF (the inter- DAC data registers should be updated as DACH first, followed nal bandgap 2.5 V reference) and0Vto AVDD. It can operate in by DACL. The 12-bit DAC data should be written into DACH/L 12-bit or 8-bit mode. The DAC has a control register, DACCON, right-justified such that DACL contains the lower eight bits, and two data registers, DACH/L. The DAC output can be and the lower nibble of DACH contains the upper four bits. Table XV. DACCON SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 ––– Reserved for Future Use 5 ––– Reserved for Future Use 4 DACPIN DAC Output Pin Select. Set by the user to direct the DAC output to Pin 12 (P1.7/AIN4/DAC). Cleared by user to direct the DAC output to Pin 3 (P1.2/DAC/IEXC1). 3 DAC8 DAC 8-bit Mode Bit. Set by user to enable 8-bit DAC operation. In this mode, the 8-bits in DACL SFR are routed to the 8 MSBs of the DAC, and the 4 LSBs of the DAC are set to zero. Cleared by user to operate the DAC in its normal 12-bit mode of operation. 2 DACRN DAC Output Range Bit. Set by user to configure DAC range of 0–AVDD. Cleared by user to configure DAC range of 0 V–2.5 V (VREF). 1 DACCLR DAC Clear Bit. Set to 1 by user to enable normal DAC operation. Cleared to 0 by user to reset DAC data registers DACL/H to zero. 0 DACEN DAC Enable Bit. Set to 1 by user to enable normal DAC operation. Cleared to 0 by user to power down the DAC. DACH/L DAC Data Registers Function DAC Data Registers, written by user to update the DAC output. SFR Address DACL (DAC Data Low Byte) FBH DACH (DAC Data High Byte) FCH Power-On Default Value 00H Both Registers Bit Addressable No Both Registers Using the D/A Converter Features of this architecture include inherent guaranteed mono- The on-chip D/A converter architecture consists of a resistor tonicity and excellent differential linearity. As illustrated in string DAC followed by an output buffer amplifier, the func- Figure 21, the reference source for the DAC is user selectable in tional equivalent of which is illustrated in Figure 21. software. It can be either AVDD or VREF. In 0-to-AVDD mode, the DAC output transfer function spans from0Vto the voltage AV at the AVDD pin. In 0-to-VREF mode, the DAC output transferDD ADuC834 function spans from0Vto the internal VREF (2.5 V). The DAC VREF R output buffer amplifier features a true rail-to-rail output stage OUTPUT implementation. This means that, unloaded, each output is

BUFFER

R capable of swinging to within less than 100 mV of both AVDD 12 DAC and ground. Moreover, the DAC’s linearity specification (when R driving a 10 kΩ resistive load to ground) is guaranteed through the full transfer function except codes 0 to 48 in 0-to-VREF HIGH-Z DISABLE mode and 0 to 100 and 3950 to 4095 in 0-to-VDD mode. (FROM MCU) Linearity degradation near ground and VDD is caused by saturationR of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in Figure 22. The R dotted line in Figure 22 indicates the ideal transfer function, and the solid line represents what the transfer function might look like with endpoint nonlinearities due to saturation of the output amplifier. Figure 21. Resistor String DAC Functional Equivalent –34– REV. A, Note that Figure 22 represents a transfer function in 0-to-VDD 4 mode only. In 0-to-VREF mode (with VREF < VDD), the lower nonlinearity would be similar, but the upper portion of the DAC LOADED WITH 0FFF HEX transfer function would follow the “ideal” line right to the end, showing no signs of endpoint linearity errors. 3

VDD

VDD–50mV VDD–100mV 1 DAC LOADED WITH 0000 HEX0510 15 SOURCE/SINK CURRENT – mA Figure 24. Source and Sink Current Capability 100mV with VREF = VDD = 3 V 50mV For larger loads, the current drive capability may not be 0mV 000 Hex FFF Hex sufficient. In order to increase the source and sink current capability of the DAC, an external buffer should be added, as Figure 22. Endpoint Nonlinearities Due to Amplifier shown in Figure 25. Saturation The endpoint nonlinearities conceptually illustrated in Figure 22 get worse as a function of output loading. Most of the ADuC834 ADuC834 data sheet specifications assume a 10 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of Figure 22 become larger. With larger current demands, this can significantly limit output voltage swing. Figures 23 and 24 illustrate this behavior. It should be noted that the upper trace in each of these figures is only valid for an Figure 25. Buffering the DAC Output output range selection of 0-to-AVDD. In 0-to-VREF mode, DAC The DAC output buffer also features a high impedance disable loading will not cause high-side voltage drops as long as the function. In the chip’s default power-on state, the DAC is reference voltage remains below the upper trace in the corre- disabled and its output is in a high impedance state (or “three- sponding figure. For example, if AVDD = 3 V and VREF = 2.5 V, state”) where they remain inactive until enabled in software. the high-side voltage will not be affected by loads less than 5 mA. But somewhere around 7 mA, the upper curve in Figure 24 This means that if a zero output is desired during power-up or drops below 2.5 V (V power-down transient conditions, a pull-down resistor must beREF) indicating that at these higher currents, the output will not be capable of reaching V . added to each DAC output. Assuming this resistor is in place,REF the DAC output will remain at ground potential whenever the 5 DAC is disabled. DAC LOADED WITH 0FFF HEX DAC LOADED WITH 0000 HEX0510 15 SOURCE/SINK CURRENT – mA Figure 23. Source and Sink Current Capability with VREF = AVDD = 5 V REV. A –35– OUTPUT VOLTAGE – V OUTPUT VOLTAGE – V, PULSEWIDTH MODULATOR (PWM) The PWM uses five SFRs: the control SFR, PWMCON, and four The PWM on the ADuC834 is a highly flexible PWM offering data SFRs PWM0H, PWM0L, PWM1H, and PWM1L. programmable resolution and input clock, and can be config- PWMCON (as described below) controls the different modes of ured for any one of six different modes of operation. Two of operation of the PWM as well as the PWM clock frequency. these modes allow the PWM to be configured as a - DAC PWM0H/L and PWM1H/L are the data registers that determine with up to 16 bits of resolution. A block diagram of the PWM is the duty cycles of the PWM outputs at P1.0 and P1.1. shown in Figure 26. To use the PWM user software, first write to PWMCON to 12.583MHz select the PWM mode of operation and the PWM input clock. PWMCLK CLOCK PROGRAMMABLE Writing to PWMCON also resets the PWM counter. In any of 32.768kHz SELECT DIVIDER the 16-bit modes of operation (Modes 1, 3, 4, 6), user software 32.768kHz/15 should write to the PWM0L or PWM1L SFRs first. This value is written to a hidden SFR. Writing to the PWM0H or PWM1H 16-BIT PWM COUNTER SFRs updates both the PWMxH and the PWMxL SFRs but does not change the outputs until the end of the PWM cycle in progress. The values written to these 16-bit registers are then used in the next PWM cycle. P1.0

COMPARE

P1.1 PWMCON PWM Control SFR SFR Address AEH MODE PWM0H/L PWM1H/L Power-On Default Value 00H Bit Addressable No Figure 26. PWM Block Diagram Table XVI. PWMCON SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 MD2 PWM Mode Bits 5 MD1 The MD2/1/0 bits choose the PWM mode as follows: 4 MD0 MD2 MD1 MD0 Mode000Mode 0: PWM Disabled001Mode 1: Single Variable Resolution PWM010Mode 2: Twin 8-bit PWM011Mode 3: Twin 16-bit PWM100Mode 4: Dual NRZ 16-bit - DAC101Mode 5: Dual 8-bit PWM110Mode 6: Dual RZ 16-bit - DAC111Reserved for Future Use 3 CDIV1 PWM Clock Divider 2 CDIV0 Scale the clock source for the PWM counter as follows: CDIV1 CDIV0 Description00PWM Counter = Selected Clock /101PWM Counter = Selected Clock /410PWM Counter = Selected Clock /1611PWM Counter = Selected Clock /64 1 CSEL1 PWM Clock Divider 0 CSEL0 Select the clock source for the PWM as follows: CSEL1 CSEL0 Description00PWM Clock = fXTAL/1501PWM Clock = fXTAL10PWM Clock = External Input at P3.4/T0/PWMCLK11PWM Clock = fVCO (12.58 MHz) –36– REV. A, PWM MODES OF OPERATION PWM1L Mode 0: PWM Disabled PWM COUNTER The PWM is disabled, allowing P1.0 and P1.1 be used as normal. PWM0H Mode 1: Single-Variable Resolution PWM PWM0L In Mode 1, both the pulse length and the cycle time (period) are PWM1H programmable in user code, allowing the resolution of the PWM to be variable. P1.0 PWM1H/L sets the period of the output waveform. Reducing PWM1H/L reduces the resolution of the PWM output but P1.1 increases the maximum output rate of the PWM (e.g., setting PWM1H/L to 65536 gives a 16-bit PWM with a maximum Figure 28. PWM Mode 2 output rate of 192 Hz (12.583 MHz/65536). Setting PWM1H/L to 4096 gives a 12-bit PWM with a maximum output rate of Mode 3: Twin 16-Bit PWM 3072 Hz (12.583 MHz/4096)). In Mode 3, the PWM counter is fixed to count from 0 to 65536 PWM0H/L sets the duty cycle of the PWM output waveform, giving a fixed 16-bit PWM. Operating from the 12.58 MHz core as shown in Figure 27. clock results in a PWM output rate of 192 Hz. The duty cycle of the PWM outputs at P1.0 and P1.1 are independently PWM1H/L programmable. PWM COUNTER As shown below, while the PWM counter is less than PWM0H/L, PWM0H/L the output of PWM0 (P1.0) is high. Once the PWM counter equals PWM0H/L, then PWM0 (P1.0) goes low and remains low until the PWM counter rolls over. 0 Similarly, while the PWM counter is less than PWM1H/L, the output of PWM1 (P1.1) is high. Once the PWM counter equals P1.0 PWM1H/L, then PWM1 (P1.1) goes low and remains low until the PWM counter rolls over. Figure 27. PWM in Mode 1 In this mode, both PWM outputs are synchronized (i.e., once the Mode 2: Twin 8-Bit PWM PWM counter rolls over to 0, both PWM0 (P1.0) and PWM1 In Mode 2, the duty cycle of the PWM outputs and the resolution (P1.1) will go high). of the PWM outputs are both programmable. The maximum resolution of the PWM output is eight bits. 65536 PWM COUNTER PWM1L sets the period for both PWM outputs. Typically this will be set to 255 (FFh) to give an 8-bit PWM, although it is PWM1H/L possible to reduce this as necessary. A value of 100 could be loaded here to give a percentage PWM (i.e., the PWM is accu- PWM0H/L rate to 1%). The outputs of the PWM at P1.0 and P1.1 are shown in the diagram below. As can be seen, the output of PWM0 (P1.0) goes P1.0 low when the PWM counter equals PWM0L. The output of PWM1 (P1.1) goes high when the PWM counter equals PWM1H P1.1 and goes low again when the PWM counter equals PWM0H. Setting PWM1H to 0 ensures that both PWM outputs start Figure 29. PWM Mode 3 simultaneously. REV. A –37–, Mode 4: Dual NRZ 16-Bit - DAC PWM1L Mode 4 provides a high speed PWM output similar to that of a PWM COUNTERS Σ-∆ DAC. Typically, this mode will be used with the PWM PWM1H clock equal to 12.58 MHz. PWM0L In this mode, P1.0 and P1.1 are updated every PWM clock PWM0H (80 ns in the case of 12.58 MHz). Over any 65536 cycles (16-bit PWM) PWM0 (P1.0) is high for PWM0H/L cycles and low for (65536 – PWM0H/L) cycles. Similarly PWM1 (P1.1) is high for P1.0 PWM1H/L cycles and low for (65536 – PWM1H/L) cycles. P1.1 If PWM1H is set to 4010H (slightly above one quarter of FS), then typically P1.1 will be low for three clocks and high for one clock (each clock is approximately 80 ns). Over every 65536 Figure 31. PWM Mode 5 clocks, the PWM will compromise for the fact that the output Mode 6: Dual RZ 16-Bit - DAC should be slightly above one quarter of full scale by having a Mode 6 provides a high speed PWM output similar to that of a high cycle followed by only two low cycles. Σ-∆ DAC. Mode 6 operates very similarly to Mode 4. However, the key difference is that Mode 6 provides return to zero (RZ) PWM0H/L = C000H Σ-∆ DAC output. Mode 4 provides non-return-to-zero Σ-∆ DAC CARRY OUT AT P1.0 outputs. The RZ mode ensures that any difference in the rise0 0 16-BIT11111and fall times will not affect the Σ-∆ DAC INL. However, the RZ mode halves the dynamic range of the Σ-∆ DAC outputs from 0→AVDD to 0→AVDD/2. For best results, this mode should be 80s used with a PWM clock divider of 4. 16-BIT 16-BIT If PWM1H is set to 4010H (slightly above one quarter of FS) then typically P1.1 will be low for three full clocks (3 80 ns), 12.583MHz LATCH high for half a clock (40 ns) and then low again for half a clock (40 ns) before repeating itself. Over every 65536 clocks, the 16-BIT 16-BIT PWM will compromise for the fact that the output should be slightly above one quarter of full scale by leaving the output0001000high for two half clocks in four every so often. CARRY OUT AT P1.1 For faster DAC outputs (at lower resolution), write 0s to the 16-BIT LSBs that are not required witha1in the LSB position. If, for 80s example, only 12-bit performance is required, write “0001” to PWM1H/L = 4000H the 4 LSBs. This means that a 12-bit accurate Σ-∆ DAC output can occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs

Figure 30. PWM Mode 4 gives an 8-bit accurate Σ-∆ DAC output at 49 kHz.

For faster DAC outputs (at lower resolution), write 0s to the LSBs that are not required witha1in the LSB position. If, for PWM0H/L = C000H example, only 12-bit performance is required, write “0001” to CARRY OUT AT P1.0 the 4 LSBs. This means that a 12-bit accurate Σ-∆ DAC output 16-BIT0111011can occur at 3 kHz. Similarly, writing 00000001 to the 8 LSBs gives an 8-bit accurate Σ-∆ DAC output at 49 kHz. Mode 5: Dual 8-Bit PWM 318s 16-BIT 16-BIT In Mode 5, the duty cycle of the PWM outputs and the resolu- tion of the PWM outputs are individually programmable. The maximum resolution of the PWM output is eight bits. 3.146MHz LATCH The output resolution is set by the PWM1L and PWM1H SFRs for the P1.0 and P1.1 outputs respectively. PWM0L and 16-BIT 16-BIT PWM0H sets the duty cycles of the PWM outputs at P1.0 and P1.1, respectively. Both PWMs have the same clock source and0001000CARRY OUT AT P1.1 clock divider. 16-BIT 318s PWM1H/L = 4000H

Figure 32. PWM Mode 6

–38– REV. A, ON-CHIP PLL required. The default core clock is the PLL clock divided by 8 The ADuC834 is intended for use with a 32.768 kHz watch or 1.572864 MHz. The ADC clocks are also derived from the crystal. A PLL locks onto a multiple (384) of this to provide a PLL clock, with the modulator rate being the same as the crys- stable 12.582912 MHz clock for the system. The core can oper- tal oscillator frequency. The above choice of frequencies ensures ate at this frequency, or at binary submultiples of it, to allow that the modulators and the core will be synchronous, regardless power saving in cases where maximum core performance is not of the core clock rate. The PLL control register is PLLCON. PLLCON PLL Control Register SFR Address D7H Power-On Default Value 03H Bit Addressable No Table XVII. PLLCON SFR Bit Designations Bit Name Description 7 OSC_PD Oscillator Power-Down Bit. Set by user to halt the 32 kHz oscillator in power-down mode. Cleared by user to enable the 32 kHz oscillator in power-down mode. This feature allows the TIC to continue counting even in power-down mode. 6 LOCK PLL Lock Bit. This is a read-only bit. Set automatically at power-on to indicate the PLL loop is correctly tracking the crystal clock. After power down, this bit can be polled to wait for the PLL to lock. Cleared automatically at power-on to indicate the PLL is not correctly tracking the crystal clock. This may be due to the absence of a crystal clock or an external crystal at power-on. In this mode, the PLL output can be 12.58 MHz ± 20%. After the ADuC834 wakes up from power-down, user code may poll this bit, to wait for the PLL to lock. If LOCK = 0, then the PLL is not locked. 5 ––– Reserved for Future Use; Should Be Written with ‘0’ 4 LTEA Reading this bit returns the state of the external EA pin latched at reset or power-on. 3 FINT Fast Interrupt Response Bit. Set by user enabling the response to any interrupt to be executed at the fastest core clock frequency, regardless of the configuration of the CD2–0 bits (see below). After user code has returned from an interrupt, the core resumes code execution at the core clock selected by the CD2–0 bits. Cleared by user to disable the fast interrupt response feature. 2 CD2 CPU (Core Clock) Divider Bits. 1 CD1 This number determines the frequency at which the microcontroller core will operate. 0 CD0 CD2 CD1 CD0 Core Clock Frequency (MHz) 00012.5829120016.2914560103.1457280111.572864 (Default Core Clock Frequency) 1000.7864321010.3932161100.1966081110.098304 REV. A –39–, TIME INTERVAL COUNTER (WAKE-UP/RTC TIMER) sheet.) If the ADuC834 is in power-down mode, again with TIC A time interval counter (TIC) is provided on-chip for: interrupt enabled, the TII bit will wake up the device and resume • periodically waking the part up from power-down code execution by vectoring directly to the TIC interrupt service • implementing a Real-Time Clock vector address at 0053H. The TIC-related SFRs are described • counting longer intervals than the standard 8051 compatible below with a block diagram of the TIC shown in Figure 33. timers are capable of TCEN 32.768kHz EXTERNAL CRYSTAL The TIC is capable of timeout intervals ranging from 1/128th second to 255 hours. Furthermore, this counter is clocked by the ITS0, 1 crystal oscillator rather than the PLL and thus has the ability to remain active in power-down mode and time long power-down 8-BIT

PRESCALER

intervals. This has obvious applications for remote battery-powered sensors where regular widely spaced readings are required. The TIC counter can easily be used to generate a real-time HUNDREDTHS COUNTERHTHSEC clock. The hardware will count in seconds, minutes, and hours; INTERVAL TIEN however, user software will have to count in days, months, and TIMEBASE SECOND COUNTER SELECTION years. The current time can be written to the timebase SFRs SEC MUX (HTHSEC, SEC, MIN, and HOUR) while TCEN is low. When the RTC timer is enabled (TCEN is set), the TCEN bit itself MINUTE COUNTER and the HTHSEC, SEC, MIN, and HOUR Registers are not MIN reset to 00H after a hardware or watchdog timer reset. This is to prevent the need to recalibrate the real-time clock after a reset. HOUR COUNTER However, these registers will be reset to 00H after a power cycle HOUR 8-BIT (independent of TCEN) or after any reset if TCEN is clear. INTERVAL COUNTER Six SFRs are associated with the time interval counter, TIMECON being its control register. Depending on the configuration of the INTERVAL TIMEOUTTIME INTERVAL COUNTER INTERRUPT EQUAL? IT0 and IT1 bits in TIMECON, the selected time counter register overflow will clock the interval counter. When this counter is equal to the time interval value loaded in the INTVAL SFR, the INTVAL SFR TII bit (TIMECON.2) is set and generates an interrupt if enabled. (See IEIP2 SFR description under Interrupt System in this data Figure 33. TIC, Simplified Block Diagram Table XVIII. TIMECON SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 ––– Reserved for Future Use. For future product code compatibility, this bit should be written as a ‘1.’ 5 ITS1 Interval Timebase Selection Bits 4 ITS0 Written by user to determine the interval counter update rate. ITS1 ITS0 Interval Timebase001/128 Second01Seconds10Minutes11Hours 3 STI Single Time Interval Bit. Set by user to generate a single interval timeout. If set, a timeout will clear the TIEN bit. Cleared by user to allow the interval counter to be automatically reloaded and start counting again at each interval timeout. 2 TII TIC Interrupt Bit. Set when the 8-bit Interval Counter matches the value in the INTVAL SFR. Cleared by user software. 1 TIEN Time Interval Enable Bit. Set by user to enable the 8-bit time interval counter. Cleared by user to disable and clear the contents of the 8-bit interval counter. To ensure that the 8-bit interval counter is cleared TIEN must be held low for at least 30.5 s (32 kHz). 0 TCEN Time Clock Enable Bit. Set by user to enable the time clock to the time interval counters. Cleared by user to disable the 32 kHz clock to the TIC and clear the 8-bit prescaler and the HTHSEC, SEC, MIN and HOURS SFRs. To ensure that these registers are cleared, TCEN must be held low for at least 30.5 s (32 kHz). The time registers (HTHSEC, SEC, MIN, and HOUR) can only be written while TCEN is low. –40– REV. A, INTVAL User Time Interval Select Register Function User code writes the required time interval to this register. When the 8-bit interval counter is equal to the time interval value loaded in the INTVAL SFR, the TII bit (TIMECON.2) is set and generates generates an interrupt if enabled. (See IEIP2 SFR description under Interrupt System in this data sheet.) SFR Address A6H Power-On Default Value 00H Reset Default Value 00H Bit Addressable No Valid Value 0 to 255 decimal HTHSEC Hundredths Seconds Time Register Function This register is incremented in (1/128) second intervals once TCEN in TIMECON is active. The HTHSEC SFR counts from 0 to 127 before rolling over to increment the SEC time register. SFR Address A2H Power-On Default Value 00H Reset Default Value 00H if TCEN = 0, Previous Value before reset if TCEN = 1 Bit Addressable No Valid Value 0 to 127 decimal SEC Seconds Time Register Function This register is incremented in 1-second intervals once TCEN in TIMECON is active. The SEC SFR counts from 0 to 59 before rolling over to increment the MIN time register. SFR Address A3H Power-On Default Value 00H Reset Default Value 00H if TCEN = 0, Previous Value before reset if TCEN = 1 Bit Addressable No Valid Value 0 to 59 decimal MIN Minutes Time Register Function This register is incremented in 1-minute intervals once TCEN in TIMECON is active. The MIN counts from 0 to 59 before rolling over to increment the HOUR time register. SFR Address A4H Power-On Default Value 00H Reset Default Value 00H if TCEN = 0, Previous Value before reset if TCEN = 1 Bit Addressable No Valid Value 0 to 59 decimal HOUR Hours Time Register Function This register is incremented in 1-hour intervals once TCEN in TIMECON is active. The HOUR SFR counts from 0 to 23 before rolling over to 0. SFR Address A5H Power-On Default Value 00H Reset Default Value 00H if TCEN = 0, Previous Value before reset if TCEN = 1 Bit Addressable No Valid Value 0 to 23 decimal REV. A –41–, WATCHDOG TIMER amount of time (see PRE3–0 bits in WDCON). The watchdog The purpose of the watchdog timer is to generate a device reset or timer itself is a 16-bit counter that is clocked at 32.768 kHz. The interrupt within a reasonable amount of time if the ADuC834 watchdog timeout interval can be adjusted via the PRE3–0 bits enters an erroneous state, possibly due to a programming error, in WDCON. Full control and status of the watchdog timer electrical noise, or RFI. The watchdog function can be disabled function can be controlled via the Watchdog Timer Control SFR by clearing the WDE (Watchdog Enable) bit in the Watchdog (WDCON). The WDCON SFR can only be written by user Control (WDCON) SFR. When enabled; the watchdog circuit software if the double write sequence described in WDWR will generate a system reset or interrupt (WDS) if the user program below is initiated on every write access to the WDCON SFR. fails to set the Watchdog (WDE) bit within a predetermined WDCON Watchdog Timer Control Register SFR Address C0H Power-On Default Value 10H Bit Addressable Yes Table XIX. WDCON SFR Bit Designations Bit Name Description 7 PRE3 Watchdog Timer Prescale Bits. 6 PRE2 The Watchdog timeout period is given by the equation: t = (2PRE (29WD /fPLL)) 5 PRE1 (0 ≤ PRE ≤ 7; fPLL = 32.768 kHz) 4 PRE0 PRE3 PRE2 PRE1 PRE0 Timeout Period (ms) Action000015.6 Reset or Interrupt000131.2 Reset or Interrupt001062.5 Reset or Interrupt0011125 Reset or Interrupt0100250 Reset or Interrupt0101500 Reset or Interrupt01101000 Reset or Interrupt01112000 Reset or Interrupt10000.0 Immediate Reset PRE3–0 > 1001 Reserved 3 WDIR Watchdog Interrupt Response Enable Bit. If this bit is set by the user, the watchdog will generate an interrupt response instead of a system reset when the watchdog timeout period has expired. This interrupt is not disabled by the CLR EA instruction and it is also a fixed, high-priority interrupt. If the watchdog is not being used to monitor the system, it can alternatively be used as a timer. The prescaler is used to set the timeout period in which an interrupt will be generated. (See also Note 1, Table XXXIX in the Interrupt System section.) 2 WDS Watchdog Status Bit. Set by the Watchdog Controller to indicate that a watchdog timeout has occurred. Cleared by writinga0or by an external hardware reset. It is not cleared by a watchdog reset. 1 WDE Watchdog Enable Bit. Set by user to enable the watchdog and clear its counters. Ifa1is not written to this bit within the watchdog timeout period, the watchdog will generate a reset or interrupt, depending on WDIR. Cleared under the following conditions, User writes 0, Watchdog Reset (WDIR = 0); Hardware Reset; PSM Interrupt. 0 WDWR Watchdog Write Enable Bit. To write data into the WDCON SFR involves a double instruction sequence. The WDWR bit must be set and the very next instruction must be a write instruction to the WDCON SFR. For example: CLR EA ; disable interrupts while writing ; to WDT SETB WDWR ; allow write to WDCON MOV WDCON, #72h ; enable WDT for 2.0s timeout SETB EA ; enable interrupts again (if rqd) –42– REV. A, POWER SUPPLY MONITOR the monitor will interrupt the core using the PSMI bit in the As its name suggests, the Power Supply Monitor, once enabled, PSMCON SFR. This bit will not be cleared until the failing power monitors both supplies (AVDD or DVDD) on the ADuC834. It will supply has returned above the trip point for at least 250 ms. This indicate when any of the supply pins drop below one of four monitor function allows the user to save working registers to avoid user-selectable voltage trip points from 2.63 V to 4.63 V. For possible data loss due to the low supply condition, and also correct operation of the Power Supply Monitor function, AVDD ensures that normal code execution will not resume until a safe must be equal to or greater than 2.7 V. Monitor function is supply level has been well established. The supply monitor is also controlled via the PSMCON SFR. If enabled via the IEIP2 SFR, protected against spurious glitches triggering the interrupt circuit. PSMCON Power Supply Monitor Control Register SFR Address DFH Power-On Default Value DEH Bit Addressable No Table XX. PSMCON SFR Bit Designations Bit Name Description 7 CMPD DVDD Comparator Bit. This is a read-only bit and directly reflects the state of the DVDD comparator. Read 1 indicates the DVDD supply is above its selected trip point. Read 0 indicates the DVDD supply is below its selected trip point. 6 CMPA AVDD Comparator Bit. This is a read-only bit and directly reflects the state of the AVDD comparator. Read 1 indicates the AVDD supply is above its selected trip point. Read 0 indicates the AVDD supply is below its selected trip point. 5 PSMI Power Supply Monitor Interrupt Bit. This bit will be set high by the MicroConverter if either CMPA or CMPD are low, indicating low analog or digital supply. The PSMI bit can be used to interrupt the processor. Once CMPD and/or CMPA return (and remain) high, a 250 ms counter is started. When this counter timesout, the PSMI interrupt is cleared. PSMI can also be written by the user. However, if either comparator output is low, it is not possible for the user to clear PSMI. 4 TPD1 DVDD Trip Point Selection Bits. 3 TPD0 These bits select the DVDD trip point voltage as follows: TPD1 TPD0 Selected DVDD Trip Point (V) 0 0 4.63013.08102.93112.63 2 TPA1 AVDD Trip Point Selection Bits. 1 TPA0 These bits select the AVDD trip point voltage as follows: TPA1TPA0 Selected AVDD Trip Point (V) 0 0 4.63013.08102.93112.63 0 PSMEN Power Supply Monitor Enable Bit. Set to 1 by the user to enable the Power Supply Monitor Circuit. Cleared to 0 by the user to disable the Power Supply Monitor Circuit. REV. A –43–, SERIAL PERIPHERAL INTERFACE MISO (Master In, Slave Out Data I/O Pin), Pin 14 The ADuC834 integrates a complete hardware Serial Peripheral The MISO (master in slave out) pin is configured as an input Interface (SPI) interface on-chip. SPI is an industry-standard line in Master mode and an output line in Slave mode. The synchronous serial interface that allows eight bits of data to be MISO line on the master (data in) should be connected to the synchronously transmitted and received simultaneously, i.e., full MISO line in the slave device (data out). The data is transferred duplex. It should be noted that the SPI pins SCLOCK and MOSI as byte-wide (8-bit) serial data, MSB first. are multiplexed with the I2C pins SCLOCK and SDATA. The MOSI (Master Out, Slave In Pin), Pin 27 pins are controlled via the I2CCON SFR only if SPE is clear. The MOSI (master out slave in) pin is configured as an output SPI can be configured for master or slave operation and typically line in Master mode and an input line in Slave mode. The MOSI consists of four pins, namely: line on the master (data out) should be connected to the MOSI line SCLOCK (Serial Clock I/O Pin), Pin 26 in the slave device (data in). The data is transferred as byte-wide The master clock (SCLOCK) is used to synchronize the data (8-bit) serial data, MSB first. being transmitted and received through the MOSI and MISO SS (Slave Select Input Pin), Pin 13 data lines. A single data bit is transmitted and received in each The Slave Select (SS) input pin is only used when the ADuC834 SCLOCK period. Therefore, a byte is transmitted/received after is configured in SPI Slave mode. This line is active low. Data is only eight SCLOCK periods. The SCLOCK pin is configured as an received or transmitted in Slave mode when the SS pin is low, output in master mode and as an input in Slave mode. In master allowing the ADuC834 to be used in single master, multislave SPI mode the bit-rate, polarity, and phase of the clock are controlled configurations. If CPHA = 1, the SS input may be permanently by the CPOL, CPHA, SPR0, and SPR1 bits in the SPICON SFR pulled low. With CPHA = 0, the SS input must be driven low (see Table XXI). In Slave mode the SPICON register will have to before the first bit in a byte wide transmission or reception and be configured with the phase and polarity (CPHA and CPOL) as return high again after the last bit in that byte wide transmission the master as for both Master and Slave mode the data is transmitted or reception. In SPI Slave mode, the logic level on the external on one edge of the SCLOCK signal and sampled on the other. SS pin (Pin 13), can be read via the SPR0 bit in the SPICON SFR. The following SFR registers are used to control the SPI interface. Table XXI. SPICON SFR Bit Designations Bit Name Description 7 ISPI SPI Interrupt Bit. Set by MicroConverter at the end of each SPI transfer. Cleared directly by user code or indirectly by reading the SPIDAT SFR 6 WCOL Write Collision Error Bit. Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress. Cleared by user code. 5 SPE SPI Interface Enable Bit. Set by user to enable the SPI interface. Cleared by user to enable the I2C interface. 4 SPIM SPI Master/Slave Mode Select Bit. Set by user to enable Master mode operation (SCLOCK is an output). Cleared by user to enable Slave mode operation (SCLOCK is an input). 3 CPOL* Clock Polarity Select Bit. Set by user if SCLOCK idles high. Cleared by user if SCLOCK idles low. 2 CPHA* Clock Phase Select Bit. Set by user if leading SCLOCK edge is to transmit data. Cleared by user if trailing SCLOCK edge is to transmit data. 1 SPR1 SPI Bit-Rate Select Bits. 0 SPR0 These bits select the SCLOCK rate (bit-rate) in Master mode as follows: SPR1 SPR0 Selected Bit Rate00fCORE/201fCORE/410fCORE/811fCORE/16 In SPI Slave mode, i.e., SPIM = 0, the logic level on the external SS pin (Pin 13), can be read via the SPR0 bit. *The CPOL and CPHA bits should both contain the same values for master and slave devices. –44– REV. A, SPIDAT SPI Data Register Function The SPIDAT SFR is written by the user to transmit data over the SPI interface or read by user code to read data just received by the SPI interface. SFR Address F7H Power-On Default Value 00H Bit Addressable No Using the SPI Interface SPI Interface—Master Mode Depending on the configuration of the bits in the SPICON SFR In Master Mode, the SCLOCK pin is always an output and shown in Table XXI, the ADuC834 SPI interface will transmit generates a burst of eight clocks whenever user code writes to or receive data in a number of possible modes. Figure 34 shows the SPIDAT Register. The SCLOCK bit rate is determined by all possible ADuC834 SPI configurations and the timing rela- SPR0 and SPR1 in SPICON. It should also be noted that the tionships and synchronization between the signals involved. SS Pin is not used in Master mode. If the ADuC834 needs to Also shown in this figure is the SPI interrupt bit (ISPI) and how assert the SS Pin on an external slave device, a port digital output it is triggered at the end of each byte-wide communication. pin should be used. In Master Mode, a byte transmission or reception is initiated by

SCLOCK

(CPOL = 1) a write to SPIDAT. Eight clock periods are generated via the SCLOCK pin and the SPIDAT byte being transmitted via MOSI. With each SCLOCK period, a data bit is also sampled

SCLOCK

(CPOL = 0) via MISO. After eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting SS in the input shift register. The ISPI flag will be set automatically SAMPLE INPUT and an interrupt will occur if enabled. The value in the shift DATA OUTPUT ? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB register will be latched into SPIDAT. (CPHA = 1) SPI Interface—Slave Mode In Slave Mode, the SCLOCK is an input. The SS pin must also ISPI FLAG be driven low externally during the byte communication. Trans- SAMPLE INPUT mission is also initiated by a write to SPIDAT. In Slave Mode, DATA OUTPUT MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB a data bit is transmitted via MISO and a data bit is received via? (CPHA = 0) MOSI through each input SCLOCK period. After eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in the input shift register. The ISPI ISPI FLAG flag will be set automatically and an interrupt will occur if enabled. The value in the shift register will be latched into SPIDAT

Figure 34. SPI Timing, All Modes only when the transmission/reception of a byte has been com-

pleted. The end of transmission occurs after the eighth clock has been received, if CPHA = 1 or when SS returns high if CPHA = 0.

REV. A –45–

, I2C SERIAL INTERFACE MOSI and SCLOCK pins of the on-chip SPI interface. Therefore The ADuC834 supports a fully licensed* I2C serial interface. The the user can only enable one or the other interface at any given I2C interface is implemented as a full hardware slave and software time (see SPE in Table XXI). Application Note uC001 describes master. SDATA (Pin 27) is the data I/O pin and SCLOCK the operation of this interface as implemented and is available from (Pin 26) is the serial clock. These two pins are shared with the the MicroConverter website at www.analog.com/microconverter. Three SFRs are used to control the I2C interface. These are described below. I2CCON I2C Control Register SFR Address E8H Power-On Default Value 00H Bit Addressable Yes Table XXII. I2CCON SFR Bit Designations Bit Name Description 7 MDO I2C Software Master Data Output Bit (Master Mode Only). This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit will be outputted on the SDATA pin if the data output enable (MDE) bit is set. 6 MDE I2C Software Master Data Output Enable Bit (Master Mode Only). Set by the user to enable the SDATA pin as an output (Tx). Cleared by the user to enable SDATA pin as an input (Rx). 5 MCO I2C Software Master Clock Output Bit (Master Mode Only). This data bit is used to implement a master I2C transmitter interface in software. Data written to this bit will be outputted on the SCLOCK pin. 4 MDI I2C Software Master Data Input Bit (Master Mode Only). This data bit is used to implement a master I2C receiver interface in software. Data on the SDATA pin is latched into this bit on SCLOCK if the data output enable (MDE) bit is 0. 3 I2CM I2C Master/Slave Mode Bit. Set by the user to enable I2C software master mode. Cleared by user to enable I2C hardware slave mode. 2 I2CRS I2C Reset Bit (Slave Mode Only). Set by the user to reset the I2C interface. Cleared by user code for normal I2C operation. 1 I2CTX I2C Direction Transfer Bit (Slave Mode Only). Set by the MicroConverter if the interface is transmitting. Cleared by the MicroConverter if the interface is receiving. 0 I2CI I2C Interrupt Bit (Slave Mode Only). Set by the MicroConverter after a byte has been transmitted or received. Cleared automatically when the user code reads the I2CDAT SFR (see I2CDAT below). I2CADD I2C Address Register Function Holds the I2C peripheral address for the part. It may be overwritten by the user code. Application Note uC001 at www.analog.com/microconverter describes the format of the I2C standard 7-bit address in detail. SFR Address 9BH Power-On Default Value 55H Bit Addressable No I2CDAT I2C Data Register Function The I2CDAT SFR is written by the user to transmit data over the I2C interface or read by user code to read data just received by the I2C interface. Accessing I2CDAT automatically clears any pending I2C interrupt and the I2CI bit in the I2CCON SFR. User software should only access I2CDAT once per interrupt cycle. SFR Address 9AH Power-On Default Value 00H Bit Addressable No * Purchase of licensed I2C components of Analog Devices or one of its sublicensed associated companies conveys a license for the purchaser under the Philips I2C Patent Rights to use these components in an I2C system provided that the system conforms to the I2C Standard Specification as defined by Philips. –46– REV. A, The main features of the MicroConverter I2C interface are: Once enabled in I2C slave mode, the slave controller waits for a • Only two bus lines are required; a serial data line (SDATA) START condition. If the ADuC834 detects a valid start condition, and a serial clock line (SCLOCK). followed by a valid address, and by the R/W bit, the I2CI inter- 2 rupt bit will get automatically set by hardware.• AnICmaster can communicate with multiple slave devices. Because each slave device has a unique 7-bit address then TheICperipheral will only generate a core interrupt if the user single master/slave relationships can exist at all times even in has preconfigured the I 2C interrupt enable bit in the IEIP2 SFR a multislave environment (Figure 35). as well as the global interrupt bit EA in the IE SFR, i.e., • On-chip filtering rejects <50 ns spikes on the SDATA and ; Enabling I2C Interrupts for the ADuC834 the SCLOCK lines to preserve data integrity. MOV IEIP2,#01h ; enable I2C interrupt SETB EA DVDD On the ADuC834 an auto clear of the I2CI bit is implemented so this bit is cleared automatically on a read or write access to the I2CDAT SFR. I2C I2C MOV I2CDAT, A ; I2CI auto-cleared MOV MASTER SLAVE #1 A, I2CDAT ; I2CI auto-cleared If for any reason the user tries to clear the interrupt more than I2C once, i.e., access the data SFR more than once per interrupt, SLAVE #2 then the I2C controller will halt. The interface will then have to be reset using the I2CRS bit. Figure 35. Typical I2C System The user can choose to poll the I2CI bit or enable the interrupt. In the case of the interrupt, the PC counter will vector to 003BH Software Master Mode at the end of each complete byte. For the first byte when the The ADuC834 can be used as a I2C master device by configuring user gets to the I2CI ISR, the 7-bit address and the R/W bit will the I2C peripheral in master mode and writing software to output appear in the I2CDAT SFR. the data bit by bit, which is referred to as a software master. Master mode is enabled by setting the I2CM bit in the I2CCON register. The I2CTX bit contains the R/W bit sent from the master. If I2CTX is set then the master would like to receive a byte. Hence To transmit data on the SDATA line, MDE must be set to enable the slave will transmit data by writing to the I2CDAT register. the output driver on the SDATA pin. If MDE is set then the If I2CTX is cleared, the master would like to transmit a byte. SDATA pin will be pulled high or low depending on whether the Hence the slave will receive a serial byte. The software can MDO bit is set or cleared. MCO controls the SCLOCK pin and interrogate the state of I2CTX to determine whether it should is always configured as an output in Master mode. In Master write to or read from I2CDAT. mode, the SCLOCK pin will be pulled high or low depending on the whether MCO is set or cleared. Once the ADuC834 has received a valid address, hardware will hold SCLOCK low until the I2CI bit is cleared by the software. To receive data, MDE must be cleared to disable the output This allows the master to wait for the slave to be ready before driver on SDATA. Software must provide the clocks by toggling transmitting the clocks for the next byte. the MCO bit and read SDATA pin via the MDI bit. If MDE is cleared, MDI can be used to read the SDATA pin. The value of The I2CI interrupt bit will be set every time a complete data the SDATA pin is latched into MDI on a rising edge of SCLOCK. byte is received or transmitted provided it is followed by a valid MDI is set if the SDATA pin was high on the last rising edge of ACK. If the byte is followed by a NACK, an interrupt is NOT SCLOCK. MDI is clear if the SDATA pin was low on the last generated. The ADuC834 will continue to issue interrupts for rising edge of SCLOCK. each complete data byte transferred until a STOP condition is received or the interface is reset. Software must control MDO, MCO, and MDE appropriately to generate the START condition, slave address, acknowledge bits, When a STOP condition is received, the interface will reset to a data bytes, and STOP conditions appropriately. These functions state where it is waiting to be addressed (idle). Similarly, if the are provided in Application Note uC001. interface receives a NACK at the end of a sequence, it also returns to the default idle state. The I2CRS bit can be used to Hardware Slave Mode reset the I2C interface. This bit can be used to force the inter- After reset, the ADuC834 defaults to hardware slave mode. The face back to the default idle state. I2C interface is enabled by clearing the SPE bit in SPICON. Slave mode is enabled by clearing the I2CM bit in I2CCON. It should be noted that there is no way (in hardware) to distin- The ADuC834 has a full hardware slave. In slave mode, the I2C guish between an interrupt generated by a received START + address is stored in the I2CADD register. Data received or to be valid address and an interrupt generated by a received data byte. transmitted is stored in the I2CDAT register. User software must be used to distinguish between these interrupts. REV. A –47–, DUAL DATA POINTER DPCON Data Pointer Control SFR The ADuC834 incorporates two data pointers. The second data SFR Address A7H pointer is a shadow data pointer and is selected via the data Power-On Default Value 00H pointer control SFR (DPCON). DPCON also includes features Bit Addressable No such as automatic hardware post-increment and post-decrement, as well as automatic data pointer toggle. DPCON is described in Table XXIII. Table XXIII. DPCON SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 DPT Data Pointer Automatic Toggle Enable. Cleared by user to disable auto swapping of the DPTR. Set in user software to enable automatic toggling of the DPTR after each MOVX or MOVC instruction. 5 DP1m1 Shadow Data Pointer Mode 4 DP1m0 These two bits enable extra modes of the shadow data pointer operation allowing for more compact and more efficient code size and execution. m1 m0 Behavior of the Shadow Data Pointer008052 Behavior01DPTR is post-incremented after a MOVX or a MOVC instruction10DPTR is post-decremented after a MOVX or MOVC instruction11DPTR LSB is toggled after a MOVX or MOVC instruction (This instruction can be useful for moving 8-bit blocks to/from 16-bit devices) 3 DP0m1 Main Data Pointer Mode 2 DP0m0 These two bits enable extra modes of the main data pointer operation allowing for more compact and more efficient code size and execution. m1 m0 Behavior of the Main Data Pointer008052 Behavior01DPTR is post-incremented after a MOVX or a MOVC instruction10DPTR is post-decremented after a MOVX or MOVC instruction11DPTR LSB is toggled after a MOVX or MOVC instruction (This instruction can be useful for moving 8-bit blocks to/from 16-bit devices) 1 ––– This bit is not implemented to allow the INC DPCON instruction toggle the data pointer without incrementing the rest of the SFR. 0 DPSEL Data Pointer Select. Cleared by user to select the main data pointer. This means that the contents of the main 24-bit DPTR appears in the 3 SFRs DPL, DPH, and DPP. Set by the user to select the shadow data pointer. This means that the contents of the shadow 24-bit DPTR appears in the 3 SFRs DPL, DPH, and DPP.

NOTES

1. This is the only place where the main and shadow data pointers are distinguished. Everywhere else in this data sheet, wherever the DPTR is mentioned, operation on the active DPTR is implied. 2. Only MOVC/MOVX @DPTR instructions are relevant above. MOVC/MOVX PC/@Ri instructions will not cause the DPTR to automatically post increment/decrement, and so on. To illustrate the operation of DPCON, the following code will copy 256 bytes of code memory at Address D000h into XRAM starting from Address 0000h. the code uses 16 bytes and 2054 cycles. To perform this on a standard 8051 requires approximately 33 bytes and 7172 cycles (depending on how it is implemented). MOVELOOP: MOV DPTR,#0 ; Main DPTR = 0 CLR A MOV DPCON,#55h ; Select shadow DPTR MOVC A,@A+DPTR ; Get data ; DPTR1 increment mode, ; Post Inc DPTR ; DPTR0 increment mode ; Swap to Main DPTR (Data) ; DPTR auto toggling ON MOVX @DPTR,A ; Put ACC in XRAM MOV DPTR,#0D000h ; Shadow DPTR = D000h ; Increment main DPTR ; Swap to Shad DPTR (Code) MOV A, DPL JNZ MOVELOOP –48– REV. A, 8052 COMPATIBLE ON-CHIP PERIPHERALS Port 1 This section gives a brief overview of the various secondary Port 1 is also an 8-bit port directly controlled via the P1 SFR. peripheral circuits that are also available to the user on-chip. The Port 1 pins are divided into two distinct pin groupings P1.0 These remaining functions are mostly 8052 compatible (with a to P1.1 and P1.2 to P1.7. few additional features) and are controlled via standard 8052 P1.0 and P1.1 SFR bit definitions. P1.0 and P1.1 are bidirectional digital I/O pins with internal Parallel I/O pull-ups. The ADuC834 uses four input/output ports to exchange data If P1.0 and P1.1 have 1s written to them via the P1 SFR, these with external devices. In addition to performing general-purpose pins are pulled high by the internal pull-up resistors. In this state, I/O, some ports are capable of external memory operations while they can also be used as inputs. As input pins being externally others are multiplexed with alternate functions for the peripheral pulled low, they will source current because of the internal features on the device. In general, when a peripheral is enabled, pull-ups. With 0s written to them, both these pins will drive a that pin may not be used as a general-purpose I/O pin. logic low output voltage (VOL) and will be capable of sinking Port 0 10 mA compared to the standard 1.6 mA sink capability on the Port 0 is an 8-bit open-drain bidirectional I/O port that is directly other port pins. controlled via the Port 0 SFR. Port 0 is also the multiplexed low These pins also have various secondary functions described in order address and databus during accesses to external program Table XXIV. The timer 2 alternate functions of P1.0 and P1.1 or data memory. can only be activated if the corresponding bit latch in the P1 Figure 36 shows a typical bit latch and I/O buffer for a Port 0 port SFR contains a 1. Otherwise, the port pin is stuck at 0. In the pin. The bit latch (one bit in the port’s SFR) is represented as a case of the PWM outputs at P1.0 and P1.1, the PWM outputs Type D flip-flop, which will clock in a value from the internal bus will overwrite anything written to P1.0 or P1.1. in response to a “write to latch” signal from the CPU. The Q output Table XXIV. P1.0 and P1.1 Alternate Pin Functions of the flip-flop is placed on the internal bus in response to a “read latch” signal from the CPU. The level of the port pin itself Pin Alternate Function is placed on the internal bus in response to a “read pin” signal from the CPU. Some instructions that read a port activate the P1.0 T2 (Timer/Counter 2 External Input) “read latch” signal, and others activate the “read pin” signal. PWM0 (PWM0 output at this pin) See the following Read-Modify-Write Instructions section for P1.1 T2EX (Timer/Counter 2 Capture/Reload Trigger) more details. PWM1 (PWM1 output at this pin) ADDR/DATA DVDD Figure 37 shows a typical bit latch and I/O buffer for a P1.0 or CONTROL P1.1 port pin. No external memory access is required from

READ

LATCH either of these pins although internal pull-ups are present. P0.x DVDD INTERNAL PIN BUSDQALTERNATEREAD OUTPUT FUNCTION INTERNAL LATCH PULL-UP*

WRITE

TO LATCH CL Q P1.x LATCH INTERNALDQPINBUS

READ

PIN WRITETO LATCH CL Q

LATCH

Figure 36. Port 0 Bit Latch and I/O Buffer As shown in Figure 36, the output drivers of Port 0 pins are READPIN ALTERNATE *SEE FIGURE 38FOR DETAILS OF switchable to an internal ADDR and ADDR/DATA bus by an INPUTFUNCTION INTERNAL PULL-UP internal CONTROL signal for use in external memory accesses. Figure 37. P1.0 and P1.1 Bit Latch and I/O Buffer During external memory accesses, the P0 SFR gets 1s written to it (i.e., all of its bit latches become 1). When accessing external The internal pull-up consists of active circuitry as shown in memory, the CONTROL signal in Figure 36 goes high, enabling Figure 38. Whenever a P1.0 or P1.1 bit latch transitions from push-pull operation of the output pin from the internal address low to high, Q1 in Figure 38 turns on for 2 oscillator periods to or databus (ADDR/DATA line). Therefore, no external pull-ups quickly pull the pin to a logic high state. Once there, the weaker are required on Port 0 in order for it to access external memory. Q3 turns on, thereby latching the pin to a logic high. If the pin is momentarily pulled low externally, Q3 will turn off, but the In general-purpose I/O port mode, Port 0 pins that have 1s very weak Q2 will continue to source some current into the pin, written to them via the Port 0 SFR will be configured as open- attempting to restore it to a logic high. drain and will therefore float. In this state, Port 0 pins can be used as high impedance inputs. This is represented in Figure 36 DVDD DVDD DVDD by the NAND gate whose output remains high as long as the 2 CLK Q1 Q2 Q3

DELAY

CONTROL signal is low, thereby disabling the top FET. Exter- nal pull-up resistors are therefore required when Port 0 pins are Q Px.x used as general-purpose outputs. Port 0 pins with 0s written to Q4FROM PIN them will drive a logic low output voltage (V ) and will be PORTOL LATCH capable of sinking 1.6 mA. Figure 38. Internal Pull-Up Configuration REV. A –49–, P1.2 to P1.7 Port 3 pins also have various secondary functions described in The remaining Port 1 pins (P1.2–P1.7) can only be configured as Table XXV. The alternate functions of Port 3 pins can only be analog input (ADC) or digital input pins. By (power-on) default, activated if the corresponding bit latch in the P3 SFR contains a 1. these pins are configured as analog inputs, i.e., ‘1’ written in the Otherwise, the port pin is stuck at 0. corresponding Port 1 register bit. To configure any of these pins as digital inputs, the user should write a ‘0’ to these port bits to Table XXV. Port 3, Alternate Pin Functions configure the corresponding pin as a high impedance digital Pin Alternate Function input. Figure 39 illustrates this function. Note that there are no output drivers for Port 1 pins, and they therefore cannot be P3.0 RxD (UART Input Pin) used as outputs. (or Serial Data I/O in Mode 0) P3.1 TxD (UART Output Pin) READ (or Serial Clock Output in Mode 0) LATCH P3.2 INT0 (External Interrupt 0) INTERNAL P3.3 INT1 (External Interrupt 1) BUSDQP3.4 T0 (Timer/Counter 0 External Input)

WRITE

TO LATCH CL Q PWMCLK (PWM External Clock) LATCH P3.5 T1 (Timer/Counter 1 External Input) P1.x READ PIN PIN TO ADC P3.6 WR (External Data Memory Write Strobe) P3.7 RD (External Data Memory Read Strobe)

Figure 39. P1.2 to P1.7 Bit Latch and I/O Buffer

Port 3 pins have the same bit latch and I/O buffer configurations Port 2 as the P1.0 and P1.1 as shown in Figure 41. The internal pull-up Port 2 is a bidirectional port with internal pull-up resistors directly configuration is also defined by that in Figure 38. controlled via the P2 SFR. Port 2 also emits the high order address bytes during fetches from external program memory DVDD and middle and high order address bytes during accesses to the

ALTERNATE

24-bit external data memory space. READ OUTPUT INTERNAL LATCH FUNCTION PULL-UP* As shown in Figure 40, the output drivers of Ports 2 are switch- able to an internal ADDR bus by an internal CONTROL signal P3.xINTERNAL PIN for use in external memory accesses (as for Port 0). In external BUSDQmemory addressing mode (CONTROL = 1), the port pins WRITE CL Q feature push/pull operation controlled by the internal address TO LATCH LATCH bus (ADDR line). However unlike the P0 SFR during external memory accesses, the P2 SFR remains unchanged. READ PIN ALTERNATE *SEE FIGURE 38 In general-purpose I/O port mode, Port 2 pins that have 1s written INPUT FOR DETAILS OFINTERNAL PULL-UP to them are pulled high by the internal pull-ups (Figure 38) and, FUNCTION in that state, they can be used as inputs. As inputs, Port 2 pins Figure 41. Port 3 Bit Latch and I/O Buffer being pulled externally low will source current because of the Additional Digital I/O internal pull-up resistors. Port 2 pins with 0s written to them In addition to the port pins, the dedicated SPI/I2C pins (SCLOCK will drive a logic low output voltage (VOL) and will be capable and SDATA/MOSI) also feature both input and output functions. of sinking 1.6 mA. Their equivalent I/O architectures are illustrated in Figure 42 ADDR and Figure 44, respectively, for SPI operation and in Figure 43 READ DV DVDD LATCH CONTROL DD and Figure 45 for I2C operation.

INTERNAL

PULL-UP* Notice that in I2C mode (SPE = 0), the strong pull-up FET

INTERNAL

BUSDQP2.x (Q1) is disabled leaving only a weak pull-up (Q2) present. By PIN contrast, in SPI mode (SPE = 1), the strong pull-up FET (Q1)

WRITE

TO LATCH CL Q is controlled directly by SPI hardware, giving the pin push/pull LATCH capability. READ *SEE FIGURE 38 FOR PIN DETAILS OF INTERNAL PULL-UP In I2C mode (SPE = 0), two pull-down FETs (Q3 and Q4)

Figure 40. Port 2 Bit Latch and I/O Buffer operate in parallel in order to provide an extra 60% or 70% of

Port 3 current sinking capability. In SPI mode, however, (SPE = 1), only Port 3 is a bidirectional port with internal pull-ups directly one of the pull-down FETs (Q3) operates on each pin resulting controlled via the P3 SFR. in sink capabilities identical to that of Port 0 and Port 2 pins. Port 3 pins that have 1s written to them are pulled high by the On the input path of SCLOCK, notice that a Schmitt trigger internal pull-ups and in that state they can be used as inputs. As conditions the signal going to the SPI hardware to prevent false inputs, Port 3 pins being pulled externally low will source current triggers (double triggers) on slow incoming edges. For incoming2 because of the internal pull-ups. Port 3 pins with 0s written to signals from the SCLOCK and SDATA pins going toIChard- them will drive a logic low output voltage (V ) and will be ware, a filter conditions the signals in order to reject glitches ofOL capable of sinking 1.6 mA. up to 50 ns in duration. –50– REV. A, Notice also that direct access to the SCLOCK and SDATA/MOSI As shown in Figure 46, the MISO pin in SPI master/slave pins is afforded through the SFR interface in I2C master mode. operation offers the exact same pull-up and pull-down configu- Therefore, if you are not using the SPI or I2C functions, you can ration as the MOSI pin in SPI slave/master operation. use these two pins to give additional high current digital outputs. The SS pin has a weak internal pull-up permanently enabled to prevent the SS input from floating. This pull-up can be easily

DV

SPE = 1 (SPI ENABLE) DD overdriven by an external device to drive the SS pin low. Q1 Q2 (OFF) DVDD HARDWARE SPI SCLOCK (MASTER/SLAVE) PIN SCHMITT Q4 (OFF) TRIGGER HARDWARE SPI MISO Q3 (MASTER/SLAVE) PIN

Figure 42. SCLOCK Pin I/O Functional Equivalent in SPI Mode Figure 46. MISO Pin I/O Functional Equivalent DVDD

SPE = 0 (I2C ENABLE)

DVDD

HARDWARE I2C Q1 (SLAVE ONLY) (OFF) SFR 50ns GLITCH Q2 BITS REJECTION FILTER HARDWARE SPI SS (MASTER/SLAVE) PIN

SCLOCK PIN

MCO Figure 47. SS Pin I/O Functional Equivalent Q4 Q3 I2CM Read-Modify-Write Instructions Some 8051 instructions that read a port read the latch and

Figure 43. SCLOCK Pin I/O Functional Equivalent in others read the pin. The instructions that read the latch rather I2C Mode than the pins are the ones that read a value, possibly change it,

and then rewrite it to the latch. These are called “read-modify- DVDD write” instructions. Listed below are the read-modify-write SPE = 1 (SPI ENABLE) instructions. When the destination operand is a port, or a port bit, these instructions read the latch rather than the pin. Q1 Q2 (OFF) ANL (Logical AND, e.g., ANL P1, A) HARDWARE SPI SDATA/MOSI ORL (Logical OR, e.g., ORL P2, A)(MASTER/SLAVE) PIN XRL (Logical EX-OR, e.g., XRL P3, A) Q4 (OFF) JBC (Jump If Bit = 1 and Clear Bit, e.g., JBC P1.1, LABEL Q3 CPL (Complement Bit, e.g., CPL P3.0) INC (Increment, e.g., INC P2)

Figure 44. SDATA/MOSI Pin I/O Functional Equivalent DEC (Decrement, e.g., DEC P2)

in SPI Mode DJNZ (Decrement and Jump IFf Not Zero, e.g.,DJNZ P3, LABEL) MOV PX.Y, C* (Move Carry to Bit Y of Port X) DVDD CLR PX.Y* (Clear Bit Y of Port X) SPE = 0 (I2C ENABLE) SETB PX.Y* (Set Bit Y of Port X) Q1 HARDWARE I2C (OFF) The reason that read-modify-write instructions are directed to (SLAVE ONLY) SFR Q2 the latch rather than the pin is to avoid a possible misinterpreta- BITS 50ns GLITCH tion of the voltage level of a pin. For example, a port pin might REJECTION FILTER SDATA/ be used to drive the base of a transistor. Whena1is written to MDI MOSI PIN the bit, the transistor is turned on. If the CPU then reads the same port bit at the pin rather then the latch, it will read the MDO Q4 base voltage of the transistor and interpret it as a Logic 0. Read- ing the latch rather than the pin will return the correct value of 1. Q3

MDE

I2CM

Figure 45. SDATA/MOSI Pin I/O Functional Equivalent

in I2C Mode *These instruction read the port byte (all 8 bits), modify the addressed bit and then write the new byte back to the latch.

REV. A –51–

, TIMERS/COUNTERS S5P2 of every machine cycle. When the samples show a high in The ADuC834 has three 16-bit Timer/Counters: Timer 0, one cycle and a low in the next cycle, the count is incremented. Timer 1, and Timer 2. The Timer/Counter hardware has been The new count value appears in the register during S3P1 of the included on-chip to relieve the processor core of the overhead cycle following the one in which the transition was detected. inherent in implementing timer/counter functionality in soft- Since it takes two machine cycles (16 core clock periods) to ware. Each Timer/Counter consists of two 8-bit registers THx recognize a 1-to-0 transition, the maximum count rate is 1/16 of and TLx (x = 0, 1 and 2). All three can be configured to oper- the core clock frequency. There are no restrictions on the duty ate either as timers or event counters. cycle of the external input signal, but to ensure that a given level In ‘Timer’ function, the TLx Register is incremented every is sampled at least once before it changes, it must be held for a machine cycle. Thus it can be viewed as counting machine minimum of one full machine cycle. Remember that the core cycles. Since a machine cycle consists of 12 core clock periods, clock frequency is programmed via the CD0–2 selection bits in the maximum count rate is 1/12 of the core clock frequency. the PLLCON SFR. In ‘Counter’ function, the TLx Register is incremented by a User configuration and control of the timers is achieved via 1-to-0 transition at its corresponding external input pin, T0, three main SFRs. TMOD and TCON control the configuration T1, or T2. In this function, the external input is sampled during of Timers 0 and 1 while T2CON configures Timer 2. TMOD Timer/Counter 0 and 1 Mode Register SFR Address 89H Power-On Default Value 00H Bit Addressable No Table XXVI. TMOD SFR Bit Designations Bit Name Description 7 Gate Timer 1 Gating Control. Set by software to enable timer/counter 1 only while INT1 pin is high and TR1 control bit is set. Cleared by software to enable Timer 1 whenever TR1 control bit is set. 6 C/T Timer 1 Timer or Counter Select Bit. Set by software to select counter operation (input from T1 pin). Cleared by software to select timer operation (input from internal system clock). 5 M1 Timer 1 Mode Select Bit 1 (used with M0 Bit) 4 M0 Timer 1 Mode Select Bit 0. M1 M000TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler. 1 0 8-Bit Auto-Reload Timer/Counter. TH1 holds a value that is to be reloaded into TL1 each time it overflows. 1 1 Timer/Counter 1 Stopped. 3 Gate Timer 0 Gating Control. Set by software to enable timer/counter 0 only while INT0 pin is high and TR0 control bit is set. Cleared by software to enable Timer 0 whenever TR0 control bit is set. 2 C/T Timer 0 Timer or Counter Select Bit. Set by software to select counter operation (input from T0 pin). Cleared by software to select timer operation (input from internal system clock). 1 M1 Timer 0 Mode Select Bit10M0 Timer 0 Mode Select Bit 0. M1 M000TH0 operates as an 8-bit timer/counter. TL0 serves as 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler108-Bit Auto-Reload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each time it overflows. 1 1 TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits. –52– REV. A, TCON Timer/Counter 0 and 1 Control Register SFR Address 88H Power-On Default Value 00H Bit Addressable Yes Table XXVII. TCON SFR Bit Designations Bit Name Description 7 TF1 Timer 1 Overflow Flag. Set by hardware on a Timer/Counter 1 overflow. Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine. 6 TR1 Timer 1 Run Control Bit. Set by user to turn on Timer/Counter 1. Cleared by user to turn off Timer/Counter 1. 5 TF0 Timer 0 Overflow Flag. Set by hardware on a Timer/Counter 0 overflow. Cleared by hardware when the PC vectors to the interrupt service routine. 4 TR0 Timer 0 Run Control Bit. Set by user to turn on Timer/Counter 0. Cleared by user to turn off Timer/Counter 0. 3 IE1* External Interrupt 1 (INT1) Flag. Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1, depending on bit IT1 state. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. 2 IT1* External Interrupt 1 (IE1) Trigger Type. Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). Cleared by software to specify level-sensitive detection (i.e., zero level). 1 IE0* External Interrupt 0 (INT0) Flag. Set by hardware by a falling edge or zero level being applied to external interrupt pin INT0, depending on bit IT0 state. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. 0 IT0* External Interrupt 0 (IE0) Trigger Type. Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). Cleared by software to specify level-sensitive detection (i.e., zero level). *These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins. Timer/Counter 0 and 1 Data Registers Both timer 0 and timer 1 consist of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit register, depending on the timer mode configuration. TH0 and TL0 Timer 0 high byte and low byte. SFR Address = 8CH, 8AH, respectively. TH1 and TL1 Timer 1 high byte and low byte. SFR Address = 8DH, 8BH, respectively. REV. A –53–, TIMER/COUNTER 0 AND 1 OPERATING MODES Mode 2 (8-Bit Timer/Counter with Auto Reload) The following paragraphs describe the operating modes for Mode 2 configures the timer register as an 8-bit counter (TL0) Timer/Counters 0 and 1. Unless otherwise noted, it should be with automatic reload, as shown in Figure 50. Overflow from assumed that these modes of operation are the same for Timer 0 TL0 not only sets TF0, but also reloads TL0 with the contents as for Timer 1. of TH0, which are preset by software. The reload leaves TH0 Mode 0 (13-Bit Timer/Counter) unchanged. Mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler. Figure 48 shows Mode 0 operation. CORE CLK 12* C/ T = 0 CORE INTERRUPT CLK 12 TL0* (8 BITS) TF0 C/ T = 0 INTERRUPT C/ T = 1 TL0 TH0 (5 BITS) (8 BITS) TF0 P3.4/T0

CONTROL

C/ T = 1 TR0 P3.4/T0

CONTROL

TR0 RELOADGATE TH0 P3.2/INT0 (8 BITS) GATE *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE "ON-CHIP PLL") P3.2/INT0

Figure 50. Timer/Counter 0, Mode 2

*THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE "ON-CHIP PLL") Mode 3 (Two 8-Bit Timer/Counters)

Figure 48. Timer/Counter 0, Mode 0 Mode 3 has different effects on Timer 0 and Timer 1. Timer 1 in

In this mode, the timer register is configured as a 13-bit register. Mode 3 simply holds its count. The effect is the same as setting As the count rolls over from all 1s to all 0s, it sets the timer over- TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two flow flag. The overflow flag, TF0, can then be used to request separate counters. This configuration is shown in Figure 51. an interrupt. The counted input is enabled to the timer when TL0 uses the timer 0 control bits: C/T, Gate, TR0, INT0, and TR0 = 1 and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows TF0. TH0 is locked into a timer function (counting machine the timer to be controlled by external input INT0, to facilitate cycles) and takes over the use of TR1 and TF1 from Timer 1. pulsewidth measurements. TR0 is a control bit in the special Thus, TH0 now controls the “Timer 1” interrupt. Mode 3 is function register TCON; Gate is in TMOD. The 13-bit register provided for applications requiring an extra 8-bit timer or counter. consists of all eight bits of TH0 and the lower five bits of TL0. When Timer 0 is in Mode 3, Timer 1 can be turned on and off The upper three bits of TL0 are indeterminate and should be by switching it out of and into its own Mode 3, or can still be ignored. Setting the run flag (TR0) does not clear the registers. used by the serial interface as a baud rate generator. In fact, it Mode 1 (16-Bit Timer/Counter) can be used, in any application not requiring an interrupt from Mode 1 is the same as Mode 0, except that the timer register is Timer 1 itself. running with all 16 bits. Mode 1 is shown in Figure 49.

CORE

12 CORE CORE CLK* CLK/12 CLK 12* C/ T = 0

INTERRUPT

C/ T = 0 TL0 INTERRUPT (8 BITS) TF0TL0 TH0 (8 BITS) (8 BITS) TF0 C/ T = 1 C/ T = 1 P3.4/T0 P3.4/T0 CONTROL CONTROL TR0 TR0

GATE

GATE P3.2/INT0 P3.2/INT0 *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE "ON-CHIP PLL")

INTERRUPT

CORE TH0

Figure 49. Timer/Counter 0, Mode 1 CLK/12 (8 BITS) TF1

TR1 *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE "ON-CHIP PLL")

Figure 51. Timer/Counter 0, Mode 3

–54– REV. A, TIMER/COUNTER 2 OPERATING MODES 16-Bit Capture Mode The following paragraphs describe the operating modes for In the Capture Mode, there are again two options, selected by bit Timer/Counter 2. The operating modes are selected by bits in EXEN2 in T2CON. If EXEN2 = 0, Timer 2 is a 16-bit timer or the T2CON SFR as shown in Table XXIX. counter that, upon overflowing, sets bit TF2, the Timer 2 over- flow bit, which can be used to generate an interrupt. If EXEN2 = 1, Table XXVIII. Timer 2 Operating Modes Timer 2 still performs the above, but a l-to-0 transition on external input T2EX causes the current value in the Timer 2 RCLK (or) TCLK CAP2 TR2 MODE registers, TL2 and TH2, to be captured into registers RCAP2L00116-Bit Autoreload and RCAP2H, respectively. In addition, the transition at T2EX01116-Bit Capture causes bit EXF2 in T2CON to be set; EXF2, like TF2, can gener- 1X1Baud Rate ate an interrupt. The Capture Mode is illustrated in Figure 53. XX0OFF The baud rate generator mode is selected by RCLK = 1 and/or TCLK = 1. 16-Bit Autoreload Mode In Autoreload Mode, there are two options, selected by bit In either case, if Timer 2 is being used to generate the baud rate, EXEN2 in T2CON. If EXEN2 = 0, when Timer 2 rolls over it the TF2 interrupt flag will not occur. Therefore Timer 2 interrupts not only sets TF2 but also causes the Timer 2 registers to be will not occur so they do not have to be disabled. However, in reloaded with the 16-bit value in registers RCAP2L and RCAP2H, this mode, the EXF2 flag can still cause interrupts and this can which are preset by software. If EXEN2 = 1, Timer 2 still performs be used as a third external interrupt. the above, but with the added feature that a 1-to-0 transition at Baud rate generation will be described as part of the UART external input T2EX will also trigger the 16-bit reload and set serial port operation. EXF2. The Autoreload Mode is illustrated in Figure 52.

CORE

CLK 12* C/ T2 = 0 TL2 TH2 (8 BITS) (8 BITS) T2 C/ T2 = 1 PIN CONTROL TR2

RELOAD TRANSITION DETECTOR

RCAP2L RCAP2H TF2

TIMER INTERRUPT

T2EX EXF2

PIN CONTROL

EXEN2 *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE "ON-CHIP PLL")

Figure 52. Timer/Counter 2, 16-Bit Autoreload Mode CORE

CLK 12* C/ T2 = 0 TL2 TH2 (8 BITS) (8 BITS) TF2 T2 C/ T2 = 1 PIN CONTROL TR2 CAPTURE TIMERINTERRUPT

TRANSITION DETECTOR

RCAP2L RCAP2H T2EX EXF2

PIN CONTROL

EXEN2 *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE "ON-CHIP PLL")

Figure 53. Timer/Counter 2, 16-Bit Capture Mode REV. A –55–

, T2CON Timer/Counter 2 Control Register SFR Address C8H Power-On Default Value 00H Bit Addressable Yes Table XXIX. T2CON SFR Bit Designations Bit Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a Timer 2 overflow. TF2 will not be set when either RCLK or TCLK = 1. Cleared by user software. 6 EXF2 Timer 2 External Flag. Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. Cleared by user software. 5 RCLK Receive Clock Enable Bit. Set by user to enable the serial port to use Timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. Cleared by user to enable Timer 1 overflow to be used for the receive clock. 4 TCLK Transmit Clock Enable Bit. Set by user to enable the serial port to use Timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. Cleared by user to enable Timer 1 overflow to be used for the transmit clock. 3 EXEN2 Timer 2 External Enable Flag. Set by user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. Cleared by user for Timer 2 to ignore events at T2EX. 2 TR2 Timer 2 Start/Stop Control Bit. Set by user to start Timer 2. Cleared by user to stop Timer 2. 1 CNT2 Timer 2 Timer or Counter Function Select Bit. Set by user to select counter function (input from external T2 Pin). Cleared by user to select timer function (input from on-chip core clock). 0 CAP2 Timer 2 Capture/Reload Select Bit. Set by user to enable captures on negative transitions at T2EX if EXEN2 = 1. Cleared by user to enable auto reloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow. Timer/Counter 2 Data Registers Timer/Counter 2 also has two pairs of 8-bit data registers associated with it. These are used as both timer data registers and timer capture/reload registers. TH2 and TL2 Timer 2, data high byte and low byte. SFR Address = CDH, CCH, respectively. RCAP2H and RCAP2L Timer 2, Capture/Reload byte and low byte. SFR Address = CBH, CAH, respectively. –56– REV. A, UART SERIAL INTERFACE RxD(P3.0) and TxD(P3.1), while the SFR interface to the UART The serial port is full duplex, meaning it can transmit and comprises the following registers: receive simultaneously. It is also receive-buffered, meaning it SBUF can commence reception of a second byte before a previously The serial port receive and transmit registers are both accessed received byte has been read from the receive register. However, through the SBUF SFR (SFR address = 99H). Writing to SBUF if the first byte still has not been read by the time reception of loads the transmit register and reading SBUF accesses a physically the second byte is complete, the first byte will be lost. The separate receive register. physical interface to the serial data network is via Pins SCON UART Serial Port Control Registers SFR Address 98H Power-On Default Value 00H Bit Addressable Yes Table XXX. SCON SFR Bit Designations Bit Name Description 7 SM0 UART Serial Mode Select Bits. 6 SM1 These bits select the Serial Port operating mode as follows: SM0 SM1 Selected Operating Mode00Mode 0: Shift Register, fixed baud rate (fCORE/12) 0 1 Mode 1: 8-bit UART, variable baud rate10Mode 2: 9-bit UART, fixed baud rate (fCORE/64) or (fCORE/32) 1 1 Mode 3: 9-bit UART, variable baud rate 5 SM2 Multiprocessor Communication Enable Bit. Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared. In Mode 1, if SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is cleared, RI will be set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is set, RI will not be activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI will be set as soon as the byte of data has been received. 4 REN Serial Port Receive Enable Bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. 3 TB8 Serial Port Transmit (Bit 9). The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3. 2 RB8 Serial Port Receiver Bit 9. The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1, the stop bit is latched into RB8. 1 TI Serial Port Transmit Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3. TI must be cleared by user software. 0 RI Serial Port Receive Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0, or halfway through the stop bit in Modes 1, 2, and 3. RI must be cleared by software. UART OPERATING MODES MACHINE MACHINE MACHINE MACHINECYCLE 1 CYCLE 2 CYCLE 7 CYCLE 8 Mode 0: 8-Bit Shift Register Mode S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S4 S5 S6 S1 S2 S3 S4 S5 S6 Mode 0 is selected by clearing both the SM0 and SM1 bits in the SFR SCON. Serial data enters and exits through RxD. TxD outputs CORECLK the shift clock. Eight data bits are transmitted or received. Trans- mission is initiated by any instruction that writes to SBUF. The ALE data is shifted out of the RxD line. The 8 bits are transmitted RxD (DATA OUT) DATA BIT 0 DATA BIT 1 DATA BIT 6 DATA BIT 7 with the least-significant bit (LSB) first, as shown in Figure 54. TxD Reception is initiated when the Receive Enable bit (REN) is (SHIFT CLOCK) 1 and the Receive Interrupt bit (RI) is 0. When RI is cleared, Figure 54. UART Serial Port Transmission, Mode 0 the data is clocked into the RxD line and the clock pulses are output from the TxD line. REV. A –57–, Mode 1: 8-Bit UART, Variable Baud Rate The transmission will start at the next valid baud rate clock. Mode 1 is selected by clearing SM0 and setting SM1. Each data The TI flag is set as soon as the stop bit appears on TxD. byte (LSB first) is preceded by a start bit (0) and followed by a Reception for Mode 2 is similar to that of Mode 1. The eight stop bit (1). Therefore 10 bits are transmitted on TxD or received data bytes are input at RxD (LSB first) and loaded onto the on RxD. The baud rate can be set by Timer 1 or Timer 2 (or Receive Shift Register. When all eight bits have been clocked in, both). Alternatively, a dedicated baud rate generator, Timer 3, is the following events occur: provided on-chip to generate high speed, very accurate baud rates. • The eight bits in the Receive Shift Register are latched Transmission is initiated by writing to SBUF. The ‘write to into SBUF SBUF’ signal also loadsa1(stop bit) into the ninth bit position of the Transmit Shift Register. The data is output bit by bit until • The ninth data bit is latched into RB8 in SCON the stop bit appears on TxD and the transmit interrupt flag (TI) • The Receiver Interrupt flag (RI) is set is automatically set as shown in Figure 55. if, and only if, the following conditions are met at the time the START STOP BIT final shift pulse is generated:

BIT

D0 D1 D2 D3 D4 D5 D6 D7 TxD • RI = 0, and TI • Either SM2 = 0, or SM2 = 1 and the received stop bit = 1. (SCON.1) If either of these conditions is not met, the received frame is SET INTERRUPT i.e., READY FOR MORE DATA irretrievably lost and RI is not set. Figure 55. UART Serial Port Transmission, Mode 0 Mode 3: 9-Bit UART with Variable Baud Rate Mode 3 is selected by setting both SM0 and SM1. In this mode, Reception is initiated when a 1-to-0 transition is detected on the 8051 UART serial port operates in 9-bit mode with a variable RxD. Assuming a valid start bit was detected, character recep- baud rate determined by either Timer 1 or Timer 2. The opera- tion continues. The start bit is skipped and the eight data bits tion of the 9-bit UART is the same as for Mode 2, but the baud are clocked into the serial port shift register. When all eight bits rate can be varied as for Mode 1. have been clocked in, the following events occur: In all four modes, transmission is initiated by any instruction that • The eight bits in the receive shift register are latched into uses SBUF as a destination register. Reception is initiated in SBUF Mode 0 by the condition RI = 0 and REN = 1. Reception is • The ninth bit (stop bit) is clocked into RB8 in SCON initiated in the other modes by the incoming start bit if REN = 1. • The Receiver Interrupt flag (RI) is set UART Serial Port Baud Rate Generation if, and only if, the following conditions are met at the time the Mode 0 Baud Rate Generation final shift pulse is generated: The baud rate in Mode 0 is fixed: • RI = 0, and f Mode 0 Baud Rate = CORE* • Either SM2 = 0, or SM2 = 1 and the received stop bit = 1. 12 If either of these conditions is not met, the received frame is Mode 2 Baud Rate Generation irretrievably lost and RI is not set. The baud rate in Mode 2 depends on the value of the SMOD bit in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the Mode 2: 9-Bit UART with Fixed Baud Rate core clock. If SMOD = 1, the baud rate is 1/32 of the core clock: Mode 2 is selected by setting SM0 and clearing SM1. In this

SMOD

mode, the UART operates in 9-bit mode with a fixed baud rate. fCORE* × 2Mode 2 Baud Rate = The baud rate is fixed at Core_Clk/64 by default, although by 64 setting the SMOD bit in PCON, the frequency can be doubled to Core_Clk/32. Eleven bits are transmitted or received, a start Mode 1 and 3 Baud Rate Generation bit (0), eight data bits, a programmable ninth bit, and a stop bit Traditionally, the baud rates in Modes 1 and 3 are determined (1). The ninth bit is most often used as a parity bit, although it by the overflow rate in Timer 1 or Timer 2, or both (one for can be used for anything, including a ninth data bit if required. transmit and the other for receive). On the ADuC834, however, the baud rate can also be generated via a separate baud rate To transmit, the eight data bits must be written into SBUF. The generator to achieve higher baud rates and allow all three to be ninth bit must be written to TB8 in SCON. When transmission used for other functions. is initiated, the eight data bits (from SBUF) are loaded onto the transmit shift register (LSB first). The contents of TB8 are loaded into the ninth bit position of the transmit shift register. *fCORE refers to the output of the PLL as described in the “On-Chip PLL” section. –58– REV. A, BAUD RATE GENERATION USING TIMER 1 AND TIMER 2 Timer 2 Generated Baud Rates Timer 1 Generated Baud Rates Baud rates can also be generated using Timer 2. Using Timer 2 When Timer 1 is used as the baud rate generator, the baud rates is similar to using Timer 1 in that the timer must overflow 16 in Modes 1 and 3 are determined by the Timer 1 overflow rate times before a bit is transmitted/received. Because Timer 2 has and the value of SMOD as follows: a 16-bit Autoreload Mode, a wider range of baud rates is pos- sible using Timer 2. Modes 1 and 3 Baud Rate = (2SMOD ⁄ 32) × (Timer 1 Overflow Rate)

Mode 1 and Mode 3 Baud Rate = (1 16) × (Timer 2 Overflow Rate)

The Timer 1 interrupt should be disabled in this application. The timer itself can be configured for either timer or counter Therefore when Timer 2 is used to generate baud rates, the operation, and in any of its three running modes. In the most timer increments every two clock cycles and not every core typical application, it is configured for timer operation, in the machine cycle as before. Thus, it increments six times faster Autoreload Mode (high nibble of TMOD = 0100 binary). In than Timer 1, and therefore baud rates six times faster are pos- that case, the baud rate is given by the formula: sible. Because Timer 2 has a 16-bit autoreload capability, very low baud rates are still possible. 2SMOD × f

Mode 1 and Mode 3 Baud Rate = CORE Timer 2 is selected as the baud rate generator by setting the

32 × 12 (256 − TH1) TCLK and/or RCLK in T2CON. The baud rates for transmit and receive can be simultaneously different. Setting RCLK and/or A very low baud rate can also be achieved with Timer 1 by TCLK puts Timer 2 into its baud rate generator mode as shown leaving the Timer 1 interrupt enabled, configuring the timer to in Figure 56. In this case, the baud rate is given by the formula: run as a 16-bit timer (high nibble of TMOD = 0100 binary), and using the Timer 1 interrupt to do a 16-bit software reload. fMode 1 and Mode 3 Baud Rate = CORE Table XXXI shows some commonly-used baud rates and how 32 × (65536 − RCAP2H L) they might be calculated from a core clock frequency of 1.5728 MHz and 12.58 MHz using Timer 1. Generally speaking, a 5% Table XXXII shows some commonly used baud rates and error is tolerable using asynchronous (start/stop) communications. how they might be calculated from a core clock frequency of 1.5728 MHz and 12.5829 MHz using Timer 2. Table XXXI. Commonly Used Baud Rates, Timer 1 Table XXXII. Commonly Used Baud Rates, Timer 2 Ideal Core SMOD TH1-Reload Actual % Baud CLK Value Value Baud Error Ideal Core RCAP2H RCAP2L Actual % 9600 12.58 1 –7 (F9H) 9362 2.5 Baud CLK Value Value Baud Error 1600 12.58 1 –27 (E5H) 1627 1.1 19200 12.58 –1 (FFH) –20 (ECH) 19661 2.4 1200 12.58 1 –55 (C9H) 1192 0.7 9600 12.58 –1 (FFH) –41 (D7H) 9591 0.1 1200 1.57 1 –7 (F9H) 1170 2.5 1600 12.58 –1 (FFH) –164 (5CH) 2398 0.1 1200 12.58 –2 (FEH) –72 (B8H) 1199 0.1 9600 1.57 –1 (FFH) –5 (FBH) 9830 2.4 1600 1.57 –1 (FFH) –20 (ECH) 1658 2.4 1200 1.57 –1 (FFH) –41 (D7H) 1199 0.1 TIMER 1

OVERFLOW

OSC. FREQ. IS DIVIDED BY 2, NOT 12. 201

SMOD

CORE 2 CONTROL CLK* C/ T2 = 0 TIMER 2 TL2 TH2 OVERFLOW10(8 BITS) (8 BITS) RCLK T2 C/ T2 = 1 RX PIN 16 CLOCK10TR2 TCLK NOTE AVAILABILITY OF ADDITIONAL RELOAD EXTERNAL INTERRUPT 16 TXCLOCK RCAP2L RCAP2H T2EX EXF 2 TIMER 2 PIN INTERRUPT

CONTROL TRANSITION DETECTOR

EXEN2 *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE "ON-CHIP PLL")

Figure 56. Timer 2, UART Baud Rates REV. A –59–

, BAUD RATE GENERATION USING TIMER 3 The appropriate value to write to the DIV2-1-0 bits can be The high integer dividers in a UART block means that high calculated using the following formula where fCORE is the output speed baud rates are not always possible using some particular of the PLL as described in the “On-Chip PLL” description. crystals. e.g., using a 12 MHz crystal, a baud rate of 115200 is Note: The DIV value must be rounded down. not possible. To address this problem the ADuC834 has added a dedicated baud rate timer (Timer 3) specifically for generating fCORE highly accurate baud rates. log 32 × Baud Rate DIV = Timer 3 can be used instead of Timer 1 or Timer 2 for generating log(2) very accurate high speed UART baud rates including 115200 and 230400. Timer 3 also allows a much wider range of baud T3FD is the fractional divider ratio required to achieve the rates to be obtained. In fact, every desired bit rate from 12 bits required baud rate. We can calculate the appropriate value for to 393216 bits can be generated to within an error of ±0.8%. T3FD using the following formula. Timer 3 also frees up the other three timers allowing them to be Note: T3FD should be rounded to the nearest integer. used for different applications. A block diagram of Timer 3 is shown in Figure 57. 2 × fT3FD = CORE − 64 2DIV × Baud Rate CORE 2 CLK* Once the values for DIV and T3FD are calculated, the actual TIMER 1/TIMER 2 baud rate can be calculated using the following formula: TX CLOCK (FIG 56)

FRACTIONAL

DIVIDER (1 + T3FD/64) TIMER 1/TIMER22× fCORERX CLOCK (FIG 56) Actual Baud Rate = 2DIV × T3FD + 6410( ) 2DIV For a baud rate of 115200 while operating from the maximum RX core frequency (CD = 0) we have:

CLOCK

1 0 16 DIV = log(12582912/32 × 115200) / log 2 = 1.77 = 1 T3 RX/TX T3EN CLOCK TX CLOCK T3FD = (2 × 12.582912) (21 × 115200) − 64 = 45.22 = 2Dh *THE CORE CLOCK IS THE OUTPUT OF THE PLL (SEE "ON-CHIP PLL") Therefore, the actual baud rate is 115439 bits. Figure 57. Timer 3, UART Baud Rates Two SFRs (T3CON and T3FD) are used to control Timer 3. Table XXXIV. Commonly Used Baud Rates Using Timer 3 T3CON is the baud rate control SFR, allowing Timer 3 to be used to set up the UART baud rate, and setting up the binary Ideal % divider (DIV). Baud CD DIV T3CON T3FD Error 2304000080H 2DH 0.2 Table XXXIII. T3CON SFR Bit Designations 1152000181H 2DH 0.2 Bit Name Description 1152001080H 2DH 0.2 7 T3EN Set to enable Timer 3 to generate the baud rate. When set PCON.7, T2CON.4 and 576000282H 2DH 0.2 T2CON.5 are ignored. Cleared to let the baud 576001181H 2DH 0.2 rate be generated as per a standard 8052. 576002080H 2DH 0.2 6 ––– Reserved for future use 384000383H 12H 0.1 5 ––– Reserved for future use 384001282H 12H 0.1 4 ––– Reserved for future use 384002181H 12H 0.1 3 ––– Reserved for future use 384003080H 12H 0.1 2 DIV2 Binary Divider Factor 192000484H 12H 0.1 1 DIV1 DIV2 DIV1 DIV0 Bin Divider 192001383H 12H 0.1 0 DIV00001192002282H 12H 0.10012192003181H 12H 0.10104192004080H 12H 0.1011810016 96000585H 12H 0.110132 96001484H 12H 0.111064 96002383H 12H 0.1111128 96003282H 12H 0.1 96004181H 12H 0.1 96005080H 12H 0.1 384000383H 12H 0.1 –60– REV. A, INTERRUPT SYSTEM The ADuC834 provides a total of 11 interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three interrupt-related SFRs. These are the IE (Interrupt Enable) Register, the IP (Interrupt Priority Register) and the IEIP2 (Secondary Interrupt Enable/Priority SFR) Registers. Their bit definitions are given in the Tables XXXV – XXXVII. IE Interrupt Enable Register SFR Address A8H Power-On Default Value 00H Bit Addressable Yes Table XXXV. IE SFR Bit Designations Bit Name Description 7 EA Written by User to Enable ‘1’ or Disable ‘0’ All Interrupt Sources 6 EADC Written by User to Enable ‘1’ or Disable ‘0’ ADC Interrupt 5 ET2 Written by User to Enable ‘1’ or Disable ‘0’ Timer 2 Interrupt 4 ES Written by User to Enable ‘1’ or Disable ‘0’ UART Serial Port Interrupt 3 ET1 Written by User to Enable ‘1’ or Disable ‘0’ Timer 1 Interrupt 2 EX1 Written by User to Enable ‘1’ or Disable ‘0’ External Interrupt11ET0 Written by User to Enable ‘1’ or Disable ‘0’ Timer 0 Interrupt 0 EX0 Written by User to Enable ‘1’ or Disable ‘0’ External Interrupt 0 IP Interrupt Priority Register SFR Address B8H Power-On Default Value 00H Bit Addressable Yes Table XXXVI. IP SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 PADC Written by User to Select ADC Interrupt Priority (‘1’ = High; ‘0’ = Low) 5 PT2 Written by User to Select Timer 2 Interrupt Priority (‘1’ = High; ‘0’ = Low) 4 PS Written by User to Select UART Serial Port Interrupt Priority (‘1’ = High; ‘0’ = Low) 3 PT1 Written by User to Select Timer 1 Interrupt Priority (‘1’ = High; ‘0’ = Low) 2 PX1 Written by User to Select External Interrupt 1 Priority (‘1’ = High; ‘0’ = Low) 1 PT0 Written by User to Select Timer 0 Interrupt Priority (‘1’ = High; ‘0’ = Low) 0 PX0 Written by User to Select External Interrupt 0 Priority (‘1’ = High; ‘0’ = Low) IEIP2 Secondary Interrupt Enable and Priority Register SFR Address A9H Power-On Default Value A0H Bit Addressable No Table XXXVII. IEIP2 SFR Bit Designations Bit Name Description 7 ––– Reserved for Future Use 6 PTI Written by User to Select TIC Interrupt Priority (‘1’ = High; ‘0’ = Low) 5 PPSM Written by User to Select Power Supply Monitor Interrupt Priority (‘1’ = High; ‘0’ = Low) 4 PSI Written by User to Select SPI/I2C Serial Port Interrupt Priority (‘1’ = High; ‘0’ = Low) 3 ––– Reserved. This Bit Must Be ‘0.’ 2 ETI Written by User to Enable ‘1’ or Disable ‘0’ TIC Interrupt 1 EPSM Written by User to Enable ‘1’ or Disable ‘0’ Power Supply Monitor Interrupt 0 ESI Written by User to Enable ‘1’ or Disable ‘0’ SPI/I2C Serial Port Interrupt REV. A –61–, Interrupt Priority Interrupt Vectors The Interrupt Enable registers are written by the user to enable When an interrupt occurs, the program counter is pushed onto individual interrupt sources, while the Interrupt Priority registers the stack and the corresponding interrupt vector address is allow the user to select one of two priority levels for each inter- loaded into the program counter. The interrupt vector addresses rupt. An interrupt of a high priority may interrupt the service are shown in Table XXXIX. routine of a low priority interrupt, and if two interrupts of different priority occur at the same time, the higher level interrupt will be Table XXXIX. Interrupt Vector Addresses serviced first. An interrupt cannot be interrupted by another interrupt of the same priority level. If two interrupts of the same Source Vector Address priority level occur simultaneously, a polling sequence is used to IE0 0003H determine which interrupt is serviced first. The polling sequence TF0 000BH is shown in Table XXXVIII. IE1 0013H TF1 001BH Table XXXVIII. Priority within an Interrupt Level RI + TI 0023H TF2 + EXF2 002BH Source Priority Description RDY0/RDY1 (ADC) 0033H PSMI 1 (Highest) Power Supply Monitor Interrupt ISPI/I2CI 003BH WDS 2 Watchdog Interrupt PSMI 0043H IE0 3 External Interrupt 0 TII 0053H RDY0/RDY1 4 ADC Interrupt WDS (WDIR = 1)* 005BH TF0 5 Timer/Counter 0 Interrupt *The watchdog can be configured to generate an interrupt instead of a reset IE1 6 External Interrupt 1 when it times out. This is used for logging errors or to examine the internal TF1 7 Timer/Counter 1 Interrupt status of the microcontroller core to understand, from a software debug pointof view, why a watchdog timeout occurred. The watchdog interrupt is slightly ISPI/I2CI 8 SPI Interrupt different from the normal interrupts in that its priority level is always set to 1 RI + TI 9 Serial Interrupt and it is not possible to disable the interrupt via the global disable bit (EA) in TF2 + EXF2 10 Timer/Counter 2 Interrupt the IE SFR. This is done to ensure that the interrupt will always be responded to if a watchdog timeout occurs. The watchdog will only produce an interrupt TII 11 (Lowest) Time Interval Counter Interrupt if the watchdog timeout is greater than zero. –62– REV. A, ADuC834 HARDWARE DESIGN CONSIDERATIONS Though both external program memory and external data This section outlines some of the key hardware design consider- memory are accessed using some of the same pins, the two are ations that must be addressed when integrating the ADuC834 completely independent of each other from a software point of into any hardware system. view. For example, the chip can read/write external data memory External Memory Interface while executing from external program memory. In addition to its internal program and data memories, the Figure 59 shows a hardware configuration for accessing up to ADuC834 can access up to 64 Kbytes of external program memory 64 Kbytes of external data memory. This interface is standard (ROM/PROM/and so on) and up to 16 Mbytes of external data to any 8051 compatible MCU. memory (SRAM). To select from which code space (internal or external program ADuC834 SRAM memory) to begin executing code, tie the EA (external access) D0–D7P0 (DATA) pin high or low, respectively. When EA is high (pulled up to VDD), user program execution will start at Address 0 in the LATCH A0–A7 internal 62 Kbytes Flash/EE code space. When EA is low (tied ALE to ground) user program execution will start at Address 0 in the external code space. When executing from internal code space, P2 A8–A15 accesses to the program space above F7FFH (62 Kbytes) will be read as NOP instructions. RD OE Note that a second very important function of the EA pin is WR WE described in the Single Pin Emulation Mode section. External program memory (if used) must be connected to Figure 59. External Data Memory Interface the ADuC834 as illustrated in Figure 58. Sixteen I/O lines (64 Kbytes Address Space) (Ports 0 and 2) are dedicated to bus functions during external If access to more than 64 Kbytes of RAM is desired, a feature program memory fetches. Port 0 (P0) serves as a multiplexed unique to the MicroConverter allows addressing up to 16 Mbytes address/databus. It emits the low byte of the program counter of external RAM simply by adding an additional latch as illus- (PCL) as an address, and then goes into a high impedance input trated in Figure 60. state awaiting the arrival of the code byte from the program memory. During the time that the low byte of the program counter

SRAM

is valid on P0, the signal ALE (Address Latch Enable) clocks ADuC834 this byte into an external address latch. Meanwhile, Port 2 (P2) P0 D0–D7(DATA) emits the high byte of the program counter (PCH), and PSEN

LATCH

strobes the EPROM and the code byte is read into the ADuC834. A0–A7

ALE

ADuC834 EPROM P2 A8–A15 P0 D0–D7(INSTRUCTION)

LATCH

A16–A23 LATCH A0–A7

ALE

RD OE WR WE P2 A8–A15 Figure 60. External Data Memory Interface PSEN OE (16 Mbytes Address Space) In either implementation, Port 0 (P0) serves as a multiplexed Figure 58. External Program Memory Interface address/databus. It emits the low byte of the data pointer (DPL) Note that program memory addresses are always 16 bits wide, as an address, which is latched by ALE prior to data being placed even in cases where the actual amount of program memory used on the bus by the ADuC834 (write operation) or the external is less than 64 Kbytes. External program execution sacrifices two data memory (read operation). Port 2 (P2) provides the data of the 8-bit ports (P0 and P2) to the function of addressing the pointer page byte (DPP) to be latched by ALE, followed by the program memory. While executing from external program memory, data pointer high byte (DPH). If no latch is connected to P2, Ports 0 and 2 can be used simultaneously for read/write access DPP is ignored by the SRAM, and the 8051 standard of 64 Kbyte to external data memory, but not for general-purpose I/O. external data memory access is maintained. Detailed timing diagrams of external program and data memory read and write access can be found in the Timing Specification sections of this data sheet. REV. A –63–, Power Supplies Notice that in both Figure 61 and Figure 62 a large value (10 F) The ADuC834’s operational power supply voltage range is reservoir capacitor sits on DVDD and a separate 10 F capacitor 2.7 V to 5.25 V. Although the guaranteed data sheet specifica- sits on AVDD. Also, local decoupling capacitors (0.1 F) are tions are given only for power supplies within 2.7 V to 3.6 V or located at each VDD pin of the chip. As per standard design 5% of the nominal5Vlevel, the chip will function equally well practice, be sure to include all of these capacitors and ensure at any power supply level between 2.7 V and 5.25 V. the smaller capacitors are closest to each VDD pin with lead Separate analog and digital power supply pins (AV and DV lengths as short as possible. Connect the ground terminal ofDD DD respectively) allow AVDD to be kept relatively free of noisy digi- each of these capacitors directly to the underlying ground plane. tal signals often present on the system DV line. In this mode, Finally, it should also be noticed that, at all times, the analogDD the part can also operate with split supplies; that is, using differ- and digital ground pins on the ADuC834 should be referenced ent voltage supply levels for each supply. For example, this to the same system ground reference point. means that the system can be designed to operate with a DVDD Power-On Reset Operation voltage level of3Vwhile the AVDD level can be at 5 V, or vice- An internal POR (Power-On Reset) is implemented on the versa if required. A typical split supply configuration is shown in ADuC834. For DVDD below 2.45 V, the internal POR will hold Figure 61. the ADuC834 in reset. As DVDD rises above 2.45 V, an internal timer will time out for typically 128 ms before the part is DIGITAL SUPPLY ANALOG SUPPLY released from reset. The user must ensure that the power supply 10F 10F has reached a stable 2.7 V minimum level by this time. Likewise + + – – on power-down, the internal POR will hold the ADuC834 in ADuC834 20 reset until the power supply has dropped below 1 V. Figure 63 DV AV34 DD 5 illustrates the operation of the internal POR in detail.DD 0.1F 0.1F 2.45V TYP

DV

21 DD 1.0V TYP 128ms TYP 128ms TYP 1.0V TYP DGND AGND 635

INTERNAL

Figure 61. External Dual Supply Connections CORE RESET As an alternative to providing two separate power supplies, AVDD can be kept quiet by placing a small series resistor and/or Figure 63. Internal Power-on-Reset Operation ferrite bead between it and DVDD, and then decoupling AVDD Power Consumption separately to ground. An example of this configuration is shown The DVDD power supply current consumption is specified inin Figure 62. In this configuration, other analog circuitry (such normal, idle, and power-down modes. The AV power supply as op amps, voltage reference, and so on) can be powered from DDcurrent is specified with the analog peripherals disabled. The the AVDD supply line as well. normal mode power consumption represents the current drawn DIGITAL SUPPLY from DVDD by the digital core. The other on-chip peripherals (watchdog timer, power supply monitor, and so on) consume 10F + BEAD 1.6 10F – negligible current and are therefore lumped in with the normal ADuC834 operating current here. Of course, the user must add any cur- AV 5 rents sourced by the parallel and serial I/O pins, and those34 DVDD DD 0.1F sourced by the DAC in order to determine the total current 0.1F needed at the ADuC834’s DVDD and AVDD supply pins. Also, 21 current drawn from the DVDD supply will increase by approxi- 35 DGND mately 5 mA during Flash/EE erase and program cycles. 47 AGND 6 Figure 62. External Single Supply Connections –64– REV. A, Power Saving Modes Wake-Up from Power-Down Latency Setting the Idle and Power-Down Mode Bits, PCON.0 and Even with the 32 kHz crystal enabled during power-down, the PCON.1 respectively, in the PCON SFR described in Table II PLL will take some time to lock after a wake-up from power- allows the chip to be switched from Normal mode into Idle down. Typically, the PLL will take about 1 ms to lock. During mode, and also into full Power-Down mode. this time, code will execute but not at the specified frequency. In Idle mode, the oscillator continues to run, but the core clock Some operations require an accurate clock, for example UART generated from the PLL is halted. The on-chip peripherals communications, to achieve specified 50/60 Hz rejection from continue to receive the clock and remain functional. The CPU the ADCs. The following code may be used to wait for the PLL status is preserved with the stack pointer, program counter, and to lock: all other internal registers maintain their data during Idle mode. WAITFORLOCK: Port pins and DAC output pins also retain their states, and ALE MOV A, PLLCON and PSEN outputs go high in this mode. The chip will recover JNB ACC.6, WAITFORLOCK from Idle mode upon receiving any enabled interrupt, or on If the crystal has been powered down during power-down, there receiving a hardware reset. is an additional delay associated with the startup of the crystal In Power-Down mode, both the PLL and the clock to the core are oscillator before the PLL can lock. 32 kHz crystals are inherently stopped. The on-chip oscillator can be halted or can continue to slow to oscillate, typically taking about 150 ms. Once again, during oscillate, depending on the state of the oscillator power-down this time before lock, code will execute but the exact frequency bit (OSC_PD) in the PLLCON SFR. The TIC, being driven of the clock cannot be guaranteed. Again for any timing sensitive directly from the oscillator, can also be enabled during power- operations, it is recommended to wait for lock using the lock bit down. All other on-chip peripherals however, are shut down. Port in PLLCON as shown above. pins retain their logic levels in this mode, but the DAC output Grounding and Board Layout Recommendations goes to a high impedance state (three-state) while ALE and PSEN As with all high resolution data converters, special attention must outputs are held low. During full Power-Down mode with the be paid to grounding and PC board layout of ADuC834-based oscillator and wake-up timer running, the ADuC834 typically designs in order to achieve optimum performance from the consumes a total of 15 A. There are five ways of terminating ADCs and DAC. Power-Down mode: Although the ADuC834 has separate pins for analog and digital Asserting the RESET Pin (Pin 15) ground (AGND and DGND), the user must not tie these to two Returns to Normal Mode. All registers are set to their reset separate ground planes unless the two ground planes are con- default value and program execution starts at the reset vector nected together very close to the ADuC834, as illustrated in the once the RESET pin is deasserted. simplified example of Figure 64a. In systems where digital and Cycling Power analog ground planes are connected together somewhere else All registers are set to their default state and program execution (at the system’s power supply for example), they cannot be starts at the reset vector approximately 128 ms later. connected again near the ADuC834 since a ground loop would Time Interval Counter (TIC) Interrupt result. In these cases, tie the ADuC834’s AGND and DGND If the OSC_PD bit in the PLLCON SFR is clear, the 32 kHz Pins all to the analog ground plane, as illustrated in Figure 64b. oscillator will remain powered up even in Power-Down mode. If In systems with only one ground plane, ensure that the digital the Time Interval Counter (Wakeup/RTC timer) is enabled, and analog components are physically separated onto separate a TIC interrupt will wake the ADuC834 up from Power-Down halves of the board such that digital return currents do not flow mode. The CPU services the TIC interrupt. The RETI at the near analog circuitry and vice versa. The ADuC834 can then be end of the TIC ISR will return the core to the instruction after placed between the digital and analog sections, as illustrated in that which enabled power-down. Figure 64c. SPI Interrupt In all of these scenarios, and in more complicated real-life appli- If the SERIPD Bit in the PCON SFR is set, then an SPI inter- cations, keep in mind the flow of current from the supplies and rupt, if enabled, will wake the ADuC834 up from Power-Down back to ground. Make sure the return paths for all currents are mode. The CPU services the SPI interrupt. The RETI at the as close as possible to the paths the currents took to reach their end of the ISR will return the core to the instruction after that destinations. For example, do not power components on the which enabled power-down. analog side of Figure 64b with DVDD since that would force return currents from DVDD to flow through AGND. Also, try to avoid INT0 Interrupt digital currents flowing under analog circuitry, which could happen If the INT0PD bit in the PCON SFR is set, an external if the user placed a noisy digital chip on the left half of the board interrupt 0, if enabled, will wake up the ADuC834 from power- in Figure 64c. Whenever possible, avoid large discontinuities in down. The CPU services the SPI interrupt. The RETI at the end the ground plane(s) (such as are formed by a long trace on the of the ISR will return the core to the instruction after that which same layer), since they force return signals to travel a longer path. enabled power-down. And of course, make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground. REV. A –65–, The CHIPID SFR is a read-only register located at SFR address C2H. The upper nibble of this SFR designates the PLACE ANALOG PLACE DIGITAL MicroConverter within the Σ-∆ ADC family. User software can a. COMPONENTS COMPONENTS read this SFR to identify the host MicroConverter and thus HERE HERE execute slightly different code if required. The CHIPID SFR reads AGND DGND as follows for the Σ-∆ ADC family of MicroConverter products. ADuC836 CHIPID = 3xH ADuC834 CHIPID = 2xH ADuC824 CHIPID = 0xH ADuC816 CHIPID = 1xH PLACE ANALOG PLACE DIGITAL Clock Oscillatorb. COMPONENTS COMPONENTS As described earlier, the core clock frequency for the ADuC834 HERE HERE is generated from an on-chip PLL that locks onto a multiple AGND DGND (384 times) of 32.768 kHz. The latter is generated from an internal clock oscillator. To use the internal clock oscillator, connect a 32.768 kHz parallel resonant crystal between XTAL1 and XTAL2 pins (32 and 33) as shown in Figure 65. As shown in the typical external crystal connection diagram in Figure 65, two internal 12 pF capacitors are provided on-chip. c. PLACE ANALOG PLACE DIGITALCOMPONENTS COMPONENTS These are connected internally, directly to the XTAL1 and HERE HERE XTAL2 pins, and the total input capacitances at both pins is GND detailed in the Specification section of this data sheet. The value of the total load capacitance required for the external crystal should be the value recommended by the crystal manufacturer Figure 64. System Grounding Schemes for use with that specific crystal. In many cases, because of the If the user plans to connect fast logic signals (rise/fall time < 5 ns) on-chip capacitors, additional external load capacitors will not to any of the ADuC834’s digital inputs, add a series resistor to be required. each relevant line to keep rise and fall times longer than 5 ns at the ADuC834 input pins. A value of 100 Ω or 200 Ω is usually ADuC834 sufficient to prevent high speed signals from coupling capaci- XTAL1 tively into the ADuC834 and affecting the accuracy of ADC 32.768kHz 12pF conversions. ADuC834 System Self-Identification 33 TO INTERNALPLL In some hardware designs, it may be an advantage for the XTAL2 12pF software running on the ADuC834 target to identify the host MicroConverter. For example, code running on the ADuC834 Figure 65. External Parallel Resonant Crystal may also be used with the ADuC824 or the ADuC816, and is Connections Other Hardware Considerations required to operate differently. To facilitate in-circuit programming, plus in-circuit debug and emulation options, users will want to implement some simple connection points in their hardware that will allow easy access to Download, Debug, and Emulation modes. –66– REV. A, OTHER HARDWARE CONSIDERATIONS Embedded Serial Port Debugger In-Circuit Serial Download Access From a hardware perspective, entry to Serial Port Debug mode Nearly all ADuC834 designs will want to take advantage of the is identical to the serial download entry sequence described in-circuit reprogrammability of the chip. This is accomplished above. In fact, both Serial Download and Serial Port Debug by a connection to the ADuC834’s UART, which requires an modes can be thought of as essentially one mode of operation external RS-232 chip for level translation if downloading code used in two different ways. from a PC. Basic configuration of an RS-232 connection is Note that the serial port debugger is fully contained on the illustrated in Figure 66 with a simple ADM3202-based circuit. ADuC834 device, (unlike “ROM monitor” type debuggers) and If users would rather not include an RS-232 chip onto the target therefore no external memory is needed to enable in-system board, refer to the application note uC006–A 4-Wire UART-to-PC debug sessions. Interface available at www.analog.com/microconverter, for a simple (and zero-cost-per-board) method of gaining in-circuit Single-Pin Emulation Mode serial download access to the ADuC834. Also built into the ADuC834 is a dedicated controller for single- pin in-circuit emulation (ICE) using standard production ADuC834 In addition to the basic UART connections, users will also need devices. In this mode, emulation access is gained by connection a way to trigger the chip into Download mode. This is accom- to a single pin, the EA pin. Normally, this pin is hard-wired plished viaa1kΩ pull-down resistor that can be jumpered onto either high or low to select execution from internal or external the PSEN pin, as shown in Figure 66. To get the ADuC834 into program memory space, as described earlier. To enable single-pin Download mode, simply connect this jumper and power-cycle emulation mode, however, users will need to pull the EA pin the device (or manually reset the device, if a manual reset button high througha1kΩ resistor as shown in Figure 66. The emulator is available) and it will be ready to receive a new program serially. will then connect to the 2-pin header also shown in Figure 66. With the jumper removed, the device will power-on in Normal To be compatible with the standard connector that comes mode (and run the program) whenever power is cycled or RESET with the single-pin emulator available from Accutron Limited is toggled. (www.accutron.com), use a 2-pin 0.1-inch pitch Friction Lock Note that PSEN is normally an output (as described in the header from Molex (www.molex.com) such as their part number External Memory Interface section) and it is sampled as an input 22-27-2021. Be sure to observe the polarity of this header. As only on the falling edge of RESET (i.e., at power-up or upon an represented in Figure 66, when the Friction Lock tab is at the external manual reset). Note also that if any external circuitry right, the ground pin should be the lower of the two pins (when unintentionally pulls PSEN low during power-up or reset events, viewed from the top). it could cause the chip to enter Download Mode and therefore fail to begin user code execution as it should. To prevent this, ensure that no external signals are capable of pulling the PSEN pin low, except for the external PSEN jumper itself. REV. A –67–, Typical System Configuration resistance. This differential voltage is routed directly to the positive A typical ADuC834 configuration is shown in Figure 66. It and negative inputs of the primary ADC (AIN1, AIN2 respec- summarizes some of the hardware considerations discussed in tively). The same current that excited the RTD also flows through the previous paragraphs. a series resistance RREF generating a ratiometric voltage reference Figure 66 also includes connections for a typical analog measure- VREF. The ratiometric voltage reference ensures that variations ment application of the ADuC834, namely an interface to an in the excitation current do not affect the measurement system as RTD (Resistive Temperature Device). The arrangement shown the input voltage from the RTD and reference voltage across is commonly referred to as a 4-wire RTD configuration. RREF vary ratiometrically with the excitation current. Resistor RREF must, however, have a low temperature coefficient to avoid Here, the on-chip excitation current sources are enabled to excite errors in the reference voltage over temperature. RREF must the sensor. The excitation current flows directly through the also be large enough to generate at leasta1Vvoltage reference. RTD generating a voltage across the RTD proportional to its DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) DVDD 1k DVDD 1k 2-PIN HEADER FOR EMULATION ACCESS 52 51 50 49 48 47 46 45 44 43 42 41 40 (NORMALLY OPEN) 200A/400A P1.2/IEXC1/DAC 37 EXCITATION AVDD P1.3/AIN5/DAC 36 DVDD

CURRENT

AVDD DGND 35 AGND ADuC834 DVDD 34 RTD REFIN– XTAL2 33 REFIN+ XTAL1 32 RREF P1.4/AIN1 31 32.768kHz 5.6k P1.5/AIN2 30 NOT CONNECTED IN THIS EXAMPLE

DV

DV DDDD ALL CAPACITORS IN THIS EXAMPLE ARE0.1F CERAMIC CAPACITORS RS-232 INTERFACE* STANDARD D-TYPE ADM3202 SERIAL COMMS CONNECTOR TO C1+ VCC PC HOST V+ GND 1 C1– T1OUT 2 C2+ R1IN 3 C2– R1OUT 4 V– T1IN 5 T2OUT T2IN 6 R2IN R2OUT 7 *EXTERNAL UART TRANSCEIVER INTEGRATED IN SYSTEM OR AS PART OF AN EXTERNAL DONGLE AS DESCRIBED IN uC006.

Figure 66. Typical System Configuration

–68– REV. A

RESET RXD TXD DVDD DGND DVDD DGND PSEN EA

, QUICKSTART DEVELOPMENT SYSTEM Download—In Circuit Downloader The QuickStart Development System is a full featured, low cost The Serial Downloader is a software program that allows the user development tool suite supporting the ADuC834. The system to serially download an assembled program (Intel Hex format consists of the following PC-based (Windows® compatible) file) to the on-chip program FLASH memory via the serial COM1 hardware and software development tools. port on a standard PC. An Application Note (uC004) detailing Hardware: ADuC834 Evaluation Board, this serial download protocol is available from www.analog.com/ and Serial Port Cable microconverter. Code Development: 8051 Assembler Debugger/Emulator—In-Circuit Debugger/Emulator The Debugger/Emulator is a Windows application that allows the Code Functionality: ADSIM, Windows user to debug code execution on silicon using the MicroConverter MicroConverter Code UART serial port or via a single pin to provide non intrusive Simulator debug. The debugger provides access to all on-chip peripherals In-Circuit Code Download: Serial Downloader during a typical debug session, including single-step and mul- In-Circuit Debugger/Emulator: Serial Port/Single Pin tiple break-point code execution control. C source and assembly Debugger/Emulator with level debug are both possible with the emulator. Assembly and C Source ADSIM—Windows Simulator debug The Simulator is a Windows application that fully simulates the Miscellaneous Other: CD-ROM Documentation MicroConverter functionality including ADC and DAC periph- and Two Additional erals. The simulator provides an easy-to-use, intuitive, interface to Prototype Devices the MicroConverter functionality and integrates many standard debug features, including multiple breakpoints, single stepping, Figures 67 shows the typical components of a QuickStart Devel- and code execution trace capability. This tool can be used both opment System while Figure 68 shows a typical debug session. as a tutorial guide to the part as well as an efficient way to prove A brief description of some of the software tools’ components in code functionality before moving to a hardware platform. the QuickStart Development System is given below. Figure 68. Typical Debug Session Figure 67. Components of the QuickStart Development System REV. A –69–, TIMING SPECIFICATIONS1, 2, 3 (AVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V, DVDD = 2.7 V to 3.6 V or 4.75 V to 5.25 V;all specifications TMIN to TMAX, unless otherwise noted.) 32.768 kHz External Crystal

Parameter Min Typ Max Unit Figure CLOCK INPUT (External Clock Driven XTAL1)

tCK XTAL1 Period 30.52 s 69 tCKL XTAL1 Width Low 6.26 s 69 tCKH XTAL1 Width High 6.26 s 69 tCKR XTAL1 Rise Time9s69 tCKF XTAL1 Fall Time9s69 1/t ADuC834 Core Clock Frequency4CORE 0.098 12.58 MHz tCORE ADuC834 Core Clock Period5 0.636 s tCYC ADuC834 Machine Cycle Time6 0.95 7.6 122.45 s

NOTES

1AC inputs during testing are driven at DVDD – 0.5 V for a Logic 1, and 0.45 V for a Logic 0. Timing measurements are made at V IH min for a Logic 1, and VIL max for a Logic 0 as shown in Figure 70. 2For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs as shown in Figure 70. 3CLOAD for Port0, ALE, PSEN outputs = 100 pF; CLOAD for all other outputs = 80 pF unless otherwise noted. 4ADuC834 internal PLL locks onto a multiple (384 times) the external crystal frequency of 32.768 kHz to provide a stable 12.583 MHz internal clock for the system. The core can operate at this frequency or at a binary submultiple called Core_Clk, selected via the PLLCON SFR. 5This number is measured at the default Core_Clk operating frequency of 1.57 MHz. 6ADuC834 Machine Cycle Time is nominally defined as 12/Core_Clk. t tCKH CKR tCKL tCKF tCK

Figure 69. XTAL1 Input

DVDD – 0.5V 0.2DV + 0.9V VLOAD – 0.1V VLOAD – 0.1VDD TIMING TEST POINTS VLOAD REFERENCE VLOAD 0.2DVDD – 0.1V V + 0.1V POINTS 0.45V LOAD VLOAD + 0.1V

Figure 70. Timing Waveform Characteristics

–70– REV. A, 12.58 MHz Core_Clk Variable Core_Clk Parameter Min Max Min Max Unit Figure EXTERNAL PROGRAM MEMORY tLHLL ALE Pulsewidth 119 2tCORE – 40 ns 71 tAVLL Address Valid to ALE Low 39 tCORE – 40 ns 71 tLLAX Address Hold after ALE Low 49 tCORE – 30 ns 71 tLLIV ALE Low to Valid Instruction In 218 4tCORE – 100 ns 71 tLLPL ALE Low to PSEN Low 49 tCORE – 30 ns 71 tPLPH PSEN Pulsewidth 193 3tCORE – 45 ns 71 tPLIV PSEN Low to Valid Instruction In 133 3tCORE – 105 ns 71 tPXIX Input Instruction Hold after PSEN00ns 71 tPXIZ Input Instruction Float after PSEN 54 tCORE – 25 ns 71 tAVIV Address to Valid Instruction In 292 5tCORE – 105 ns 71 tPLAZ PSEN Low to Address Float 25 25 ns 71 tPHAX Address Hold after PSEN High00ns 71 CORE_CLK tLHLL ALE (O) t tAVLL tLLPL PLPH tLLIV tPLIV PSEN (O) t t PXIZ t PLAZLLAX tPXIX PORT 0 (I/O) PCL INSTRUCTION(OUT) (IN) tAVIV tPHAX PORT 2 (O) PCH

Figure 71. External Program Memory Read Cycle REV. A –71–

, 12.58 MHz Core_Clk Variable Core_Clk Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY READ CYCLE tRLRH RD Pulsewidth 377 6tCORE – 100 ns 72 tAVLL Address Valid after ALE Low 39 tCORE – 40 ns 72 tLLAX Address Hold after ALE Low 44 tCORE – 35 ns 72 tRLDV RD Low to Valid Data In 232 5tCORE – 165 ns 72 tRHDX Data and Address Hold after RD00ns 72 tRHDZ Data Float after RD 89 2tCORE – 70 ns 72 tLLDV ALE Low to Valid Data In 486 8tCORE – 150 ns 72 tAVDV Address to Valid Data In 550 9tCORE – 165 ns 72 tLLWL ALE Low to RD Low 188 288 3tCORE – 50 3tCORE + 50 ns 72 tAVWL Address Valid to RD Low 188 4tCORE – 130 ns 72 tRLAZ RD Low to Address Float00ns 72 tWHLH RD High to ALE High 39 119 tCORE – 40 tCORE + 40 ns 72 CORE_CLK ALE (O) tWHLH PSEN (O) tLLDV tLLWL tRLRH RD (O) tAVWL tRLDVttRHDZ t LLAX tRHDXAVLL tRLAZ A0–A7 PORT 0 (I/O) (OUT) DATA (IN) tAVDV PORT 2 (O) A16–A23 A8–A15

Figure 72. External Data Memory Read Cycle

–72– REV. A, 12.58 MHz Core_Clk Variable Core_Clk Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY WRITE CYCLE tWLWH WR Pulsewidth 377 6tCORE – 100 ns 73 tAVLL Address Valid after ALE Low 39 tCORE – 40 ns 73 tLLAX Address Hold after ALE Low 44 tCORE – 35 ns 73 tLLWL ALE Low to WR Low 188 288 3tCORE – 50 3tCORE + 50 ns 73 tAVWL Address Valid to WR Low 188 4tCORE – 130 ns 73 tQVWX Data Valid to WR Transition 29 tCORE – 50 ns 73 tQVWH Data Setup before WR 406 7tCORE – 150 ns 73 tWHQX Data and Address Hold after WR 29 tCORE – 50 ns 73 tWHLH WR High to ALE High 39 119 tCORE – 40 tCORE + 40 ns 73 CORE_CLK ALE (O) tWHLH PSEN (O) tLLWL tWLWH WR (O) tAVWL tQVWXttWHQX t LLAXAVLL tQVWH PORT 0 (O) A0–A7 DATA PORT 2 (O) A16–A23 A8–A15 Figure 73. External Data Memory Write Cycle REV. A –73–, 12.58 MHz Core_Clk Variable Core_Clk Parameter Min Typ Max Min Typ Max Unit Figure UART TIMING (Shift Register Mode) tXLXL Serial Port Clock Cycle Time 0.95 12tCORE s 74 tQVXH Output Data Setup to Clock 662 10tCORE – 133 ns 74 tDVXH Input Data Setup to Clock 292 2tCORE + 133 ns 74 tXHDX Input Data Hold after Clock00ns 74 tXHQX Output Data Hold after Clock 42 2tCORE – 117 ns 74 ALE (O) tXLXL TxD (OUTPUT CLOCK) 01 67 SET RI tQVXH OR t SET TIXHQX RxD (OUTPUT DATA) MSB BIT 6 BIT 1 tDVXH tXHDX RxD (INPUT DATA) MSB BIT 6 BIT 1 LSB

Figure 74. UART Timing in Shift Register Mode

–74– REV. A, Parameter Min Typ Max Unit Figure SPI MASTER MODE TIMING (CPHA = 1) tSL SCLOCK Low Pulsewidth* 630 ns 75 tSH SCLOCK High Pulsewidth* 630 ns 75 tDAV Data Output Valid after SCLOCK Edge 50 ns 75 tDSU Data Input Setup Time before SCLOCK Edge 100 ns 75 tDHD Data Input Hold Time after SCLOCK Edge 100 ns 75 tDF Data Output Fall Time 10 25 ns 75 tDR Data Output Rise Time 10 25 ns 75 tSR SCLOCK Rise Time 10 25 ns 75 tSF SCLOCK Fall Time 10 25 ns 75 *Characterized under the following conditions: Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, i.e., core clock frequency = 1.57 MHz, and SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.

SCLOCK

(CPOL = 0) tSH tSLttSCLOCK SR SF (CPOL = 1) tDAV tDOSU tDF tDR

MOSI

MSB BITS 6–1 LSB MISO MSB IN BITS 6–1 LSB IN tDSU tDHD

Figure 75. SPI Master Mode Timing (CPHA = 1) REV. A –75–

, Parameter Min Typ Max Unit Figure SPI MASTER MODE TIMING (CPHA = 0) tSL SCLOCK Low Pulsewidth* 630 ns 76 tSH SCLOCK High Pulsewidth* 630 ns 76 tDAV Data Output Valid after SCLOCK Edge 50 ns 76 tDOSU Data Output Setup before SCLOCK Edge 150 ns 76 tDSU Data Input Setup Time before SCLOCK Edge 100 ns 76 tDHD Data Input Hold Time after SCLOCK Edge 100 ns 76 tDF Data Output Fall Time 10 25 ns 76 tDR Data Output Rise Time 10 25 ns 76 tSR SCLOCK Rise Time 10 25 ns 76 tSF SCLOCK Fall Time 10 25 ns 76 *Characterized under the following conditions: a. Core clock divider bits CD2, CD1 and CD0 in PLLCON SFR set to 0, 1, and 1 respectively, i.e., core clock frequency = 1.57 MHz, and b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0 respectively.

SCLOCK

(CPOL = 0) tSH tSL t SCLOCK SR tSF (CPOL = 1) tDAV tDF tDR

MOSI

MSB BITS 6–1 LSB MISO MSB IN BITS 6–1 LSB IN tDSU tDHD

Figure 76. SPI Master Mode Timing (CPHA = 0)

–76– REV. A, Parameter Min Typ Max Unit Figure SPI SLAVE MODE TIMING (CPHA = 1) tSS SS to SCLOCK Edge 0 ns 77 tSL SCLOCK Low Pulsewidth 330 ns 77 tSH SCLOCK High Pulsewidth 330 ns 77 tDAV Data Output Valid after SCLOCK Edge 50 ns 77 tDSU Data Input Setup Time before SCLOCK Edge 100 ns 77 tDHD Data Input Hold Time after SCLOCK Edge 100 ns 77 tDF Data Output Fall Time 10 25 ns 77 tDR Data Output Rise Time 10 25 ns 77 tSR SCLOCK Rise Time 10 25 ns 75 tSF SCLOCK Fall Time 10 25 ns 77 tSFS SS High after SCLOCK Edge 0 ns 77

SS

tSS tSFS

SCLOCK

(CPOL = 0) t tSH SL tSR tSF

SCLOCK

(CPOL = 1) tDAV tDF tDR MISO MSB BITS 6–1 LSB MOSI MSB IN BITS 6–1 LSB IN tDSU tDHD

Figure 77. SPI Slave Mode Timing (CPHA = 1) REV. A –77–

, Parameter Min Typ Max Unit Figure SPI SLAVE MODE TIMING (CPHA = 0) tSS SS to SCLOCK Edge 0 ns 78 tSL SCLOCK Low Pulsewidth 330 ns 78 tSH SCLOCK High Pulsewidth 330 ns 78 tDAV Data Output Valid after SCLOCK Edge 50 ns 78 tDSU Data Input Setup Time before SCLOCK Edge 100 ns 78 tDHD Data Input Hold Time after SCLOCK Edge 100 ns 78 tDF Data Output Fall Time 10 25 ns 78 tDR Data Output Rise Time 10 25 ns 78 tSR SCLOCK Rise Time 10 25 ns 78 tSF SCLOCK Fall Time 10 25 ns 78 tSSR SS to SCLOCK Edge 50 ns 78 tDOSS Data Output Valid after SS Edge 20 ns 78 tSFS SS High after SCLOCK Edge 0 ns 78

SS

t tSS SFS

SCLOCK

(CPOL = 0) tSH tSL tSR tSF

SCLOCK

(CPOL = 1) tDAV tDOSS tDF tDR MISO MSB BITS 6–1 LSB MOSI MSB IN BITS 6–1 LSB IN tDSU tDHD Figure 78. SPI Slave Mode Timing (CPHA = 0) –78– REV. A, Parameter Min Max Unit Figure I2C-SERIAL INTERFACE TIMING tL SCLOCK Low Pulsewidth 4.7 µs 79 tH SCLOCK High Pulsewidth 4.0 µs 79 tSHD Start Condition Hold Time 0.6 µs 79 tDSU Data Setup Time 100 ns 79 tDHD Data Hold Time 0.9 µs 79 tRSU Setup Time for Repeated Start 0.6 µs 79 tPSU Stop Condition Setup Time 0.6 µs 79 tBUF Bus Free Time between a STOP 1.3 µs 79 Condition and a START Condition tR Rise Time of Both SCLOCK and SDATA 300 ns 79 tF Fall Time of Both SCLOCK and SDATA 300 ns 79 tSUP* Pulsewidth of Spike Suppressed 50 ns 79 *Input filtering on both the SCLOCK and SDATA inputs surpresses noise spikes less than 50 ns. tBUF tSUP tR SDATA (I/O) MSB LSB ACK MSB tDSU tDSU tt FtDHD DHDtttR PSU tSHD tH RSU SCLK (I) 1 2-7891tPS L tSUP S(R) tF STOP START REPEATED CONDITION CONDITION START

Figure 79. I2C Compatible Interface Timing REV. A –79–

,

OUTLINE DIMENSIONS

52-Lead Metric Quad Flat Package [MQFP] (S-52) Dimensions shown in millimeters 14.15 1.03 13.90 SQ 0.88 2.45 13.65

MAX

0.73 39 27 SEATING 40 26

PLANE

7.80 10.20TOP VIEW REF (PINS DOWN) 10.00 SQ 9.80 VIEW A PIN 1 52 14 1 13 0.23 0.65 BSC 0.38 0.11 0.22 2.10 2.00 7 1.95 0.10 MIN VIEW A COPLANARITY ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MO-022-AC-1 56-Lead Lead Frame Chip Scale Package [LFCSP] 8 8 mm Body (CP-56) Dimensions shown in millimeters 0.30 8.00 0.60 MAX 0.23 BSC SQ 0.60 MAX 0.18 PIN 1INDICATOR 43 56 1 PIN 1

INDICATOR

7.75 6.25 TOP BSC SQ BOTTOM 6.10 SQ VIEW VIEW 5.95 0.50 0.40 29 15 14 0.30 28 6.50 0.70 MAX REF 1.00 12 MAX 0.65 NOM 0.90 0.80 0.05 MAX 0.02 NOM 0.20 0.50 BSC COPLANARITY REF SEATING 0.08

PLANE

COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2

Revision History Location Page

4/03—Data Sheet changed from REV. 0 to REV. A. Updated OUTLINE DIMENSIONS .80 –80– REV. A C02942–0–4/03(A)]

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