Download: a MicroConverter 12-Bit ADC with Embedded FLASH MCU ADuC812

a MicroConverter ®, Multichannel 12-Bit ADC with Embedded FLASH MCU

ADuC812

FEATURES APPLICATIONS Analog I/O Intelligent Sensors Calibration and Conditioning 8-Channel, High Accuracy 12-Bit ADC Battery Powered Systems (Portable PCs, Instruments, On-Chip, 100 ppm/C Voltage Reference Monitors) High-Speed 200 kSPS Transient Capture Systems DMA Controller for High-Speed ADC-to-RAM Capture DAS and Communications Systems Two 12-Bit Voltage Output DACs Control Loop Monitors (Optical Networks/Base Stations) On-Chip Temperature Sensor Function Memory GENERAL DESCRIPTION 8K Bytes On-Chip Flash/EE Program Memory The ADuC812 is a fully integrated 12-bit data acquisition system 640 Bytes On-Chip Flash/EE Data Memory incorporating a high performance self calibrating multichannel 256 Bytes On-Chip Data RAM ADC, dual DAC and programmable 8-bit MCU (8051 instruc- 16M Bytes External Data Address Space tion set compatible) on a single chip. 64K Bytes External Program Address Space The programmable 8051-compatible core is supported by 8K 8051-Compatible Core bytes Flash/EE program memory, 640 bytes Flash/EE data 12 MHz Nominal Operation (16 MHz Max) memory and 256 bytes data SRAM on-chip. Three 16-Bit Timer/Counters Additional MCU support functions include Watchdog Timer, High Current Drive Capability—Port 3 Power Supply Monitor and ADC DMA functions. 32 Pro- Nine Interrupt Sources, Two Priority Levels grammable I/O lines, SPI and Standard UART Serial Port I/O Power are provided for multiprocessor interfaces and I/O expansion. Specified for3Vand5VOperation Normal, Idle, and Power-Down Modes Normal, idle, and power-down operating modes for both the On-Chip Peripherals MCU core and analog converters allow for flexible power man- UART and SPI® Serial I/O agement schemes suited to low power applications. The part is Watchdog Timer specified for3Vand5Voperation over the industrial tem- Power Supply Monitor perature range and is available in a 52-lead, plastic quad flatpack package. FUNCTIONAL BLOCK DIAGRAM P0.0–P0.7 P1.0–P1.7 P2.0–P2.7 P3.0–P3.7 ADC DAC0 BUF DAC0 AIN0 (P1.0)–AIN7 (P1.7) 12-BIT AIN T/H SUCCESSIVE CONTROL DAC MUX APPROXIMATION AND CONTROL ADC CALIBRATIONLOGIC DAC1 BUF DAC1 T0 (P3.4) MICROCONTROLLER T1 (P3.5) 8051 BASED POWER SUPPLY 3 16-BIT T2 (P1.0) 2.5V TEMP MICROCONTROLLER CORE MONITOR TIMER/COUNTERS T2EX (P1.1) REF SENSOR 8K 8 PROGRAM WATCHDOG INT0 (P3.2) FLASH EEPROM TIMER SPI INT1 (P3.3) V 640 8 USERBUF UART MUX ALEREF FLASH EEPROM

PSEN

256 8 USER ADuC812 RAM OSC EA CREF RESET AVDD AGND DVDD DGND XTAL1 XTAL2 RxD TxD SCLOCK MOSI MISO (P3.0) (P3.1) /D0 /D1 (P3.3) MicroConverter is a registered trademark of Analog Devices, Inc. SPI is a registered trademark of Motorola Inc.

REV. C

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002, TABLE OF CONTENTS FEATURES .1 POWER SUPPLY MONITOR .24 GENERAL DESCRIPTION .1 SERIAL PERIPHERAL INTERFACE .25 SPECIFICATIONS .3 MISO (Master In, Slave Out Data I/O Pin), Pin #19 .25 ABSOLUTE MAXIMUM RATINGS .6 MOSI (Master Out, Slave In Pin), Pin #27 .26 ORDERING GUIDE .6 SCLOCK (Serial Clock I/O Pin), Pin #26 .26 PIN FUNCTION DISCRIPTIONS .7 SS (Slave Select Input Pin), Pin #12 .26 TERMINOLOGY .8 Using the SPI Interface .27 ADC SPECIFICATIONS .8 SPI Interface—Master Mode .27 Integral Nonlinearity .8 SPI Interface—Slave Mode .27 Differential Nonlinearity .8 INTERFACE TO D0 AND D1 DIGITAL OUTPUTS .27 Offset Error .8 8051-COMPATIBLE ON-CHIP PERIPHERALS .28 Full-Scale Error .8 Parallel I/O Ports 0–3 .28 Signal to (Noise + Distortion) Ratio .8 Timers/Counters .28 Total Harmonic Distortion .8 Timer/Counter 0 and 1 Data Registers .30 DAC SPECIFICATIONS .8 TH0 and TL0 .30 Relative Accuracy .8 TH1 and TL1 .30 Voltage Output Settling Time .8 TIMER/COUNTER 0 AND 1 OPERATING MODES .31 Digital-to-Analog Glitch Impulse .8 Mode 0 (13-Bit Timer/Counter) .31 ARCHITECTURE, MAIN FEATURES .9 Mode 1 (16-Bit Timer/Counter) .31 MEMORY ORGANIZATION .9 Mode 2 (8-Bit Timer/Counter with Auto Reload) .31 OVERVIEW OF MCU-RELATED SFRs .10 Mode 3 (Two 8-Bit Timer/Counters) .31 Accumulator SFR .10 Timer/Counter 2 Data Registers .32 B SFR .10 TH2 and TL2 .32 Stack Pointer SFR .10 RCAP2H and RCAP2L .32 Data Pointer .10 Timer/Counter Operation Modes .33 Program Status Word SFR .10 16-Bit Autoreload Mode .33 Power Control SFR .10 16-Bit Capture Mode .33 SPECIAL FUNCTION REGISTERS .11 UART SERIAL INTERFACE .34 ADC CIRCUIT INFORMATION .12 Mode 0: 8-Bit Shift Register Mode .35 General Overview .12 Mode 1: 8-Bit UART, Variable Baud Rate .35 ADC Transfer Function .12 Mode 2: 9-Bit UART with Fixed Baud Rate .35 Typical Operation .12 Mode 3: 9-Bit UART with Variable Baud Rate .35 ADCCON1—(ADC Control SFR #1) .13 UART Serial Port Baud Rate Generation .35 ADCCON2—(ADC Control SFR #2) .14 Timer 1 Generated Baud Rates .36 ADCCON3—(ADC Control SFR #3) .14 Timer 2 Generated Baud Rates .36 Driving the A/D Converter .15 INTERRUPT SYSTEM .37 Voltage Reference Connections .16 Interrupt Priority .38 Configuring the ADC .16 Interrupt Vectors .38 ADC DMA Mode .16 ADuC812 HARDWARE DESIGN CONSIDERATIONS .39 DMA Mode Configuration Example .17 Clock Oscillator .39 Micro Operation during ADC DMA Mode .17 External Memory Interface .39 The Offset and Gain Calibration Coefficients .17 Power-On Reset Operation .40 Calibration .18 Power Supplies .40 NONVOLATILE FLASH MEMORY .18 Power Consumption .41 Flash Memory Overview .18 Grounding and Board Layout Recommendations .42 Flash/EE Memory and the ADuC812 .18 OTHER HARDWARE CONSIDERATIONS .43 ADuC812 Flash/EE Memory Reliability .18 In-Circuit Serial Download Access .43 Using the Flash/EE Program Memory .19 Embedded Serial Port Debugger .43 Using the Flash/EE Data Memory .19 Single-Pin Emulation Mode .44 ECON—Flash/EE Memory Control SFR .20 Enhanced-Hooks Emulation Mode .44 Flash/EE Memory Timing .20 Typical System Configuration .44 Using the Flash/EE Memory Interface .20 QUICKSTART DEVELOPMENT SYSTEM .44 Erase-All .20 Download—In-Circuit Serial Downloader .44 Program a Byte .20 DeBug—In-Circuit Debugger .44 USER INTERFACE TO OTHER ON-CHIP ADSIM—Windows Simulator .44 ADuC812 PERIPHERALS .21 TIMING SPECIFICATIONS .45 Using the D/A Converter .22 OUTLINE DIMENSIONS .54 WATCHDOG TIMER .24 Revision History .55 –2– REV. C,

SPECIFICATIONS1, 2 (AVDD = DVDD = 3.0 V or 5.0 V 10%, REFIN/REFOUT = 2.5 V Internal Reference, MCLKIN = 11.0592 MHz,

fSAMPLE = 200 kHz, DAC VOUT Load to AGND; RL = 2 k, CL = 100 pF. All specifications TA = TMIN to TMAX, unless otherwise noted.) ADuC812BS Parameter VDD = 5 V VDD = 3 V Unit Test Conditions/Comments ADC CHANNEL SPECIFICATIONS DC ACCURACY3, 4 Resolution 12 12 Bits Integral Nonlinearity ±1/2 ±1/2 LSB typ fSAMPLE = 100 kHz ±1.5 ±1.5 LSB max fSAMPLE = 100 kHz ±1.5 ±1.5 LSB typ fSAMPLE = 200 kHz Differential Nonlinearity ±1 ±1 LSB typ fSAMPLE = 100 kHz. Guaranteed No Missing Codes at5VCALIBRATED ENDPOINT ERRORS5, 6 Offset Error ±5 ±5 LSB max ±1 ±1 LSB typ Offset Error Match11LSB typ Gain Error ±6 ±6 LSB max ±1 ±1 LSB typ Gain Error Match 1.5 1.5 LSB typ USER SYSTEM CALIBRATION7 Offset Calibration Range ±5 ±5 % of VREF typ Gain Calibration Range ±2.5 ±2.5 % of VREF typ DYNAMIC PERFORMANCE fIN = 10 kHz Sine Wave fSAMPLE = 100 kHz Signal-to-Noise Ratio (SNR)8 70 70 dB typ Total Harmonic Distortion (THD) –78 –78 dB typ Peak Harmonic or Spurious Noise –78 –78 dB typ ANALOG INPUT Input Voltage Ranges 0 to VREF 0 to VREF Volts Leakage Current ±1 ±1 µA max ±0.1 ±0.1 µA typ Input Capacitance9 20 20 pF max TEMPERATURE SENSOR10 Voltage Output at 25°C 600 600 mV typ Can vary significantly (> ±20%) Voltage TC –3.0 –3.0 mV/°C typ from device to device DAC CHANNEL SPECIFICATIONS DC ACCURACY11 Resolution 12 12 Bits Relative Accuracy ±3 ±3 LSB typ Differential Nonlinearity ±0.5 ±1 LSB typ Guaranteed 12-Bit Monotonic Offset Error ±60 ±60 mV max ±15 ±15 mV typ Full-Scale Error ±30 ±30 mV max ±10 ±10 mV typ Full-Scale Mismatch ±0.5 ±0.5 % typ % of Full-Scale on DAC1 ANALOG OUTPUTS Voltage Range_0 0 to VREF 0 to VREF V typ Voltage Range_1 0 to VDD 0 to VDD V typ Resistive Load 10 10 kΩ typ Capacitive Load 100 100 pF typ Output Impedance 0.5 0.5 Ω typ ISINK 50 50 µA typ REV. C –3–,

ADuC812–SPECIFICATIONS1, 2 (continued)

ADuC812BS Parameter VDD = 5 V VDD = 3 V Unit Test Conditions/Comments DAC AC CHARACTERISTICS Voltage Output Settling Time 15 15 µs typ Full-Scale Settling Time to Within 1/2 LSB of Final Value Digital-to-Analog Glitch Energy 10 10 nV sec typ 1 LSB Change at Major Carry REFERENCE INPUT/OUTPUT REFIN Input Voltage Range9 2.3/VDD 2.3/VDD V min/max Input Impedance 150 150 kΩ typ REFOUT Output Voltage 2.5 ± 2.5% 2.5 ± 2.5% V min/max Initial Tolerance @ 25°C 2.5 2.5 V typ REFOUT Tempco 100 100 ppm/°C typ FLASH/EE MEMORY PERFORMANCE CHARACTERISTICS12, 13 Endurance 10,000 Cycles min 50,000 50,000 Cycles typ Data Retention 10 Years min WATCHDOG TIMER

CHARACTERISTICS

Oscillator Frequency 64 64 kHz typ POWER SUPPLY MONITOR

CHARACTERISTICS

Power Supply Trip Point Accuracy ±2.5 ±2.5 % of Selected Nominal Trip Point Voltage max ±1.0 ±1.0 % of Selected Nominal Trip Point Voltage typ DIGITAL INPUTS Input High Voltage (VINH) 2.4 2.4 V min XTAL1 Input High Voltage (VINH) Only4Vmin Input Low Voltage (VINL) 0.8 0.8 V max Input Leakage Current (Port 0, EA) ±10 ±10 µA max VIN = 0 V or VDD ±1 ±1 µA typ VIN = 0 V or VDD Logic 1 Input Current (All Digital Inputs) ±10 ±10 µA max VIN = VDD ±1 ±1 µA typ VIN = VDD Logic 0 Input Current (Port 1, 2, 3) –80 –40 µA max –40 –20 µA typ VIL = 450 mV Logic 1-0 Transition Current (Port 1, 2, 3) –700 –500 µA max VIL = 2 V –400 –200 µA typ VIL = 2 V Input Capacitance 10 10 pF typ –4– REV. C,

ADuC812BS Parameter VDD = 5 V VDD = 3 V Unit Test Conditions/Comments DIGITAL OUTPUTS Output High Voltage (VOH) 2.4 2.4 V min VDD = 4.5 V to 5.5 V ISOURCE = 80 µA

4.0 2.6 V typ VDD = 2.7 V to 3.3 V

ISOURCE = 20 µA Output Low Voltage (VOL) ALE, PSEN, Ports 0 and 2 0.4 0.4 V max ISINK = 1.6 mA

0.2 0.2 V typ ISINK = 1.6 mA

Port 3 0.4 0.4 V max ISINK = 8 mA

0.2 0.2 V typ ISINK = 8 mA

Floating State Leakage Current ±10 ±10 µA max

±1 ±1 µA typ

Floating State Output Capacitance 10 10 pF typ POWER REQUIREMENTS14, 15, 16 I 17DD Normal Mode 43 25 mA max MCLKIN = 16 MHz

32 16 mA typ MCLKIN = 16 MHz 26 12 mA typ MCLKIN = 12 MHz83mA typ MCLKIN = 1 MHz

IDD Idle Mode 25 10 mA max MCLKIN = 16 MHz

18 6 mA typ MCLKIN = 16 MHz 15 6 mA typ MCLKIN = 12 MHz72mA typ MCLKIN = 1 MHz

IDD Power-Down Mode18 30 15 µA max

5 5 µA typ

NOTES

1Specifications apply after calibration. 2Temperature range –40°C to +85°C. 3Linearity is guaranteed during normal MicroConverter Core operation. 4Linearity may degrade when programming or erasing the 640 Byte Flash/EE space during ADC conversion times due to on-chip charge pump activity. 5Measured in production at VDD = 5 V after Software Calibration Routine at 25°C only. 6User may need to execute Software Calibration Routine to achieve these specifications, which are configuration dependent. 7The offset and gain calibration spans are defined as the voltage range of user system offset and gain errors that the ADuC812 can compensate. 8SNR calculation includes distortion and noise components. 9Specification is not production tested, but is supported by characterization data at initial product release. 10The temperature sensor will give a measure of the die temperature directly; air temperature can be inferred from this result. 11DAC linearity is calculated using: reduced code range of 48 to 4095, 0 to VREF range reduced code range of 48 to 3995, 0 to VDD range DAC output load = 10 kΩ and 50 pF. 12Flash/EE Memory Performance Specifications are qualified as per JEDEC Specification (Data Retention) and JEDEC Draft Specification A117 (Endurance). 13Endurance Cycling is evaluated under the following conditions: Mode = Byte Programming, Page Erase Cycling Cycle Pattern = 00Hex to FFHex Erase Time = 20 ms Program Time = 100 µs 14IDD at other MCLKIN frequencies is typically given by: Normal Mode (VDD = 5 V): IDD = (1.6 nAs × MCLKIN) + 6 mA Normal Mode (VDD = 3 V): IDD = (0.8 nAs × MCLKIN) + 3 mA Idle Mode (VDD = 5 V): IDD = (0.75 nAs × MCLKIN) + 6 mA Idle Mode (VDD = 3 V): IDD = (0.25 nAs × MCLKIN) + 3 mA Where MCLKIN is the oscillator frequency in MHz and resultant I DD values are in mA. 15IDD Currents are expressed as a summation of analog and digital power supply currents during normal MicroConverter operation. 16IDD is not measured during Flash/EE program or erase cycles; IDD will typically increase by 10 mA during these cycles. 17Analog IDD = 2 mA (typ) in normal operation (internal VREF, ADC and DAC peripherals powered on). 18EA = Port0 = DVDD, XTAL1 (Input) tied to DVDD, during this measurement. Typical specifications are not production tested, but are supported by characterization data at initial product release. Timing Specifications—See pages 45–53. Specifications subject to change without notice. Please refer to User Guide, Quick Reference Guide, Application Notes, and Silicon Errata Sheet at www.analog.com/microconverter for additional information.

REV. C –5–

, ABSOLUTE MAXIMUM RATINGS* PIN CONFIGURATION (TA = 25°C unless otherwise noted.) AVDD to DVDD .–0.3 V to +0.3 V AGND to DGND .–0.3 V to +0.3 V DVDD to DGND, AVDD to AGND .–0.3 V to +7 V Digital Input Voltage to DGND .–0.3 V, DVDD + 0.3 V 52 51 50 49 48 47 46 45 44 43 42 41 40 Digital Output Voltage to DGND .–0.3 V, DVDD + 0.3 V P1.0/ADC0/T2 1 39 P2.7/A15/A23 VREF to AGND .–0.3 V, AVDD + 0.3 V PIN 1 P1.1/ADC1/T2EX 2 IDENTIFIER 38 P2.6/A14/A22 Analog Inputs to AGND .–0.3 V, AVDD + 0.3 V P1.2/ADC2 3 37 P2.5/A13/A21 Operating Temperature Range Industrial (B Version) P1.3/ADC3 4 36 P2.4/A12/A20 .–40°C to +85°C AVDD 5 35 DGND AGND 6 34 DV Storage Temperature Range .–65°C to +150°C ADuC812 DDCREF 7 TOP VIEW 33 XTAL2 Junction Temperature .150°C VREF 8 (Not to Scale) 32 XTAL1 θJA Thermal Impedance .90°C/W DAC0 9 31 P2.3/A11/A19 Lead Temperature, Soldering DAC1 10 30 P2.2/A10/A18 Vapor Phase (60 sec) .215°C P1.4/ADC4 11 29 P2.1/A9/A17 P1.5/ADC5/SS 12 28 P2.0/A8/A16 Infrared (15 sec) .220°C P1.6/ADC6 13 27 D1/MOSI *Stresses above those listed under Absolute Maximum Ratings may cause perma- 14 15 16 17 18 19 20 21 22 23 24 25 26 nent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ORDERING GUIDE Temperature Package Package Model Range Description Option ADuC812BS –40°C to +85°C 52-Lead Plastic Quad Flatpack S-52 EVAL-ADuC812QS QuickStart Development System

CAUTION

ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although WARNING! the ADuC812 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ESD SENSITIVE DEVICE –6– REV. C P1.7/ADC7 P0.7/AD7 RESET P0.6/AD6 P3.0/RxD P0.5/AD5 P3.1/TxD P0.4/AD4 P3.2/INT0 DVDD P3.3/INT1/MISO DGND DVDD P0.3/AD3 DGND P0.2/AD2 P3.4/T0 P0.1/AD1 P3.5/T1/CONVST P0.0/AD0 P3.6/WR ALE P3.7/RD PSEN SCLOCK/D0 EA, PIN FUNCTION DESCRIPTIONS Mnemonic Type Function DVDD P Digital Positive Supply Voltage, 3 V or5VNominal AVDD P Analog Positive Supply Voltage, 3 V or5VNominal CREF I Decoupling Input for On-Chip Reference. Connect 0.1 µF between this pin and AGND. VREF I/O Reference Input/Output. This pin is connected to the internal reference through a series resistor and is the reference source for the analog-to-digital converter. The nominal internal reference voltage is 2.5 V and this appears at the pin. This pin can be overdriven by an external reference. AGND G Analog Ground. Ground Reference point for the analog circuitry. P1.0–P1.7 I Port 1 is an 8-bit Input Port only. Unlike other Ports, Port 1 defaults to Analog Input Mode, to configure any of these Port Pins as a digital input, write a “0” to the port bit. Port 1 pins are multifunction and share the following functionality. ADC0–ADC7 I Analog Inputs. Eight single-ended analog inputs. Channel selection is via ADCCON2 SFR. T2 I Timer 2 Digital Input. Input to Timer/Counter 2. When Enabled, Counter 2 is incremented in response toa1to 0 transition of the T2 input. T2EX I Digital Input. Capture/Reload trigger for Counter 2 and also functions as an Up/Down control input for Counter 2. SS I Slave Select Input for the SPI Interface D0 O Digital Output Pin D1 O Digital Output Pin SCLOCK I/O SPI Serial Interface Clock MOSI I/O SPI Master Output/Slave Input Data I/O Pin for SPI Interface MISO I/O SPI Master Input/Slave Output Data I/O Pin for SPI Serial Interface DAC0 O Voltage Output from DAC0 DAC1 O Voltage Output from DAC1 RESET I Digital Input. A high level on this pin for 24 master clock cycles while the oscillator is running resets the device. External power-on reset (POR) circuity must be implemented to drive the RESET pin as described in the Power-On Reset Operation section of this data sheet. P3.0–P3.7 I/O Port 3 is a bidirectional port with internal pull-up resistors. Port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 3 pins being pulled externally low will source current because of the internal pull-up resistors. Port 3 pins also contain various secondary functions which are described below. RxD I/O Receiver Data Input (Asynchronous) or Data Input/Output (Synchronous) of Serial (UART) Port TxD O Transmitter Data Output (Asynchronous) or Clock Output (Synchronous) of Serial (UART) Port INT0 I Interrupt 0, programmable edge or level triggered Interrupt input, which can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 0. INT1 I Interrupt 1, programmable edge or level triggered Interrupt input, which can be programmed to one of two priority levels. This pin can also be used as a gate control input to Timer 1. T0 I Timer/Counter 0 Input T1 I Timer/Counter 1 Input CONVST I Active low Convert Start Logic input for the ADC block when the external Convert start function is enabled. A low-to-high transition on this input puts the track/hold into its hold mode and starts conversion. WR O Write Control Signal, Logic Output. Latches the data byte from Port 0 into the external data memory. RD O Read Control Signal, Logic Output. Enables the external data memory to Port 0. XTAL2 O Output of the Inverting Oscillator Amplifier XTAL1 I Input to the inverting oscillator amplifier and input to the internal clock generator circuits. DGND G Digital Ground. Ground reference point for the digital circuitry. P2.0–P2.7 I/O Port 2 is a bidirectional port with internal pull-up resistors. Port 2 pins that have 1s written to them are (A8–A15) pulled high by the internal pull-up resistors, and in that state they can be used as inputs. As inputs Port 2 (A16–A23) pins being pulled externally low will source current because of the internal pull-up resistors. Port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space. REV. C –7–, PIN FUNCTION DESCRIPTIONS (continued) Mnemonic Type Function PSEN O Program Store Enable, Logic Output. This output is a control signal that enables the external program memory to the bus during external fetch operations. It is active every six oscillator periods except during external data memory accesses. This pin remains high during internal program execution. PSEN can also be used to enable serial download mode when pulled low through a resistor on power-up or RESET. ALE O Address Latch Enable, Logic Output. This output is used to latch the low byte (and page byte for 24-bit address space accesses) of the address into external memory during normal operation. It is activated every six oscillator periods except during an external data memory access. EA I External Access Enable, Logic Input. When held high, this input enables the device to fetch code from internal program memory locations 0000H to 1FFFH. When held low this input enables the device to fetch all instructions from external program memory. P0.7–P0.0 I/O Port 0 is an 8-Bit Open Drain Bidirectional I/O port. Port 0 pins that have 1s written to them float and in (A0–A7) that state can be used as high impedance inputs. Port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory. In this application it uses strong internal pull-ups when emitting 1s. TERMINOLOGY The ratio is dependent upon the number of quantization levels ADC SPECIFICATIONS in the digitization process; the more levels, the smaller the quan- Integral Nonlinearity tization noise. The theoretical signal to (noise + distortion) ratio This is the maximum deviation of any code from a straight line for an ideal N-bit converter with a sine wave input is given by: passing through the endpoints of the ADC transfer function. Signal to (Noise + Distortion) = (6.02N + 1.76) dB The endpoints of the transfer function are zero scale, a point 1/2 LSB below the first code transition and full-scale, a point Thus for a 12-bit converter, this is 74 dB. 1/2 LSB above the last code transition. Total Harmonic Distortion Differential Nonlinearity Total Harmonic Distortion is the ratio of the rms sum of the This is the difference between the measured and the ideal 1 LSB harmonics to the fundamental. change between any two adjacent codes in the ADC. DAC SPECIFICATIONS Offset Error Relative Accuracy This is the deviation of the first code transition (0000 .000) Relative accuracy or endpoint linearity is a measure of the to (0000 .001) from the ideal, i.e., +1/2 LSB. maximum deviation from a straight line passing through the Full-Scale Error endpoints of the DAC transfer function. It is measured after This is the deviation of the last code transition from the ideal adjusting for zero error and full-scale error. AIN voltage (Full-Scale – 1.5 LSB) after the offset error has Voltage Output Settling Time been adjusted out. This is the amount of time it takes for the output to settle to a Signal to (Noise + Distortion) Ratio specified level for a full-scale input change. This is the measured ratio of signal to (noise + distortion) at the Digital-to-Analog Glitch Impulse output of the A/D converter. The signal is the rms amplitude of This is the amount of charge injected into the analog output the fundamental. Noise is the rms sum of all nonfundamental when the inputs change state. It is specified as the area of the signals up to half the sampling frequency (fS/2), excluding dc. glitch in nV sec. –8– REV. C, ARCHITECTURE, MAIN FEATURES 7FH The ADuC812 is a highly integrated true 12-bit data acquisition system. At its core, the ADuC812 incorporates a high- perfor- mance 8-bit (8052-Compatible) MCU with on-chip reprogrammable nonvolatile Flash program memory control- 2FH ling a multichannel (8-input channels), 12-bit ADC. BANKS BIT-ADDRESSABLE SPACE SELECTED (BIT ADDRESSES 0FH–7FH) The chip incorporates all secondary functions to fully support VIABITS IN PSW 20H the programmable data acquisition core. These secondary 1FH functions include User Flash Memory, Watchdog Timer 11 18H (WDT), Power Supply Monitor (PSM) and various industry- 17H standard parallel and serial interfaces. 10 10H 4 BANKS OF 8 REGISTERS 0FH R0–R7 PROGRAM MEMORY SPACE 01 READ ONLY 08H 07H RESET VALUE OF FFFFH 00 STACK POINTER 00H

EXTERNAL

PROGRAM Figure 2. Lower 128 Bytes of Internal RAM

MEMORY SPACE

MEMORY ORGANIZATION As with all 8052-compatible devices, the ADuC812 has separate address spaces for Program and Data memory as shown in Fig- 2000H ure 1. Also as shown in Figure 1, an additional 640 Bytes of User Data Flash EEPROM are available to the user. The User Data Flash Memory area is accessed indirectly via a group of 1FFFH EA = 1 EA = 0 control registers mapped in the Special Function Register (SFR) INTERNAL EXTERNAL area in the Data Memory Space. 8K BYTE PROGRAM FLASH/EE MEMORY PROGRAM SPACE The SFR space is mapped in the upper 128 bytes of internal data

MEMORY

0000H memory space. The SFR area is accessed by direct addressing only and provides an interface between the CPU and all on-chip DATA MEMORY SPACE READ/WRITE peripherals. A block diagram showing the programming model of the ADuC812 via the SFR area is shown in Figure 3.

FFFFFFH

9FH (PAGE 159) 640 BYTES FLASH/EE DATA 8K BYTE MEMORY ELECTRICALLY 640-BYTE ACCESSED REPROGRAMMABLE ELECTRICALLY INDIRECTLY NONVOLATILE REPROGRAMMABLE VIA SFR FLASH/EE PROGRAM CONTROL REGISTERS NONVOLATILEMEMORY FLASH/EE DATA 00H (PAGE 0) MEMORY 128-BYTE EXTERNAL SPECIAL AUTO-CALIBRATING INTERNAL 8051DATA 8-CHANNEL DATA MEMORY MEMORY COMPATIBLE

FUNCTION

REGISTER HIGH SPEED SPACE SPACE CORE AREA 12-BIT ADC FFH (24-BIT FFH SPECIAL ADDRESSACCESSIBLE FUNCTION SPACE) OTHER ON-CHIP BY REGISTERS INDIRECT ACCESSIBLE PERIPHERALSUPPER 128 ADDRESSING BY DIRECT

TEMPERATURE

ONLY ADDRESSING SENSOR ONLY 80H 2 12-BIT DACs80H 7FH SERIAL I/OACCESSIBLE PARALLEL I/O

BY

LOWER WDTDIRECT 128 PSMAND

INDIRECT

00H ADDRESSING 000000H Figure 3. Programming Model

Figure 1. Program and Data Memory Maps

The lower 128 bytes of internal data memory are mapped as shown in Figure 2. The lowest 32 bytes are grouped into four banks of eight registers addressed as R0 through R7. The next 16 bytes (128 bits) above the register banks form a block of bit addressable memory space at bit addresses 00H through 7FH.

REV. C –9–

, OVERVIEW OF MCU-RELATED SFRs Power Control SFR Accumulator SFR The Power Control (PCON) register contains bits for power- ACC is the Accumulator register and is used for math opera- saving options and general-purpose status flags as shown in tions including addition, subtraction, integer multiplication and Table II. division, and Boolean bit manipulations. The mnemonics for SFR Address 87H accumulator-specific instructions refer to the Accumulator as A. Power ON Default Value 00H B SFR Bit Addressable No The B register is used with the ACC for multiplication and division operations. For other instructions it can be treated as a SMOD SERIPD INTOPD ALEOFF GF1 GF0 PD IDL general-purpose scratchpad register. Stack Pointer SFR The SP register is the stack pointer and is used to hold an inter- Table II. PCON SFR Bit Designations nal RAM address that is called the “top of the stack.” The SP register is incremented before data is stored during PUSH and Bit Name Description CALL executions. While the Stack may reside anywhere in 7 SMOD Double UART Baud Rate on-chip RAM, the SP register is initialized to 07H after a reset. 6 ——— Reserved This causes the stack to begin at location 08H. 5 ——— Reserved Data Pointer 4 ALEOFF Disable ALE Output The Data Pointer is made up of three 8-bit registers, named 3 GF1 General-Purpose Flag Bit DPP (page byte), DPH (high byte) and DPL (low byte). These 2 GF0 General-Purpose Flag Bit are used to provide memory addresses for internal and external 1 PD Power-Down Mode Enable code access and external data access. It may be manipulated asa0IDL Idle Mode Enable 16-bit register (DPTR = DPH, DPL), although INC DPTR instructions will automatically carry over to DPP, or as three independent 8-bit registers (DPP, DPH, DPL). Program Status Word SFR The PSW register is the Program Status Word which contains several bits reflecting the current status of the CPU as detailed in Table I. SFR Address D0H Power ON Default Value 00H Bit Addressable Yes CY AC F0 RS1 RS0 OV F1 P Table I. PSW SFR Bit Designations Bit Name Description 7 CY Carry Flag 6 AC Auxiliary Carry Flag 5 F0 General-Purpose Flag 4 RS1 Register Bank Select Bits 3 RS0 RS1 RS0 Selected Bank0000111021132OV Overflow Flag 1 F1 General-Purpose Flag0PParity Bit –10– REV. C,

SPECIAL FUNCTION REGISTERS All registers except the program counter and the four general purpose register banks, reside in the special function register (SFR) area. The SFR registers include control, configuration and data registers that provide an interface between the CPU and other on-chip

peripherals.

Figure 4 shows a full SFR memory map and SFR contents on Reset. Unoccupied SFR locations are shown dark-shaded in the figure

below (NOT USED). Unoccupied locations in the SFR address space are not implemented i.e., no register exists at this location. If an unoccupied location is read, an unspecified value is returned. SFR locations reserved for on chip testing are shown lighter shaded below (RESERVED) and should not be accessed by user software. Sixteen of the SFR locations are also bit addressable and denoted by ‘1’ in the figure below, i.e., the bit addressable SFRs are those whose address ends in 0H or 8H. ISPI WCOL SPE SPIM CPOL CPHA SPR1 SPR0 SPICON1BITS DAC0L DAC0H DAC1L DAC1H DACCON RESERVED NOT USED FFH 0 FEH 0 FDH 0 FCH 0 FBH 0 FAH 0 F9H 0 F8H 0 F8H 00H F9H 00H FAH 00H FBH 00H FCH 00H FDH 04H B1 ADCOFSL2 ADCOFSH2 ADCGAINL2 ADCGAINH2 ADCCON3 SPIDAT

BITS

F7H 0 F6H 0 F5H 0 F4H 0 F3H 0 F2H 0 F1H 0 F0H 0 RESERVEDF0H 00H F1H 00H F2H 20H F3H 00H F4H 00H F5H 00H F7H 00H D1 D1EN D0 D0EN DCON1 ADCCON1BITS RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED EFH 0 EEH 0 EDH 0 ECH 0 EBH 0 EAH 0 E9H 0 E8H 0 E8H 00H EFH 20H ACC1 BITS RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED RESERVED E7H 0 E6H 0 E5H 0 E4H 0 E3H 0 E2H 0 E1H 0 E0H 0 E0H 00H ADCI DMA CCONV SCONV CS3 CS2 CS1 CS0 ADCCON21 ADCDATAL ADCDATAH PSMCON BITS RESERVED RESERVED RESERVED RESERVED DFH 0 DEH 0 DDH 0 DCH 0 DBH 0 DAH 0 D9H 0 D8H 0 D8H 00H D9H 00H DAH 00H DFH DEH CY AC F0 RS1 RS0 OV FI P PSW1 DMAL DMAH DMAP BITS RESERVED RESERVED RESERVED RESERVED D7H 0 D6H 0 D5H 0 D4H 0 D3H 0 D2H 0 D1H 0 D0H 0 D0H 00H D2H 00H D3H 00H D4H 00H TF2 EXF2 RCLK TCLK EXEN2 TR2 CNT2 CAP2 T2CON1 RCAP2L RCAP2H TL2 TH2BITS RESERVED RESERVED RESERVED CFH 0 CEH 0 CDH 0 CCH 0 CBH 0 CAH 0 C9H 0 C8H 0 C8H 00H CAH 00H CBH 00H CCH 00H CDH 00H PRE2 PRE1 PRE0 WDR1 WDR2 WDS WDE WDCON1 ETIM3 EDARLBITS NOT USED NOT USED NOT USED RESERVED RESERVED C7H 0 C6H 0 C5H 0 C4H 0 C3H 0 C2H 0 C1H 0 C0H 0 C0H 00H C4H C9H C6H 00H PSI PADC PT2 PS PT1 PX1 PT0 PX0 IP1 ECON ETIM1 ETIM2 EDATA1 EDATA2 EDATA3 EDATA4BITS BFH 0 BEH 0 BDH 0 BCH 0 BBH 0 BAH 0 B9H 0 B8H 0 B8H 00H B9H 00H BAH 52H BBH 04H BCH 00H BDH 00H BEH 00H BFH 00H RD WR T1 T0 INT1 INT0 TxD RxD P31BITS NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED B7H 1 B6H 1 B5H 1 B4H 1 B3H 1 B2H 1 B1H 1 B0H 1 B0H FFH EA EADC ET2 ES ET1 EX1 ET0 EX0 IE1 IE2BITS NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED AFH 0 AEH 0 ADH 0 ACH 0 ABH 0 AAH 0 A9H 0 A8H 0 A8H 00H A9H 00H BITS NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED A7H 1 A6H 1 A5H 1 A4H 1 A3H 1 A2H 1 A1H 1 A0H 1 A0H FFH SM0 SM1 SM2 REN TB8 RB8 TI RI SCON1 SBUFBITS RESERVED RESERVED NOT USED NOT USED NOT USED NOT USED 9FH 0 9EH 0 9DH 0 9CH 0 9BH 0 9AH 0 99H 0 98H 0 98H 00H 99H 00H T2EX T2 P11, 3BITS NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED NOT USED 97H 1 96H 1 95H 1 94H 1 93H 1 92H 1 91H 1 90H 1 90H FFH TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0 TCON1 TMOD TL0 TL1 TH0 TH1BITS NOT USED NOT USED 8FH 0 8EH 0 8DH 0 8CH 0 8BH 0 8AH 0 89H 0 88H 0 88H 00H 89H 00H 8AH 00H 8BH 00H 8CH 00H 8DH 00H P01 SP DPL DPH DPP PCON BITS RESERVED RESERVED 87H 1 86H 1 85H 1 84H 1 83H 1 82H 1 81H 1 80H 1 80H FFH 81H 07H 82H 00H 83H 00H 84H 00H 87H 00H SFR MAP KEY: THESE BITS ARE CONTAINED IN THIS BYTE. MNEMONIC IE0 IT0 TCON MNEMONIC SFR ADDRESS 89H 0 88H 0 88H 00H DEFAULT VALUE DEFAULT VALUE SFR ADDRESS SFR NOTES 1SFRs WHOSE ADDRESS ENDS IN 0H OR 8H ARE BIT ADDRESSABLE. 2CALIBRATION COEFFICIENTS ARE PRECONFIGURED ON POWER-UP TO FACTORY CALIBRATED VALUES. 3THE PRIMARY FUNCTION OF PORT1 IS AS AN ANALOG INPUT PORT; THEREFORE, TO ENABLE THE DIGITAL SECONDARY FUNCTIONS ON THESE PORT PINS, WRITE A ‘0’ TO THE CORRESPONDING PORT 1 SFR BIT.

Figure 4. Special Function Register Locations and Reset Values REV. C –11–

, ADC CIRCUIT INFORMATION ADC Transfer Function General Overview The analog input range for the ADC is0Vto VREF. For this The ADC conversion block incorporates a fast, 8-channel, range, the designed code transitions occur midway between 12-bit, single supply A/D converter. This block provides the successive integer LSB values (i.e., 1/2 LSB, 3/2 LSBs, user with multichannel mux, track/hold, on-chip reference, 5/2 LSBs .FS –3/2 LSBs). The output coding is straight calibration features and A/D converter. All components in this binary with 1 LSB = FS/4096 or 2.5 V/4096 = 0.61 mV when block are easily configured via a 3-register SFR interface. VREF = 2.5 V. The ideal input/output transfer characteristic for The A/D converter consists of a conventional successive- the 0 to VREF range is shown in Figure 5. approximation converter based around a capacitor DAC. The

OUTPUT

converter accepts an analog input range of 0 to +VREF. A high CODE precision, low drift and factory calibrated 2.5 V reference is 111...111 provided on-chip. The internal reference may be overdriven via 111...110 the external VREF pin. This external reference can be in the 111...101 range 2.3 V to AVDD. 111...100

FS

Single step or continuous conversion modes can be initiated in 1LSB = 4096 software or alternatively by applying a convert signal to the an external pin. Timer 2 can also be configured to generate a repeti- tive trigger for ADC conversions. The ADC may be configured 000...011 to operate in a DMA Mode whereby the ADC block continu- 000...010 ously converts and captures samples to an external RAM space 000...001 without any interaction from the MCU core. This automatic 000...000 capture facility can extend through a 16 MByte external Data 0V 1LSB +FSVOLTAGE INPUT –1LSB Memory space. Figure 5. ADC Transfer Function The ADuC812 is shipped with factory programmed calibration coefficients which are automatically downloaded to the ADC on Typical Operation power-up ensuring optimum ADC performance. The ADC core Once configured via the ADCCON 1–3 SFRs (shown on the contains internal Offset and Gain calibration registers. A following page) the ADC will convert the analog input and provide software calibration routine is provided to allow the user to an ADC 12-bit result word in the ADCDATAH/L SFRs. The top overwrite the factory programmed calibration coefficients if 4 bits of the ADCDATAH SFR will be written with the channel required, thus minimizing the impact of endpoint errors in the selection bits to identify the channel result. The format of the ADC user’s target system. 12-bit result word is shown in Figure 6. A voltage output from an On-Chip bandgap reference propor- tional to absolute temperature can also be routed through the ADCDATAH SFR front end ADC multiplexor (effectively a 9th ADC channel input) facilitating a temperature sensor implementation. CH–ID HIGH 4 BITS OFTOP 4 BITS ADC RESULT WORD ADCDATAL SFR LOW 8 BITS OF THE ADC RESULT WORD Figure 6. ADC Result Format –12– REV. C, ADCCON1—(ADC Control SFR #1) The ADCCON1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as detailed below. SFR Address: EFH SFR Power-On Default Value: 20H MD1 MD0 CK1 CK0 AQ1 AQ0 T2C EXC Table III. ADCCON1 SFR Bit Designations Bit Name Description ADCCON1.7 MD1 The mode bits (MD1, MD0) select the active operating mode of the ADC as follows: ADCCON1.6 MD0 MD1 MD0 Active Mode00ADC powered down01ADC normal mode10ADC powered down if not executing a conversion cycle. 1 1 ADC standby if not executing a conversion cycle. Note: In powered down mode the ADC VREF circuits are maintained on, whereas in power-down mode all ADC peripherals are powered down thus minimizing current consumption. ADCCON1.5 CK1 The ADC clock divide bits (CK1, CK0) select the divide ratio for the master clock used to generate the ADCCON1.4 CK0 ADC clock. A typical ADC conversion will require 17 ADC clocks. The divider ratio is selected as follows: CK1 CK0 MCLK Divider001012104118ADCCON1.3 AQ1 The ADC acquisition select bits (AQ1, AQ0) select the time provided for the input track/hold amplifier ADCCON1.2 AQ0 to acquire the input signal and are selected as follows: AQ1 AQ0 #ADC Clks001012104118ADCCON1.1 T2C The Timer 2 conversion bit (T2C) is set by the user to enable the Timer 2 over flow bit be used as the ADC convert start trigger input. ADC conversions are initiated on the second Timer 2 overflow. ADCCON1.0 EXC The external trigger enable bit (EXC) is set by the user to allow the external Pin 23 (CONVST) to be used as the active low convert start input. This input should be an active low pulse (minimum pulse width >100 ns) at the required sample rate. REV. C –13–, ADCCON2—(ADC Control SFR #2) The ADCCON2 register controls ADC channel selection and conversion modes as detailed below. SFR Address: D8H SFR Power On Default Value: 00H ADCI DMA CCONV SCONV CS3 CS2 CS1 CS0 Table IV. ADCCON2 SFR Bit Designations Location Name Description ADCCON2.7 ADCI The ADC interrupt bit (ADCI) is set by hardware at the end of a single ADC conversion cycle or at the end of a DMA block conversion. ADCI is cleared by hardware when the PC vectors to the ADC Interrupt Service Routine. ADCCON2.6 DMA The DMA mode enable bit (DMA) is set by the user to enable a preconfigured ADC DMA mode operation. A more detailed description of this mode is given in the ADC DMA Mode section. ADCCON2.5 CCONV The continuous conversion bit (CCONV) is set by the user to initiate the ADC into a continuous mode of conversion. In this mode the ADC starts converting based on the timing and channel configuration already set up in the ADCCON SFRs, the ADC automatically starts another conversion once a previous conversion has completed. ADCCON2.4 SCONV The single conversion bit (SCONV) is set to initiate a single conversion cycle. The SCONV bit is automatically reset to “0” on completion of the single conversion cycle. ADCCON2.3 CS3 The channel selection bits (CS3–0) allow the user to program the ADC channel selection under ADCCON2.2 CS2 software control. When a conversion is initiated the channel converted will be that pointed to by ADCCON2.1 CS1 these channel selection bits. In DMA mode the channel selection is derived from the channel ID ADCCON2.0 CS0 written to the external memory. CS3 CS2 CS1 CS0 CH# 00000000110010200113010040101501106011171000Temp Sensor1111DMA STOP All other combinations reserved ADCCON3—(ADC Control SFR #3) The ADCCON3 register gives user software an indication of ADC busy status. SFR Address: F5H SFR Power On Default Value: 00H BUSY RSVD RSVD RSVD RSVD RSVD RSVD RSVD Table V. ADCCON3 SFR Bit Designations Bit Location Bit Status Description ADCCON3.7 BUSY The ADC busy status bit (BUSY) is a read-only status bit that is set during a valid ADC conversion or calibration cycle. Busy is automatically cleared by the core at the end of conversion or calibration. ADCCON3.6 RSVD ADCCON3.0–3.6 are reserved (RSVD) for internal use. These bits will read as zero and should only ADCCON3.5 RSVD be written as zero by user software. ADCCON3.4 RSVD ADCCON3.3 RSVD ADCCON3.2 RSVD ADCCON3.1 RSVD ADCCON3.0 RSVD –14– REV. C, Driving the A/D Converter The ADC incorporates a successive approximation (SAR) archi- ADuC812 tecture involving a charge-sampled input stage. Figure 7 shows 51 the equivalent circuit of the analog input section. Each ADC 1 AIN0 conversion is divided into two distinct phases as defined by the 0.01F position of the switches in Figure 7. During the sampling phase (with SW1 and SW2 in the “track” position) a charge propor- tional to the voltage on the analog input is developed across the Figure 8. Buffering Analog Inputs input sampling capacitor. During the conversion phase (with does so by providing a capacitive bank from which the 2 pF sam- both switches in the “hold” position) the capacitor DAC is pling capacitor can draw its charge. Since the 0.01 µF capacitor adjusted via internal SAR logic until the voltage on node A is in Figure 8 is more than 4096 times the size of the 2 pF sam- zero indicating that the sampled charge on the input capacitor is pling capacitor, its voltage will not change by more than one balanced out by the charge being output by the capacitor DAC. count (1/4096) of the 12-bit transfer function when the 2 pF The digital value finally contained in the SAR is then latched charge from a previous channel is dumped onto it. A larger out as the result of the ADC conversion. Control of the SAR, capacitor can be used if desired, but not a larger resistor (for and timing of acquisition and sampling modes, is handled reasons described below). automatically by built-in ADC control logic. Acquisition and The Schottky diodes in Figure 8 may be necessary to limit the conversion times are also fully configurable under user control. voltage applied to the analog input pin as per the data sheet absolute maximum ratings. They are not necessary if the op amp is powered from the same supply as the ADuC812 since AIN0 TEMPERATURE ADuC812 in that case, the op amp is unable to generate voltages above SENSOR VDD or below ground. An op amp is necessary unless the signal source is very low impedance to begin with. DC leakage currents at the ADuC812’s analog inputs can cause measurable dc errors with external source impedances of as little as 100 Ω. To ensure accurate ADC operation, keep the total source impedance at each AIN7 analog input less than 61 Ω. The table below illustrates examples 200 of how source impedance can affect dc accuracy. Source Error from 1 µA Error from 10 µA

TRACK

SW1 CAPACITOR Impedance Leakage Current Leakage Current

DAC

HOLD 61 Ω 61 µV = 0.1 LSB 610 µV = 1 LSB2pF 610 Ω 610 µV = 1 LSB 6.1 mV = 10 LSB NODE A SW2 Although Figure 8 shows the op amp operating at a gain of 1, you can configure it for any gain needed. Also, you can use an TRACK HOLD instrumentation amplifier in its place to condition differential

COMPARATOR

signals. Use any modern amplifier that is capable of delivering AGND the signal (0 to VREF) with minimal saturation. Some single-supply, rail-to-rail op amps that are useful for this purpose include, but Figure 7. Internal ADC Structure are not limited to, the ones given in Table VI. Check Analog Note that whenever a new input channel is selected, a residual Devices literature (CD ROM data book, etc.) for details about charge from the 2 pF sampling capacitor places a transient on these and other op amps and instrumentation amps. the newly selected input. The signal source must be capable of recovering from this transient before the sampling switches click Table VI. Some Single-Supply Op Amps into “hold” mode. Delays can be inserted in software (between channel selection and conversion request) to account for input Op Amp Model Characteristics stage settling, but a hardware solution will alleviate this burden OP181/OP281/OP481 Micropower from the software design task and will ultimately result in a OP191/OP291/OP491 I/O Good up to VDD, Low Cost cleaner system implementation. One hardware solution would OP196/OP296/OP496 I/O to VDD, Micropower, Low Cost be to choose a very fast settling op amp to drive each analog OP183/OP283 High Gain-Bandwidth Product input. Such an op amp would need to settle fully from a small OP162/OP262/OP462 High GBP, Micro Package signal transient in less than 300 ns to guarantee adequate settling AD820/AD822/AD824 FET Input, Low Cost under all software configurations. A better solution, recommended AD823 FET Input, High GBP for use with any amplifier, is shown in Figure 8. Though at first glance the circuit in Figure 8 may look like a Keep in mind that the ADC’s transfer function is 0 to VREF, and simple antialiasing filter, it actually serves no such purpose since any signal range lost to amplifier saturation near ground will its corner frequency is well above the Nyquist frequency, even at impact dynamic range. Though the op amps in Table VI are a 200 kHz sample rate. Though the R/C does helps to reject some capable of delivering output signals very closely approaching incoming high-frequency noise, its primary function is to ensure ground, no amplifier can deliver signals all the way to ground when that the transient demands of the ADC input stage are met. It powered by a single supply. Therefore, if a negative supply is available, consider using it to power the front-end amplifiers. REV. C –15–, However, be sure to include the Schottky diodes shown in Figure 8 (or at least the lower of the two diodes) to protect the ADuC812 analog input from undervoltage conditions. To summarize this VDD 51 2.5V section, use the circuit of Figure 8 to drive the analog input pins EXTERNAL BANDGAP of the ADuC812. VOLTAGE REFERENCE REFERENCE BUFFER Voltage Reference Connections VREF 8 The on-chip 2.5 V bandgap voltage reference can be used as the 0.1F reference source for the ADC and DACs. To ensure the accuracy of the voltage reference decouple both the VREF pin and the CREF CREF 7 pin to ground with 0.1 µF ceramic chip capacitors as shown in 0.1F Figure 9. Figure 10. Using an External Voltage Reference ADuC812 Configuring the ADC BUFFER 51 2.5V The three SFRs (ADCCON1, ADCCON2, ADCCON3) con-

BANDGAP

REFERENCE figure the ADC. In nearly all cases, an acquisition time of 1 BUFFER ADC clock (ADCCON1.2 = 0, ADCCON1.3 = 0) will provide

VREF

8 plenty of time for the ADuC812 to acquire its signal before 0.1F switching the internal track and hold amplifier in to hold mode. The only exception would be a high source impedance analog CREF input, but these should be buffered first anyway since source7 0.1F impedances of greater than 610 Ω can cause dc errors as well. The ADuC812’s successive approximation ADC is driven by a divided down version of the master clock. To ensure adequate Figure 9. Decoupling VREF and CREF ADC operation, this ADC clock must be between 400 kHz and The internal voltage reference can also be tapped directly from 4 MHz, and optimum performance is obtained with ADC clock the VREF pin if desired, to drive external circuitry. However, a between 400 kHz and 3 MHz. Frequencies within this range can buffer must be used to ensure that no current is drawn from the be achieved with master clock frequencies from 400 kHz to well VREF pin itself. The voltage on the CREF pin is that of an internal above 16 MHz with the four ADC clock divide ratios to choose node within the buffer block, and its voltage is critical to ADC from. For example, with a 12 MHz master clock, set the ADC and DAC accuracy. Do not connect anything to this pin except clock divide ratio to 4 (i.e., ADCCLK = MCLK/4 = 3 MHz) by the capacitor, and be sure to keep trace-lengths short on the setting the appropriate bits in ADCCON1 (ADCCON1.5 = 1, CREF capacitor, decoupling the node straight to the underlying ADCCON1.4 = 0). ground plane. The total ADC conversion time is 15 ADC clocks, plus 1 ADC The ADuC812 powers up with its internal voltage reference in the clock for synchronization, plus the selected acquisition time “off” state. The voltage reference turns on automatically whenever (1, 2, 3, or 4 ADC clocks). For the example above, witha1clock the ADC or either DAC gets enabled in software. Once enabled, acquisition time, total conversion time is 17 ADC clocks (or 5.67 µs the voltage reference requires approximately 65 ms to power up fora3MHz ADC clock). and settle to its specified value. Be sure that your software allows In continuous conversion mode, a new conversion begins each this time to elapse before initiating any conversions. If an external time the previous one finishes. The sample rate is the inverse of the voltage reference is preferred, connect it to the VREF pin as shown total conversion time described above. In the example above, the in Figure 10 to overdrive the internal reference. continuous conversion mode sample rate would be 176.5 kHz. To ensure accurate ADC operation, the voltage applied to VREF ADC DMA Mode must be between 2.3 V and AVDD. In situations where analog The on-chip ADC has been designed to run at a maximum input signals are proportional to the power supply (such as some conversion speed of 5 µs (200 kHz sampling rate). When con- strain-gage applications) it can be desirable to connect the VREF verting at this rate the ADuC812 micro has 5 µs to read the pin directly to AVDD. In such a configuration, the user must also ADC result and store the result in memory for further post connect the CREF pin directly to AVDD to circumvent internal processing all within 5 µs otherwise the next ADC sample could buffer headroom limitations. This allows the ADC input trans- be lost. In an interrupt driven routine the micro would also have fer function to span the full range 0 to AVDD accurately. to jump to the ADC Interrupt Service routine which will also Operation of the ADC or DACs with a reference voltage below increase the time required to store the ADC results. In applica- 2.3 V, however, may incur loss of accuracy resulting in missing tions where the ADuC812 cannot sustain the interrupt rate, an codes or nonmonotonicity. For that reason, do not use a reference ADC DMA mode is provided. voltage less than 2.3 V. To enable DMA mode, Bit 6 in ADCCON2 (DMA) must be set. This allows the ADC results to be written directly to a 16 MByte external static memory SRAM (mapped into data memory space) –16– REV. C, without any interaction from the ADuC812 core. This mode 00000AH1111STOP COMMAND allows the ADuC812 to capture a contiguous sample stream at NO CONVERSION full ADC update rates (200 kHz). 0011RESULT WRITTEN HERE DMA Mode Configuration Example CONVERSION RESULT FOR ADC CH#3 To set the ADuC812 into DMA mode, a number of steps must0011be followed. CONVERSION RESULT1000FOR TEMP SENSOR 1. The ADC must be powered down by setting MD1 and MD0 CONVERSION RESULT to 0 in ADCCON1. 0101FOR ADC CH#5 CONVERSION RESULT 2. The DMA Address pointer must be set to the start address of 000000H0010FOR ADC CH#2 where the ADC Results are to be written. This is done by writing to the DMA mode Address Pointers DMAL, DMAH, Figure 12. Typical External Memory Configuration Post and DMAP. DMAL must be written to first, followed by ADC DMA Operation DMAH and then by DMAP. The DMA logic operates from the ADC clock and uses pipe- 3. The external memory must be preconfigured. This consists of lining to perform the ADC conversions and access the external writing the required ADC channel IDs into the top four bits of memory at the same time. The time it takes to perform one every second memory location in the external SRAM starting ADC conversion is called a DMA cycle. The actions performed at the first address specified by the DMA address pointer. As the by the logic during a typical DMA cycle are shown in Figure 13. ADC DMA mode operates independently of the ADuC812 core, it is necessary to provide it with a stop command. This CONVERT CHANNEL READ DURING PREVIOUS DMA CYCLE is done by duplicating the last channel ID to be converted fol- lowed by “1111” into the next channel selection field. Figure 11 WRITE ADC RESULT READ CHANNEL ID shows a typical preconfiguration of external memory. CONVERTED DURING TO BE CONVERTED DURING PREVIOUS DMA CYCLE NEXT DMA CYCLE 00000AH1111STOP COMMAND DMA CYCLE REPEAT LAST CHANNEL0011FOR A VALID STOP Figure 13. DMA Cycle

CONDITION

From the previous diagram, it can be seen that during one DMA0011CONVERT ADC CH#3 cycle the following actions are performed by the DMA logic. 1000CONVERT TEMP SENSOR 1. An ADC conversion is performed on the channel whose ID was read during the previous cycle. 0101CONVERT ADC CH#5 2. The 12-bit result and the channel ID of the conversion per- 000000H0010CONVERT ADC CH#2 formed in the previous cycle is written to the external memory. 3. The ID of the next channel to be converted is read from

Figure 11. Typical DMA External Memory Preconfiguration external memory.

4. The DMA is initiated by writing to the ADC SFRs in the For the previous example, the complete flow of events is shown following sequence. in Figure 13. Because the DMA logic uses pipe-lining, it takes a. ADCCON2 is written to enable the DMA mode. i.e., three cycles before the first correct result is written out. MOV ADCCON2, #40H; DMA Mode enabled. Micro Operation during ADC DMA Mode b. ADCCON1 is written to configure the conversion time and During ADC DMA mode, the MicroConverter core is free to power up of the ADC. It can also enable Timer 2 driven continue code execution, including general housekeeping and conversions or External Triggered conversions if required. communication tasks. However, it should be noted that MCU core c. ADC conversions are initiated. This is done by starting accesses to Ports 0 and 2 (which are being used by the DMA single/continuous conversions, starting Timer 2 running controller) are gated “OFF” during ADC DMA mode of operation. for Timer 2 conversions or by receiving an external trigger. This means that even though the instruction that accesses the external Ports 0 or 2 will appear to execute, no data will be seen When the DMA conversions are completed, the ADC interrupt at these external Ports as a result. bit ADCI is set by hardware and the external SRAM contains the new ADC conversion results as shown in Figure 12. It should be The MicroConverter core can be configured with an interrupt noted that no result is written to the last two memory locations. to be triggered by the DMA controller when it has finished filling the requested block of RAM with ADC results, allowing When the DMA mode logic is active it is responsible for storing the service routine for this interrupt to post process data without the ADC results away from both the user and ADuC812 core any real-time timing constraints. logic. As it writes the results of the ADC conversions to external memory, it takes over the external memory interface from the core. The Offset and Gain Calibration Coefficients Thus, any core instructions that access the external memory The ADuC812 has two ADC calibration coefficients, one for offset while DMA mode is enabled will not get access to it. The core calibration and one for gain calibration. Both the offset and gain will execute the instructions and they will take the same time to calibration coefficients are 14-bit words, located in the Special execute, but they will not gain access to the external memory. Function Register (SFR) area. The offset calibration coefficient is divided into ADCOFSH (6 bits) and ADCOFSL (8 bits) and

REV. C –17–

, the gain calibration coefficient is divided into ADCGAINH (6 bits) EPROM EEPROM and ADCGAINL (8 bits).The offset calibration coefficient com- TECHNOLOGY TECHNOLOGY pensates for dc offset errors in both the ADC and the input signal. Increasing the offset coefficient compensates for positive offset, SPACE EFFICIENT/ IN-CIRCUIT DENSITY REPROGRAMMABLE and effectively pushes the ADC Transfer Function DOWN. Decreasing the offset coefficient compensates for negative offset, FLASH/EE MEMORY and effectively pushes the ADC Transfer Function UP. The TECHNOLOGY maximum offset that can be compensated is typically ±5% of Figure 14. Flash Memory Development VREF, which equates to typically ±125 mV with a 2.5 V reference. Overall, Flash/EE memory represents a step closer to the ideal Similarly, the gain calibration coefficient compensates for dc gain memory device that includes nonvolatility, in-circuit programma- errors in both the ADC and the input signal. bility, high density and low cost. Incorporated in the ADuC812, Increasing the gain coefficient compensates for a smaller analog Flash/EE memory technology allows the user to update program input signal range and scales the ADC Transfer Function UP, code space in-circuit without replacing one-time programmable effectively increasing the slope of the transfer function. Decreasing (OTP) devices at remote operating nodes. the gain coefficient, compensates for a larger analog input signal Flash/EE Memory and the ADuC812 range and scales the ADC Transfer Function DOWN, effectively The ADuC812 provides two arrays of Flash/EE memory for user decreasing the slope of the transfer function. The maximum analog applications. 8K bytes of Flash/EE Program space are provided input signal range for which the gain coefficient can compensate on-chip to facilitate code execution without any external discrete is 1.025 VREF and the minimum input range is 0.975 VREF, ROM device requirements. The program memory can be pro- which equates to ±2.5% of the reference voltage. grammed using conventional third party memory programmers. Calibration This array can also be programmed in-circuit, using the serial Each ADuC812 is calibrated in the factory prior to shipping and download mode provided. the offset and gain calibration coefficients are stored in a hidden A 640-Byte Flash/EE Data Memory space is also provided on-chip area of FLASH/EE memory. Each time the ADuC812 powers up, as a general purpose nonvolatile scratchpad area. User access an internal power-on configuration routine, copies these coefficients to this area is via a group of six SFRs. into the offset and gain calibration registers in the SFR area. ADuC812 Flash/EE Memory Reliability The MicroConverter ADC accuracy may vary from system to sys- The Flash/EE Program and Data Memory arrays on the ADuC812 tem due to board layout, grounding, clock speed, etc. To get the are fully qualified for two key Flash/EE memory characteristics, best ADC accuracy in your system, perform the software calibration namely Flash/EE Memory Cycling Endurance and Flash/EE routine described in technical note, uC005 available from the Memory Data Retention. MicroConverter homepage at www.analog.com/microconverter. Endurance quantifies the ability of the Flash/EE memory to be NONVOLATILE FLASH MEMORY cycled through many Program, Read, and Erase cycles. In real Flash Memory Overview terms, a single endurance cycle is composed of four independent, The ADuC812 incorporates Flash memory technology on-chip sequential events. These events are defined as: to provide the user with a nonvolatile, in-circuit reprogram- a. Initial Page Erase Sequence mable, code and data memory space. b. Read/Verify Sequence Flash/EE memory is a relatively new type of nonvolatile memory c. Byte Program Sequence technology based on a single transistor cell architecture. d. Second Read/Verify Sequence This technology is basically an outgrowth of EPROM technology In reliability qualification, every byte in the program and data and was developed in the late 1980s. Flash/EE memory takes the Flash/EE memory is cycled from 00 hex to FFhex until the flexible in-circuit reprogrammable features of EEPROM and first fail is recorded signifying the endurance limit of the on-chip combines them with the space efficient/density features of EPROM Flash/EE memory. (see Figure 14). As indicated in the specification pages of this data sheet, the Because Flash/EE technology is based on a single transistor cell ADuC812 Flash/EE Memory Endurance qualification has been architecture, a Flash memory array, like EPROM, can be imple- carried out in accordance with JEDEC Specification A117 over mented to achieve the space efficiencies or memory densities the industrial temperature range of –40°C, +25°C, and +85°C. required by a given design. The results allow the specification of a minimum endurance figure Like EEPROM, Flash memory can be programmed in-system over supply and temperature of 10,000 cycles, with an endurance at a byte level, although it must first be erased in page blocks. figure of 50,000 cycles being typical of operation at 25°C. Thus, Flash memory is often and more correctly referred to as Retention quantifies the ability of the Flash/EE memory to retain Flash/EE memory. its programmed data over time. Again, the ADuC812 has been qualified in accordance with the formal JEDEC Retention Lifetime Specification (A117) at a specific junction temperature (TJ = 55°C). As part of this qualification procedure, the Flash/EE memory is cycled to its specified endurance limit described above, before data retention is characterized. This means that the Flash/EE memory is guaranteed to retain its data for its full specified retention lifetime every time the Flash/EE memory is reprogrammed. –18– REV. C, Using the Flash/EE Program Memory Using the Flash/EE Data Memory This 8K Byte Flash/EE Program Memory array is mapped The user Flash/EE data memory array consists of 640 bytes that into the lower 8K bytes of the 64K bytes program space addres- are configured into 160 (Page 00H to Page 9FH), 4-byte pages sable by the ADuC812 and will be used to hold user code in as shown in Figure 16. typical applications. 9FH BYTE 1 BYTE 2 BYTE 3 BYTE 4 The program memory array can be programmed in one of two modes, namely: Serial Downloading (In-Circuit Programming) As part of its embedded download/debug kernel, the ADuC812 facilitates serial code download via the standard UART serial port. Serial download mode is automatically entered on power-up if the external pin, PSEN, is pulled low through an external resistor as shown in Figure 15. Once in this mode, the user can download code 00H BYTE 1 BYTE 2 BYTE 3 BYTE 4 to the program memory array while the device is sited in its target application hardware. A PC serial download executable is provided Figure 16. User Flash/EE Memory Configuration as part of the ADuC812 QuickStart development system. As with other ADuC812 user-peripherals circuits, the interface to The Serial Download protocol is detailed in a MicroConverter this memory space is via a group of registers mapped in the SFR Applications Note uC004 available from the ADI MicroConverter space. A group of four data registers (EDATA1–4) are used to website at www.analog.com/micronverter. hold the 4-byte page being accessed. EADRL is used to hold the 8-bit address of the page being accessed. Finally, ECON is an 8- bit control register that may be written with one of five Flash/EE memory access commands to trigger various read, write, erase and verify functions. These register can be summarized as follows: ECON: SFR Address: B9H Function: Controls access to 640 Bytes Flash/EE Data Space. Default: 00H EADRL: SFR Address: C6H Function: Holds the Flash/EE Data Page Address. 0 through 9F Hex Default: 00H EDATA 1–4: SFR Address: BCH to BFH respectively Function: Holds Flash/EE Data PULL PSEN LOW DURING RESET TO memory page write or page CONFIGURE THE ADuC812 FOR SERIAL DOWNLOAD MODE read data bytes.ADuC812 Default : EDATA1–4➝00H

PSEN

1k A block diagram of the SFR registered interface to the Data Flash/EE Memory array is shown in Figure 17.

Figure 15. Flash/EE Memory Serial Download Mode FUNCTION: FUNCTION: Programming HOLDS THE 8-BIT PAGE HOLDS THE 4-BYTE

ADDRESS POINTER PAGE WORD Parallel Programming 9FH BYTE 1 BYTE 2 BYTE 3 BYTE 4 The parallel programming mode is fully compatible with conventional third party Flash or EEPROM device programmers. In this mode Ports P0, P1, and P2 operate as the external data EADRL EDATA1 (BYTE 1) and address bus interface, ALE operates as the Write Enable EDATA2 (BYTE 2) strobe, and Port P3 is used as a general configuration port that EDATA3 (BYTE 3) EDATA4 (BYTE 4) configures the device for various program and erase operations 00H BYTE 1 BYTE 2 BYTE 3 BYTE 4 during parallel programming. ECON COMMAND The high voltage (12 V) supply required for Flash programming INTERPRETER LOGIC is generated using on-chip charge pumps to supply the high voltage program lines. FUNCTION: ECON FUNCTION:HOLDS COMMAND WORD INTERPRETS THE FLASH COMMAND WORD The complete parallel programming specification is available on the MicroConverter homepage at www.analog.com/microconverter. Figure 17. User Flash/EE Memory Control and

Configuration REV. C –19–

, ECON—Flash/EE Memory Control SFR Using the Flash/EE Memory Interface This SFR acts as a command interpreter and may be written As with all Flash/EE memory architectures, the array can be pro- with one of five command modes to enable various read, pro- grammed in system at a byte level, although it must be erased gram and erase cycles as detailed in Table VII: first, the erasure being performed in page blocks (4-byte pages in this case). Table VII. ECON–Flash/EE Memory Control Register A typical access to the Flash/EE array will involve setting up the Command Modes page address to be accessed in the EADRL SFR, configuring the Command Byte Command Mode EDATA1-4 with data to be programmed to the array (the EDATA SFRs will not be written for read accesses) and finally 01H READ COMMAND writing the ECON command word which initiates one of the six Results in four bytes being read into modes shown in Table VII. It should be noted that a given EDATA 1–4 from memory page address mode of operation is initiated as soon as the command word is contained in EADRL. written to the ECON SFR. The core microcontroller operation 02H PROGRAM COMMAND on the ADuC812 is idled until the requested Program/Read or Results in four bytes (EDATA 1–4) being Erase mode is completed. written to memory page address in EADRL. In practice, this means that even though the Flash/EE memory This write command assumes the designated mode of operation is typically initiated with a two-machine cycle “write” page has been pre-erased. MOV instruction (to write to the ECON SFR), the next instruction 03H RESERVED FOR INTERNAL USE will not be executed until the Flash/EE operation is complete 03H should not be written to the (250 µs or 20 ms later). This means that the core will not respond ECON SFR. to Interrupt requests until the Flash/EE operation is complete, 04H VERIFY COMMAND although the core peripheral functions like Counter/Timers will Allows the user to verify if data in EDATA continue to count and time as configured throughout this pseudo- 1–4 is contained in page address designated idle period. by EADRL. Erase-All A subsequent read of the ECON SFR will Although the 640-byte User Flash/EE array is shipped from the result in a “zero” being read if the verification factory pre-erased, i.e., Byte locations set to FFH, it is nonethe- is valid, a nonzero value will be read to less good programming practice to include an erase-all routine indicate an invalid verification. as part of any configuration/setup code running on the ADuC812. 05H ERASE COMMAND An “ERASE-ALL” command consists of writing “06H” to the Results in an erase of the 4-byte page ECON SFR, which initiates an erase of all 640 byte locations in designated in EADRL. the Flash/EE array. This command coded in 8051 assembly 06H ERASE-ALL COMMAND would appear as: Results in erase of the full Flash/EE data MOV ECON, #06H ; Erase all Command memory 160-page (640 bytes) array. ; 20 ms Duration 07H to FFH RESERVED COMMANDS Program a Byte Commands reserved for future use. In general terms, a byte in the Flash/EE array can only be pro- grammed if it has previously been erased. To be more specific, a Flash/EE Memory Timing byte can only be programmed if it already holds the value FFH. The typical program/erase times for the Flash/EE Data Because of the Flash/EE architecture, this erasure must happen Memory are: at a page level; therefore, a minimum of four bytes (1 page) will Erase Full Array (640 Bytes) – 20 ms be erased when an erase command is initiated. A more specific Erase Single Page (4 Bytes) – 20 ms example of the Program-Byte process is shown below. In this Program Page (4 Bytes) – 250 µs example the user writes F3H into the second byte on Page Read Page (4 Bytes) – Within Single Instruction Cycle 03H of the Flash/EE Data Memory space while preserving the Flash/EE erase and program timing is derived from the master other three bytes already in this page. As the user is only required clock. When using a master clock frequency of 11.0592 MHz it is to modify one of the page bytes, the full page must be first read so not necessary to write to the ETIM registers at all. However, when that this page can then be erased without the existing data being operating at other master clock frequencies (f ), you must lost. This example, coded in 8051 assembly, would appear as:CLK change the values of ETIM1 and ETIM2 to avoid degrading data MOV EADRL, #03H ; Set Page Address Pointer Flash/EE endurance and retention. ETIM1 and ETIM2 form a MOV ECON, #01H ; Read Page 16-bit word, ETIM2 being the high byte and ETIM1 the low byte. MOV EDATA2, #0F3H ; Write New Byte The value of this 16-bit word must be set as follows to ensure MOV ECON, #05H ; Erase Page optimum data Flash/EE endurance and retention. MOV ECON, #02H ; Write Page (Program ETIM2, ETIM1 = 100 µs × f Flash/EE)CLK ETIM3 should always remain at its default value of 201 dec/C9 hex. –20– REV. C, USER INTERFACE TO OTHER ON-CHIP ADuC812 of driving 10 kΩ/100 pF. Each has two selectable ranges, 0 V to PERIPHERALS VREF (the internal bandgap 2.5 V reference) and0Vto AVDD. The following section gives a brief overview of the various Each can operate in 12-bit or 8-bit mode. Both DACs share a peripherals also available on-chip. A summary of the SFRs used to control register, DACCON, and four data registers, DAC1H/L, control and configure these peripherals is also given. DAC0H/L. It should be noted that in 12-bit asynchronous mode, DAC the DAC voltage output will be updated as soon as the DACL The ADuC812 incorporates two 12-bit, voltage output DACs data SFR has been written; therefore, the DAC data registers on-chip. Each has a rail-to-rail voltage output buffer capable should be updated as DACH first, followed by DACL. DAC Control DACCON Register SFR Address FDH Power-On Default Value 04H Bit Addressable No MODE RNG1 RNG0 CLR1 CLR0 SYNC PD1 PD0 Table VIII. DACCON SFR Bit Designations Bit Name Description 7 MODE The DAC MODE bit sets the overriding operating mode for both DACs. Set to “1” = 8-Bit Mode (Write 8 Bits to DACxL SFR). Set to “0” = 12-Bit Mode. 6 RNG1 DAC1 Range Select Bit. Set to “1” = DAC1 Range 0–VDD. Set to “0” = DAC1 Range 0–VREF. 5 RNG0 DAC0 Range Select Bit. Set to “1” = DAC0 Range 0–VDD. Set to “0” = DAC0 Range 0–VREF. 4 CLR1 DAC1 Clear Bit. Set to “0” = DAC1 Output Forced to 0 V. Set to “1” = DAC1 Output Normal. 3 CLR0 DAC0 Clear Bit. Set to “0” = DAC1 Output Forced to 0 V. Set to “1” = DAC1 Output Normal. 2 SYNC DAC0/1 Update Synchronization Bit. When set to “1” the DAC outputs update as soon as DACxL SFRs are written. The user can simultaneously update both DACs by first updating the DACxL/H SFRs while SYNC is “0.” Both DACs will then update simultaneously when the SYNC bit is set to “1.” 1 PD1 DAC1 Power-Down Bit. Set to “1” = Power-On DAC1. Set to “0” = Power-Off DAC1. 0 PD0 DAC0 Power-Down Bit. Set to “1” = Power-On DAC0. Set to “0” = Power-Off DAC0. DACxH/L DAC Data Registers Function DAC Data Registers, written by user to update the DAC output. SFR Address DAC0L (DAC0 Data Low Byte) ➝F9H; DAC1L (DAC1 Data Low Byte)➝FBH DAC0H (DAC0 Data High Byte) ➝FAH; DAC1H(DAC1 Data High Byte)➝FCH Power-On Default Value 00H ➝All four Registers Bit Addressable No ➝All four Registers The 12-bit DAC data should be written into DACxH/L right-justified such that DACL contains the lower eight bits, and the lower nibble of DACH contains the upper four bits. REV. C –21–, Using the D/A Converter VDD The on-chip D/A converter architecture consists of a resistor string DAC followed by an output buffer amplifier, the functional VDD – 50mV equivalent of which is illustrated in Figure 18. Details of the VDD – 100mV actual DAC architecture can be found in U.S. Patent Number 5969657 (www.uspto.gov). Features of this architecture include inherent guaranteed monotonicity and excellent differential linearity.

AVDD

ADuC812 100mV VREF R 50mV R OUTPUTBUFFER 0mV 000 HEX FFF HEXR8Figure 19. Endpoint Nonlinearities Due to Amplifier Saturation HIGH-Z R DISABLE The endpoint nonlinearities conceptually illustrated in Figure 19 (FROM MCU) get worse as a function of output loading. Most of the ADuC812’s R data sheet specifications assume a 10 kΩ resistive load to ground at the DAC output. As the output is forced to source or sink more current, the nonlinear regions at the top or bottom Figure 18. Resistor String DAC Functional Equivalent (respectively) of Figure 19 become larger. With larger current As illustrated in Figure 18, the reference source for each DAC is demands, this can significantly limit output voltage swing. user selectable in software. It can be either AV or V In Figure 20 and Figure 21 illustrate this behavior. It should be notedDD REF. 0-to-AVDD mode, the DAC output transfer function spans from that the upper trace in each of these figures is only valid for an0Vto the voltage at the AVDD pin. In 0-to-V mode, the output range selection of 0-to-AVDD. In 0-to-VREF mode, DACREF DAC output transfer function spans from0Vto the internal loading will not cause high-side voltage drops as long as the VREF or if an external reference is applied the voltage at the V reference voltage remains below the upper trace in the correspond-REF pin. The DAC output buffer amplifier features a true rail-to-rail ing figure. For example, if AVDD = 3 V and VREF = 2.5 V, the output stage implementation. This means that unloaded, each high-side voltage will not be affected by loads less than 5 mA. output is capable of swinging to within less than 100 mV of both But somewhere around 7 mA the upper curve in Figure 21 drops AVDD and ground. Moreover, the DAC’s linearity specification below 2.5 V (VREF) indicating that at these higher currents the (when driving a 10 kΩ resistive load to ground) is guaranteed output will not be capable of reaching VREF. through the full transfer function except codes 0 to 48, and, in 0-to-AVDD mode only, codes 3995 to 4095. Linearity degrada- 5 tion near ground and VDD is caused by saturation of the output DAC LOADED WITH 0FFF HEX amplifier, and a general representation of its effects (neglecting 4 offset and gain error) is illustrated in Figure 19. The dotted line in Figure 19 indicates the ideal transfer function, and the solid line represents what the transfer function might look like with 3 endpoint nonlinearities due to saturation of the output amplifier. Note that Figure 19 represents a transfer function in 0-to-VDD mode only. In 0-to-VREF mode (with VREF < VDD) the lower nonlinearity would be similar, but the upper portion of the transfer function would follow the “ideal” line right to the end 1 (VREF in this case, not VDD), showing no signs of endpoint lin- earity errors. DAC LOADED WITH 0000 HEX0510 15 SOURCE/SINK CURRENT – mA Figure 20. Source and Sink Current Capability with VREF = VDD = 5 V –22– REV. C OUTPUT VOLTAGE – V, 3 the DAC outputs will remain at ground potential whenever the DAC is disabled. However, each DAC output will still spike briefly when power is first applied to the chip, and again when each DAC is first enabled in software. Typical scope shots of these spikes are given in Figure 23 and Figure 24 respectively. 200s/DIV AVDD – 2V/DIV0510 15 SOURCE/SINK CURRENT – mA Figure 21. Source and Sink Current Capability with VREF = VDD = 3 V DAC OUT – 500mV/DIV To drive significant loads with the DAC outputs, external buff- ering may be required, as illustrated in Figure 22. Figure 23. DAC Output Spike at Chip Power-Up 5s/DIV, 1V/DIV 9 ADuC812 Figure 22. Buffering the DAC Outputs The DAC output buffer also features a high-impedance disable function. In the chip’s default power-on state, both DACs are disabled, and their outputs are in a high-impedance state (or “three-state”) where they remain inactive until enabled in software. Figure 24. DAC Output Spike at DAC Enable This means that if a zero output is desired during power-up or power-down transient conditions, then a pull-down resistor must be added to each DAC output. Assuming this resistor is in place, REV. C –23– OUTPUT VOLTAGE – V, WATCHDOG TIMER user program fails to set the watchdog timer refresh bits (WDR1, The purpose of the watchdog timer is to generate a device reset WDR2) within a predetermined amount of time (see PRE2–0 within a reasonable amount of time if the ADuC812 enters an bits in WDCON). The watchdog timer itself is a 16-bit counter. erroneous state, possibly due to a programming error. The Watch- The watchdog timeout interval can be adjusted via the PRE2–0 bits dog function can be disabled by clearing the WDE (Watchdog in WDCON. Full Control and Status of the watchdog timer function Enable) bit in the Watchdog Control (WDCON) SFR. When can be controlled via the watchdog timer control SFR (WDCON). enabled, the watchdog circuit will generate a system reset if the Watchdog Timer WDCON Control Register SFR Address C0H Power-On Default Value 00H Bit Addressable Yes PRE2 PRE1 PRE0 — WDR1 WDR2 WDS WDE Table IX. WDCON SFR Bit Designations Bit Name Description 7 PRE2 Watchdog Timer Prescale Bits. 6 PRE1 5 PRE0 PRE2 PRE1 PRE0 Timeout Period (ms) 00016001320106401112810025610151211010241112048 4 — Not Used. 3 WDR1 Watchdog timer refresh bits, set sequentially to refresh the watchdog. 2 WDR2 1 WDS Watchdog Status Bit. Set by the Watchdog Controller to indicate that a watchdog timeout has occurred. Cleared by writing a “0” or by an external hardware reset. It is not cleared by a watchdog reset. 1 WDE Watchdog Enable Bit. Set by user to enable the watchdog and clear its counters. Example POWER SUPPLY MONITOR To set up the watchdog timer for a timeout period As its name suggests, the Power Supply Monitor, once enabled, of 2048 ms the following code would be used. monitors both supplies (AVDD and DVDD) on the ADuC812. It MOV WDCON,#0E0h ;2.048 second will indicate when either power supply drops below one of five ;timeout period user-selectable voltage trip points from 2.63 V to 4.63 V. For correct operation of the Power Supply Monitor function, AVDD SETB WDE ;enable watchdog timer must be equal to or greater than 2.7 V. The Power Supply To prevent the watchdog timer timing out the timer Monitor function is controlled via the PSMCON SFR. If refresh bits need to be set before 2.048 seconds has elapsed. enabled via the IE2 SFR, the Power Supply Monitor will interrupt the core using the PSMI bit in the PSMCON SFR. This bit will SETB WDR1 ;refresh watchdog timer.. not be cleared until the failing power supply has returned SETB WDR2 ; ..bits must be set in this above the trip point for at least 256 ms. This ensures that the ;order power supply has fully settled before the bit is cleared. This monitor function allows the user to save working registers to avoid possible data loss due to the low supply condition, and also ensures that normal code execution will not resume until a safe supply level has been well established. The supply monitor is also protected against spurious glitches triggering the interrupt circuit. –24– REV. C, Power Supply Monitor PSMCON Control Register SFR Address DFH Power-On Default Value DCH Bit Addressable No — CMP PSMI TP2 TP1 TP0 PSF PSMEN Table X. PSMCON SFR Bit Designations Bit Name Description 7 — Not Used. 6 CMP AVDD and DVDD Comparator Bit. This is a read-only bit and directly reflects the state of the AVDD and DVDD comparators. Read “1” indicates that both AVDD and DVDD supply are above its selected trip point. Read “0” indicates that either AVDD or DVDD supply are below its selected trip point. 5 PSMI Power Supply Monitor Interrupt Bit. This bit will be set high by the MicroConverter if CMP is low, indicating low analog or digital supply. The PSMI bit can be used to interrupt the processor. Once CMPD and/or CMP return (and remain) high, a 256 ms counter is started. When this counter times out, the PSMI interrupt is cleared. PSMI can also be written by the user. However, if either comparator output is low, it is not possible for the user to clear PSMI. 4 TP2 VDD Trip Point Selection Bits. 3 TP1 2 TP0 These bits select the AVDD and DVDD trip-point voltage as follows: TP2 TP1 TP0 Selected DVDD Trip Point (V) 0004.630014.370103.080112.931002.63 1 PSF AVDD/DVDD fault indicator Read “1” indicates that the AVDD supply caused the fault condition. Read “0” indicates that the DVDD supply caused the fault condition. 0 PSMEN Power Supply Monitor Enable Bit. Set to “1” by the user to enable the Power Supply Monitor Circuit. Cleared to “0” by the user to disable the Power Supply Monitor Circuit. Example SERIAL PERIPHERAL INTERFACE To configure the PSM for a trippoint of 4.37 V, the following The ADuC812 integrates a complete hardware Serial Peripheral code would be used Interface (SPI) on-chip. SPI is an industry standard synchronous MOV PSMCON,#005h ;enable PSM with serial interface that allows eight bits of data to be synchronously ;4.37V threshold transmitted and received simultaneously, i.e., full duplex. It should SETB EA ;enable interrupts be noted that the SPI and D0/D1 Digital Output pins are shared MOV IE2,#002h ;enable PSM and therefore the user can only enable one or the other interface ;interrupt at any given time (see SPE in SPICON below). The SPI Port can If the supply voltage falls below this level, the PC would vector be configured for Master or Slave operation and typically consists to the ISR. of four pins, namely: ORG 0043h ;PSM ISR MISO (Master In, Slave Out Data I/O Pin), Pin #19 CHECK:MOV A,PSMCON ;PSMCON.5 is the The MISO (master in slave out) pin is configured as an input line ;PSM interrupt in master mode and an output line in slave mode. The MISO ;bit.. line on the master (data in) should be connected to the MISO JB ACC.5,CHECK ;..it is cleared line in the slave device (data out). The data is transferred as ;only when Vdd byte wide (8-bit) serial data, MSB first. ;has remained ;above the trip ;point for 256ms ;or more. RETI ; return only when "all's well" REV. C –25–, MOSI (Master Out, Slave In Pin), Pin #27 is transmitted on one edge of the SCLOCK signal and sampled The MOSI (master out slave in) pin is configured as an output line on the other. It is important therefore that the CPHA and CPOL in master mode and an input line in slave mode. The MOSI are configured the same for the master and slave devices. line on the master (data out) should be connected to the MOSI SS (Slave Select Input Pin), Pin #12 line in the slave device (data in). The data is transferred as byte The Slave Select (SS) input pin is shared with the ADC5 input. wide (8-bit) serial data, MSB first. In order to configure this pin as a digital input the bit must be SCLOCK (Serial Clock I/O Pin), Pin #26 cleared, e.g., CLR P1.5. The master serial clock (SCLOCK) is used to synchronize the This line is active low. Data is only received or transmitted in data being transmitted and received through the MOSI and MISO slave mode when the SS pin is low, allowing the ADuC812 to data lines. A single data bit is transmitted and received in each be used in single master, multislave SPI configurations. If SCLOCK period. Therefore, a byte is transmitted/received after CPHA = 1 then the SS input may be permanently pulled low. eight SCLOCK periods. The SCLOCK pin is configured as an With CPHA = 0 then the SS input must be driven low before output in master mode and as an input in slave mode. In master the first bit in a byte wide transmission or reception and return mode the bit-rate, polarity and phase of the clock are controlled high again after the last bit in that byte wide transmission or by the CPOL, CPHA, SPR0 and SPR1 bits in the SPICON SFR reception. In SPI Slave Mode, the logic level on the external SS (see Table XII). In slave mode the SPICON register will have to pin (Pin #13), can be read via the SPR0 bit in the SPICON SFR. be configured with the phase and polarity (CPHA and CPOL) of The following SFR registers are used to control the SPI interface. the expected input clock. In both master and slave mode the data SPI Control SPICON Register SFR Address F8H Power-On Default Value OOH Bit Addressable Yes ISPI WCOL SPE SPIM CPOL CPHA SPR1 SPR0 Table XI. SPICON SFR Bit Designations Bit Name Description 7 ISPI SPI Interrupt Bit. Set by MicroConverter at the end of each SPI transfer. Cleared directly by user code or indirectly by reading the SPIDAT SFR 6 WCOL Write Collision Error Bit. Set by MicroConverter if SPIDAT is written to while an SPI transfer is in progress. Cleared by user code. 5 SPE SPI Interface Enable Bit. Set by user to enable the SPI interface. Cleared by user to enable the D0/D1 Digital Output Pins. 4 SPIM SPI Master/Slave Mode Select Bit. Set by user to enable Master Mode operation (SCLOCK is an output). Cleared by user to enable Slave Mode operation (SCLOCK is an input). 3 CPOL* Clock Polarity Select Bit. Set by user if SCLOCK idles high. Cleared by user if SCLOCK idles low. 2 CPHA* Clock Phase Select Bit. Set by user if leading SCLOCK edge is to transmit data. Cleared by user if trailing SCLOCK edge is to transmit data. 1 SPR1 SPI Bit-Rate Select Bits. 0 SPR0 These bits select the SCLOCK rate (bit-rate) in Master Mode as follows: SPR1 SPR0 Selected Bit Rate00fOSC/401fOSC/810fOSC/3211fOSC/64 In SPI Slave Mode, i.e., SPIM = 0, the logic level on the external SS pin (Pin #12) can be read via the SPR0 bit. *The CPOL and CPHA bits should both contain the same values for master and slave devices. –26– REV. C, SPIDAT SPI Data Register SPI Interface—Master Mode Function The SPIDAT SFR is written by the In master mode, the SCLOCK pin is always an output and gener- user to transmit data over the SPI ates a burst of eight clocks whenever user code writes to the interface or read by user code to read SPIDAT register. The SCLOCK bit rate is determined by data just received by the SPI interface. SPR0 and SPR1 in SPICON. It should also be noted that the SFR Address F7H SS pin is not used in master mode. If the ADuC812 needs to Power-On Default Value 00H assert the SS pin on an external slave device, a Port digital output Bit Addressable No pin should be used. Using the SPI Interface In master mode a byte transmission or reception is initiated Depending on the configuration of the bits in the SPICON SFR by a write to SPIDAT. Eight clock periods are generated via the shown in Table XI, the ADuC812 SPI interface will transmit or SCLOCK pin and the SPIDAT byte being transmitted via MOSI. receive data in a number of possible modes. Figure 25 shows all With each SCLOCK period a data bit is also sampled via MISO. possible ADuC812 SPI configurations and the timing relation- After eight clocks, the transmitted byte will have been completely ships and synchronization between the signals involved. Also transmitted and the input byte will be waiting in the input shift shown in this figure is the SPI interrupt bit (ISPI) and how it is register. The ISPI flag will be set automatically and an interrupt triggered at the end of each byte-wide communication. will occur if enabled. The value in the shift register will be latched into SPIDAT. SCLOCK SPI Interface—Slave Mode (CPOL = 1) In slave mode the SCLOCK is an input. The SS pin must also be driven low externally during the byte communication.

SCLOCK

(CPOL = 0) Transmission is also initiated by a write to SPIDAT. In slave mode, a data bit is transmitted via MISO and a data bit is received

SS

via MOSI through each input SCLOCK period. After eight clocks, SAMPLE INPUT the transmitted byte will have been completely transmitted and the DATA OUTPUT ? MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB input byte will be waiting in the input shift register. The ISPI flag will be set automatically and an interrupt will occur if enabled. The value in the shift register will be latched into SPIDAT only ISPI FLAG when the transmission/reception of a byte has been completed. SAMPLE INPUT The end of transmission occurs after the eighth clock has been DATA OUTPUT received if CPHA = 1, or when SS returns high if CPHA = 0.MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB ? ISPI FLAG

Figure 25. SPI Timing, All Modes

INTERFACE TO D0 AND D1 DIGITAL OUTPUTS The ADuC812 has two additional digital output pins D0 and D1. They share these pins with the on-chip SPI interface and therefore the user can only enable one or the other interface at any given time (see SPE in SPICON previously). D1 (Pin 27) Digital Output Pin D0 (Pin 26) Digital Output Pin DCON Control Register SFR Address E8H Power-On Default Value 00H Bit Addressable Yes D1 D1EN D0 D0EN Table XII. DCON SFR Bit Designations Bit Name Description 7 D1 Data written to this bit will be outputted on the D1 pin if D1EN is set. 6 D1EN Set to enable the D1 pin as an output. 5 D0 Data written to this bit will be outputted on the D0 pin if D0EN is set. 3 D0EN Set to enable the D0 pin as an output.

REV. C –27–

(CPHA = 0) (CPHA = 1), 8051-COMPATIBLE ON-CHIP PERIPHERALS Port 3 is a bidirectional port with internal pull-ups directly This section gives a brief overview of the various secondary controlled via the P3 SFR (SFR address = B0 hex). Port 3 pins peripheral circuits that are also available to the user on-chip. that have 1s written to them are pulled high by the internal pull- These remaining functions are fully 8051-compatible and are ups and in that state they can be used as inputs. As inputs, Port controlled via standard 8051 SFR bit definitions. 3 pins being pulled externally low will source current because of Parallel I/O Ports 0–3 the internal pull-ups. Port 3 pins also have various secondary The ADuC812 uses four input/output ports to exchange data with functions described in Table XIV. external devices. In addition to performing general-purpose I/O, some ports are capable of external memory operations; others are Table XIV. Port 3, Alternate Pin Functions multiplexed with an alternate function for the peripheral features Pin Alternate Function on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. P3.0 RXD (UART Input Pin) (or Serial Data I/O in Mode 0) Port 0 is an 8-bit open drain bidirectional I/O port that is directly P3.1 TXD (UART Output Pin) controlled via the P0 SFR (SFR address = 80 hex). Port 0 pins (or Serial Clock Output in Mode 0) that have 1s written to them via the Port 0 SFR will be configured P3.2 INT0 (External Interrupt 0) as open drain and will therefore float. In that state, Port 0 pins can P3.3 INT1 (External Interrupt 1) be used as high impedance inputs. An external pull-up resistor P3.4 T0 (Timer/Counter 0 External Input) will be required on Port 0 outputs to force a valid logic high P3.5 T1 (Timer/Counter 1 External Input) level externally. Port 0 is also the multiplexed low-order address P3.6 WR (External Data Memory Write Strobe) and data bus during accesses to external program or data memory. P3.7 RD (External Data Memory Read Strobe) In this application it uses strong internal pull-ups when emitting 1s. Port 1 is also an 8-bit port directly controlled via the P1 SFR The alternate functions of P1.0, P1.1, P1.5 and Port 3 pins can (SFR address = 90 hex). Port 1 is an input only port. Port 1 only be activated if the corresponding bit latch in the P1 and digital output capability is not supported on this device. Port P3 SFRs contains a 1. Otherwise, the port pin is stuck at 0. 1 pins can be configured as digital inputs or analog inputs. Timers/Counters By (power-on) default these pins are configured as Analog Inputs, The ADuC812 has three 16-bit Timer/Counters: Timer 0, i.e., “1” written in the corresponding Port 1 register bit. To Timer 1, and Timer 2. The Timer/Counter hardware has been configure any of these pins as digital inputs, the user should write included on-chip to relieve the processor core of the overhead a “0” to these port bits to configure the corresponding pin as a inherent in implementing timer/counter functionality in software. high impedance digital input. Each Timer/Counter consists of two 8-bit registers THx and These pins also have various secondary functions described in TLx (x = 0, 1 and 2). All three can be configured to operate Table XIII. either as timers or event counters. In “Timer” function, the TLx register is incremented every machine Table XIII. Port 1, Alternate Pin Functions cycle. Thus, think of it as counting machine cycles. Since a machine cycle consists of 12 core clock periods, the maximum Pin Alternate Function count rate is 1/12 of the core clock frequency. P1.0 T2 (Timer/Counter 2 External Input) In “Counter” function, the TLx register is incremented by a 1-to-0 P1.1 T2EX (Timer/Counter 2 Capture/Reload Trigger) transition at its corresponding external input pin, T0, T1, or T2. P1.5 SS (Slave Select for the SPI Interface) In this function, the external input is sampled during S5P2 of every machine cycle. When the samples show a high in one cycle and Port 2 is a bidirectional port with internal pull-up resistors directly a low in the next cycle, the count is incremented. The new count controlled via the P2 SFR (SFR address = A0 hex). Port 2 pins value appears in the register during S3P1 of the cycle following the that have 1s written to them are pulled high by the internal pull-up one in which the transition was detected. Since it takes two machine resistors and, in that state, they can be used as inputs. As inputs, cycles (24 core clock periods) to recognize a 1-to-0 transition, Port 2 pins being pulled externally low will source current because the maximum count rate is 1/24 of the core clock frequency. of the internal pull-up resistors. Port 2 emits the high order There are no restrictions on the duty cycle of the external input address bytes during fetches from external program memory signal, but to ensure that a given level is sampled at least once and middle and high order address bytes during accesses to the before it changes, it must be held for a minimum of one full 24-bit external data memory space. machine cycle. –28– REV. C, User configuration and control of all Timer operating modes is achieved via three SFRs, namely: TMOD, TCON: Control and configuration for Timers 0 and 1. T2CON: Control and configuration for Timer 2. Timer/Counter 0 and TMOD 1 Mode Register SFR Address 89H Power-On Default Value 00H Bit Addressable No Gate C/T M1 M0 Gate C/T M1 M0 Table XV. TMOD SFR Bit Designations Bit Name Description 7 Gate Timer 1 Gating Control. Set by software to enable timer/counter 1 only while INT1 pin is high and TR1 control bit is set. Cleared by software to enable timer 1 whenever TR1 control bit is set. 6 C/T Timer 1 Timer or Counter Select Bit. Set by software to select counter operation (input from T1 pin). Cleared by software to select timer operation (input from internal system clock). 5 M1 Timer 1 Mode Select Bit 1 (Used with M0 Bit). 4 M0 Timer 1 Mode Select Bit 0. M1 M000TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler. 1 0 8-Bit Auto-Reload Timer/Counter. TH1 holds a value which is to be reloaded into TL1 each time it overflows. 1 1 Timer/Counter 1 Stopped. 3 Gate Timer 0 Gating Control. Set by software to enable timer/counter 0 only while INT0 pin is high and TR0 control bit is set. Cleared by software to enable Timer 0 whenever TR0 control bit is set. 2 C/T Timer 0 Timer or Counter Select Bit. Set by software to select counter operation (input from T0 pin). Cleared by software to select timer operation (input from internal system clock). 1 M1 Timer 0 Mode Select Bit 1. 0 M0 Timer 0 Mode Select Bit 0. M1 M000TH0 operates as an 8-bit timer/counter. TL0 serves as 5-bit prescaler. 0 1 16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler. 1 0 8-Bit Auto-Reload Timer/Counter. TH0 holds a value that is to be reloaded into TL0 each time it overflows. 1 1 TL0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits. REV. C –29–, Timer/Counter 0 and TCON 1 Control Register SFR Address 88H Power-On Default Value 00H Bit Addressable Yes TF1 TR1 TF0 TR0 IE1* IT1* IE0* IT0* *These bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the external INT0 and INT1 interrupt pins. Table XVI. TCON SFR Bit Designations Bit Name Description 7 TF1 Timer 1 Overflow Flag. Set by hardware on a timer/counter 1 overflow. Cleared by hardware when the Program Counter (PC) vectors to the interrupt service routine. 6 TR1 Timer 1 Run Control Bit. Set by user to turn on timer/counter 1. Cleared by user to turn off timer/counter 1. 5 TF0 Timer 0 Overflow Flag. Set by hardware on a timer/counter 0 overflow. Cleared by hardware when the PC vectors to the interrupt service routine. 4 TR0 Timer 0 Run Control Bit. Set by user to turn on timer/counter 0. Cleared by user to turn off timer/counter 0. 3 IE1 External Interrupt 1 (INT1) Flag. Set by hardware by a falling edge or zero level being applied to external interrupt pin INT1, depending on bit IT1 state. Cleared by hardware when the when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. 2 IT1 External Interrupt 1 (IE1) Trigger Type. Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). Cleared by software to specify level-sensitive detection (i.e., zero level). 1 IE0 External Interrupt 0 (INT0) Flag. Set by hardware by a falling edge or zero level being applied to external interrupt pin INT0, depending on bit IT0 state. Cleared by hardware when the PC vectors to the interrupt service routine only if the interrupt was transition-activated. If level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. 0 IT0 External Interrupt 0 (IE0) Trigger Type. Set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). Cleared by software to specify level-sensitive detection (i.e., zero level). Timer/Counter 0 and 1 Data Registers Each timer consists of two 8-bit registers. These can be used as independent registers or combined to be a single 16-bit register depending on the timer mode configuration. TH0 and TL0 Timer 0 high byte and low byte. SFR Address = 8CH, 8AH respectively. TH1 and TL1 Timer 1 high byte and low byte. SFR Address = 8DH, 8BH respectively. –30– REV. C, TIMER/COUNTER 0 AND 1 OPERATING MODES Mode 2 (8-Bit Timer/Counter with Auto Reload) The following paragraphs describe the operating modes for timer/ Mode 2 configures the timer register as an 8-bit counter (TL0) counters 0 and 1. Unless otherwise noted, it should be assumed with automatic reload, as shown in Figure 28. Overflow from TL0 that these modes of operation are the same for timer 0 as for timer 1. not only sets TF0, but also reloads TL0 with the contents of TH0, Mode 0 (13-Bit Timer/Counter) which is preset by software. The reload leaves TH0 unchanged. Mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler. Figure 26 shows mode 0 operation. CORE 12

CLK

C/T = 0 CORE INTERRUPT CLK 12 TL0 TF0 (8 BITS) C/T = 0 C/T = 1

INTERRUPT

TL0 TH0 TF0 P3.4/T0 (5 BITS) (8 BITS)

CONTROL

C/T = 1 TR0 P3.4/T0 CONTROL RELOAD TR0 GATE TH0 P3.2/INT0 (8 BITS) GATE Figure 28. Timer/Counter 0, Mode 2 P3.2/INT0 Mode 3 (Two 8-Bit Timer/Counters)

Figure 26. Timer/Counter 0, Mode 0 Mode 3 has different effects on timer 0 and timer 1. Timer 1 in

In this mode, the timer register is configured as a 13-bit register. Mode 3 simply holds its count. The effect is the same as setting As the count rolls over from all 1s to all 0s, it sets the timer overflow TR1 = 0. Timer 0 in Mode 3 establishes TL0 and TH0 as two flag TF0. The overflow flag, TF0, can then be used to request an separate counters. This configuration is shown in Figure 29. TL0 interrupt. The counted input is enabled to the timer when TR0 = 1 uses the timer 0 control bits: C/T, Gate, TR0, INT0, and TF0. and either Gate = 0 or INT0 = 1. Setting Gate = 1 allows the timer TH0 is locked into a timer function (counting machine cycles) to be controlled by external input INT0, to facilitate pulsewidth and takes over the use of TR1 and TF1 from timer 1. Thus, TH0 measurements. TR0 is a control bit in the special function regis- now controls the “Timer 1” interrupt. Mode 3 is provided for ter TCON; Gate is in TMOD. The 13-bit register consists of all applications requiring an extra 8-bit timer or counter. eight bits of TH0 and the lower five bits of TL0. The upper three When timer 0 is in Mode 3, timer 1 can be turned on and off by bits of TL0 are indeterminate and should be ignored. Setting the switching it out of, and into, its own Mode 3, or can still be used by run flag (TR0) does not clear the registers. the serial interface as a Baud Rate Generator. In fact, it can be used, Mode 1 (16-Bit Timer/Counter) in any application not requiring an interrupt from timer 1 itself. Mode 1 is the same as Mode 0, except that the timer register is running with all 16 bits. Mode 1 is shown in Figure 27. CORE 12 CORE CLK CLK/12 C/T = 0 CORE INTERRUPT12 TL0 CLK TF0(8 BITS) C/T = 0 INTERRUPT C/T = 1 TL0 TH0 TF0 P3.4/T0 (8 BITS) (8 BITS) CONTROL TR0 C/T = 1 P3.4/T0 CONTROL GATE TR0 P3.2/INT0 GATE CORE TH0 INTERRUPTTF1 P3.2/INT0 CLK/12 (8 BITS)

Figure 27. Timer/Counter 0, Mode 1 TR1 CONTROL Figure 29. Timer/Counter 0, Mode 3 REV. C –31–

, Timer/Counter 2 T2CON Control Register SFR Address C8H Power-On Default Value 00H Bit Addressable Yes TF2 EXF2 RCLK TCLK EXEN2 TR2 CNT2 CAP2 Table XVII. T2CON SFR Bit Designations Bit Name Description 7 TF2 Timer 2 Overflow Flag. Set by hardware on a timer 2 overflow. TF2 will not be set when either RCLK or TCLK = 1. Cleared by user software. 6 EXF2 Timer 2 External Flag. Set by hardware when either a capture or reload is caused by a negative transition on T2EX and EXEN2 = 1. Cleared by user software. 5 RCLK Receive Clock Enable Bit. Set by user to enable the serial port to use timer 2 overflow pulses for its receive clock in serial port Modes 1 and 3. Cleared by user to enable timer 1 overflow to be used for the receive clock. 4 TCLK Transmit Clock Enable Bit. Set by user to enable the serial port to use timer 2 overflow pulses for its transmit clock in serial port Modes 1 and 3. Cleared by user to enable timer 1 overflow to be used for the transmit clock. 3 EXEN2 Timer 2 External Enable Flag. Set by user to enable a capture or reload to occur as a result of a negative transition on T2EX if Timer 2 is not being used to clock the serial port. Cleared by user for Timer 2 to ignore events at T2EX. 2 TR2 Timer 2 Start/Stop Control Bit. Set by user to start timer 2. Cleared by user to stop timer 2. 1 CNT2 Timer 2 Timer or Counter Function Select Bit. Set by user to select counter function (input from external T2 pin). Cleared by user to select timer function (input from on-chip core clock). 0 CAP2 Timer 2 Capture/Reload Select Bit. Set by user to enable captures on negative transitions at T2EX if EXEN2 = 1. Cleared by user to enable auto-reloads with Timer 2 overflows or negative transitions at T2EX when EXEN2 = 1. When either RCLK = 1 or TCLK = 1, this bit is ignored and the timer is forced to autoreload on Timer 2 overflow. Timer/Counter 2 Data Registers Timer/Counter 2 also has two pairs of 8-bit data registers associated with it. These are used as both timer data registers and timer capture/reload registers. TH2 and TL2 Timer 2, data high byte and low byte. SFR Address = CDH, CCH respectively. RCAP2H and RCAP2L Timer 2, Capture/Reload high byte and low byte. SFR Address = CBH, CAH respectively. –32– REV. C, Timer/Counter Operation Modes 16-Bit Capture Mode The following paragraphs describe the operating modes for timer/ In the “Capture” mode, there are again two options, which are counter 2. The operating modes are selected by bits in the T2CON selected by bit EXEN2 in T2CON. If EXEN2 = 0, then Timer 2 SFR as shown in Table XVIII. is a 16-bit timer or counter which, upon overflowing, sets bit TF2, the Timer 2 overflow bit, which can be used to generate an inter- Table XVIII. TIMECON SFR Bit Designations rupt. If EXEN2 = 1, then Timer 2 still performs the above, but a l-to-0 transition on external input T2EX causes the current value RCLK (or) TCLK CAP2 TR2 MODE in the Timer 2 registers, TL2 and TH2, to be captured into regis- 00116-Bit Autoreload ters RCAP2L and RCAP2H, respectively. In addition, the01116-Bit Capture transition at T2EX causes bit EXF2 in T2CON to be set, and1X1Baud Rate EXF2, like TF2, can generate an interrupt. The Capture ModeXX0OFF is illustrated in Figure 31. The baud rate generator mode is selected by RCLK = 1 and/or 16-Bit Autoreload Mode TCLK = 1. In “Autoreload” mode, there are two options, which are selected by bit EXEN2 in T2CON. If EXEN2 = 0, then when Timer 2 In either case, if Timer 2 is being used to generate the baud rolls over it not only sets TF2 but also causes the Timer 2 registers to rate, the TF2 interrupt flag will not occur. Hence Timer 2 inter- reload with the 16-bit value in registers RCAP2L and RCAP2H, rupts will not occur so they do not have to be disabled. In this which are preset by software. If EXEN2 = 1. Then Timer 2 mode however, the EXF2 flag can still cause interrupts and this still performs the above, but with the added feature that a 1-to-0 can be used as a third external interrupt. transition at external input T2EX will also trigger the 16-bit reload Baud rate generation will be described as part of the UART and set EXF2. The Autoreload mode is illustrated in Figure 30. serial port operation in the following pages.

CORE

CLK 12 C/T2 = 0 TL2 TH2 (8-BITS) (8-BITS) T2 C/T2 = 1 PIN CONTROL TR2

RELOAD TRANSITION DETECTOR

RCAP2L RCAP2H TF2

TIMER INTERRUPT

T2EX EXF2

PIN CONTROL

EXEN2

Figure 30. Timer/Counter 2, 16-Bit Autoreload Mode CORE

CLK 12 C/T2 = 0 TL2 TH2 (8-BITS) (8-BITS) TF2 T2 C/T2 = 1 PIN CONTROL TR2 CAPTURE TIMER TRANSITION INTERRUPT

DETECTOR

RCAP2L RCAP2H T2EX EXF2

PIN CONTROL

EXEN2

Figure 31. Timer/Counter 2, 16-Bit Capture Mode REV. C –33–

, UART SERIAL INTERFACE while the SFR interface to the UART is comprised of SBUF The serial port is full duplex, meaning it can transmit and receive and SCON, as described below. simultaneously. It is also receive-buffered, meaning it can begin SBUF receiving a second byte before a previously received byte has been The serial port receive and transmit registers are both accessed read from the receive register. However, if the first byte still has through the SBUF SFR (SFR address = 99 hex). Writing to not been read by the time reception of the second byte is com- SBUF loads the transmit register and reading SBUF accesses a plete, the first byte will be lost. The physical interface to the physically separate receive register. serial data network is via Pins RXD(P3.0) and TXD(P3.1) UART Serial Port SCON Control Register SFR Address 98H Power-On Default Value 00H Bit Addressable Yes SM0 SM1 SM2 REN TB8 RB8 TI RI Table XIX. SCON SFR Bit Designations Bit Name Description 7 SM0 UART Serial Mode Select Bits. 6 SM1 These bits select the Serial Port operating mode as follows: SM0 SM1 Selected Operating Mode00Mode 0: Shift Register, fixed baud rate (Core_Clk/2) 0 1 Mode 1: 8-bit UART, variable baud rate10Mode 2: 9-bit UART, fixed baud rate (Core_Clk/64) or (Core_Clk/32) 1 1 Mode 3: 9-bit UART, variable baud rate 5 SM2 Multiprocessor Communication Enable Bit. Enables multiprocessor communication in Modes 2 and 3. In Mode 0, SM2 should be cleared. In Mode 1, if SM2 is set, RI will not be activated if a valid stop bit was not received. If SM2 is cleared, RI will be set as soon as the byte of data has been received. In Modes 2 or 3, if SM2 is set, RI will not be activated if the received ninth data bit in RB8 is 0. If SM2 is cleared, RI will be set as soon as the byte of data has been received. 4 REN Serial Port Receive Enable Bit. Set by user software to enable serial port reception. Cleared by user software to disable serial port reception. 3 TB8 Serial Port Transmit (Bit 9). The data loaded into TB8 will be the ninth data bit that will be transmitted in Modes 2 and 3. 2 RB8 Serial port Receiver Bit 9. The ninth data bit received in Modes 2 and 3 is latched into RB8. For Mode 1 the stop bit is latched into RB8. 1 TI Serial Port Transmit Interrupt Flag. Set by hardware at the end of the eighth bit in Mode 0, or at the beginning of the stop bit in Modes 1, 2, and 3. TI must be cleared by user software. 0 RI Serial Port Receive Interrupt Flag. Set by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in Modes 1, 2, and 3. RI must be cleared by software. –34– REV. C, Mode 0: 8-Bit Shift Register Mode Mode 2: 9-Bit UART with Fixed Baud Rate Mode 0 is selected by clearing both the SM0 and SM1 bits in the Mode 2 is selected by setting SM0 and clearing SM1. In this SFR SCON. Serial data enters and exits through RXD. TXD mode the UART operates in 9-bit mode with a fixed baud rate. outputs the shift clock. Eight data bits are transmitted or received. The baud rate is fixed at Core_Clk/64 by default, although by Transmission is initiated by any instruction that writes to SBUF. setting the SMOD bit in PCON, the frequency can be doubled to The data is shifted out of the RXD line. The eight bits are Core_Clk/32. Eleven bits are transmitted or received, a start transmitted with the least-significant bit (LSB) first, as shown bit (0), eight data bits, a programmable ninth bit and a stop bit in Figure 32. (1). The ninth bit is most often used as a parity bit, although it can be used for anything, including a ninth data bit if required. MACHINE MACHINE MACHINE MACHINE CYCLE 1 CYCLE 2 CYCLE 7 CYCLE 8 To transmit, the eight data bits must be written into SBUF. The S1 S2 S3 S4 S5 S6 S1 S2 S3 S4 S4 S5 S6 S1 S2 S3 S4 S5 S6 ninth bit must be written to TB8 in SCON. When transmission is initiated the eight data bits (from SBUF) are loaded onto the

CORE

CLK transmit shift register (LSB first). The contents of TB8 are loaded ALE into the ninth bit position of the transmit shift register. The trans- mission will start at the next valid baud rate clock. The TI flag

RXD

(DATA OUT) DATA BIT 0 DATA BIT 1 DATA BIT 6 DATA BIT 7 is set as soon as the stop bit appears on TXD.

TXD

(SHIFT Reception for Mode 2 is similar to that of Mode 1. The eight CLOCK) data bytes are input at RXD (LSB first) and loaded onto the Figure 32. UART Serial Port Transmission, Mode 0 receive shift register. When all eight bits have been clocked in, the following events occur: Reception is initiated when the receive enable bit (REN) is 1 and the receive interrupt bit (RI) is 0. When RI is cleared the data is The eight bits in the receive shift register are latched into SBUF. clocked into the RXD line and the clock pulses are output from The ninth data bit is latched into RB8 in SCON. the TXD line. The Receiver interrupt flag (RI) is set. Mode 1: 8-Bit UART, Variable Baud Rate This will be the case if, and only if, the following conditions are Mode 1 is selected by clearing SM0 and setting SM1. Each met at the time the final shift pulse is generated: data byte (LSB first) is preceded by a start bit (0) and followed by a stop bit (1). Therefore 10 bits are transmitted on TXD or RI = 0, and received on RXD. The baud rate is set by the Timer 1 or Timer 2 Either SM2 = 0, or SM2 = 1 and the received stop bit = 1. overflow rate, or a combination of the two (one for transmission If either of these conditions is not met, the received frame is and the other for reception). irretrievably lost, and RI is not set. Transmission is initiated by writing to SBUF. The “write to Mode 3: 9-Bit UART with Variable Baud Rate SBUF” signal also loadsa1(stop bit) into the ninth bit position Mode 3 is selected by setting both SM0 and SM1. In this mode of the transmit shift register. The data is output bit by bit the 8051 UART serial port operates in 9-bit mode with a variable until the stop bit appears on TXD and the transmit interrupt baud rate determined by either Timer 1 or Timer 2. The opera- flag (TI) is automatically set as shown in Figure 33. tion of the 9-bit UART is the same as for Mode 2 but the baud rate can be varied as for Mode 1. START STOP BIT

BIT

D0 D1 D2 D3 D4 D5 D6 D7 In all four modes, transmission is initiated by any instruction that TXD uses SBUF as a destination register. Reception is initiated in Mode 0 TI by the condition RI = 0 and REN = 1. Reception is initiated in (SCON.1) the other modes by the incoming start bit if REN = 1. SET INTERRUPT I.E., READY FOR MORE DATA UART Serial Port Baud Rate Generation Figure 33. UART Serial Port Transmission, Mode 0 Mode 0 Baud Rate Generation The baud rate in Mode 0 is fixed: Reception is initiated when a 1-to-0 transition is detected on RXD. Assuming a valid start bit was detected, character reception M ode 0 Baud Rate = (Core Clock Frequency 12) continues. The start bit is skipped and the eight data bits are Mode 2 Baud Rate Generation clocked into the serial port shift register. When all eight bits have The baud rate in Mode 2 depends on the value of the SMOD bit been clocked in, the following events occur: The eight bits in the in the PCON SFR. If SMOD = 0, the baud rate is 1/64 of the core receive shift register are latched into SBUF The ninth bit (Stop clock. If SMOD = 1, the baud rate is 1/32 of the core clock: bit) is clocked into RB8 in SCON. The Receiver interrupt flag (RI) is set if, and only if, the following conditions are met at the Mode 2 Baud Rate = (2SMOD 64) × (Core Clock Frequency) time the final shift pulse is generated: RI = 0, and either SM2 = 0, or SM2 = 1 and the received stop bit = 1. Mode 1 and 3 Baud Rate Generation The baud rates in Modes 1 and 3 are determined by the overflow If either of these conditions is not met, the received frame is rate in Timer 1 or Timer 2, or both (one for transmit and the irretrievably lost, and RI is not set. other for receive). REV. C –35–, Timer 1 Generated Baud Rates Modes 1and 3 Baud Rate = When Timer 1 is used as the baud rate generator, the baud rates in Modes 1 and 3 are determined by the Timer 1 overflow rate and (1 16) × (Timer 2 Overflow Rate ) the value of SMOD as follows: Therefore, when Timer 2 is used to generate baud rates, the Modes 1and 3 Baud Rate = timer increments every two clock cycles and not every core ( SMOD ) ( ) machine cycle as before. Hence, it increments six times faster2 32 × Timer 1Overflow Rate than Timer 1, and therefore baud rates six times faster are pos- sible. Because Timer 2 has 16-bit autoreload capability, very The Timer 1 interrupt should be disabled in this application. The low baud rates are still possible. Timer itself can be configured for either timer or counter opera- tion, and in any of its three running modes. In the most typical Timer 2 is selected as the baud rate generator by setting the TCLK application, it is configured for timer operation, in the Autoreload and/or RCLK in T2CON. The baud rates for transmit and receive mode (high nibble of TMOD = 0010 Binary). In that case, the baud can be simultaneously different. Setting RCLK and/or TCLK puts rate is given by the formula: Timer 2 into its baud rate generator mode as shown in Figure 34. In this case, the baud rate is given by the formula: Modes 1and 3 Baud Rate = (2SMOD 32) × (Core Clock (12 × [256 − TH1])) Modes 1and 3 Baud Rate = (Core Clk) (32 × [65536 − (RCAP2H , RCAP2L)]) Table XX shows some commonly-used baud rates and how they might be calculated from a core clock frequency of 11.0592 MHz Table XXI shows some commonly used baud rates and how they and 12 MHz. Generally speaking, a 5% error is tolerable might be calculated from a core clock frequency of 11.0592 MHz using asynchronous (start/stop) communications. and 12 MHz. Table XX. Commonly-Used Baud Rates, Timer 1 Table XXI. Commonly Used Baud Rates, Timer 2 Ideal Core SMOD TH1-Reload Actual % Ideal Core RCAP2H RCAP2L Actual % Baud CLK Value Value Baud Error Baud CLK Value Value Baud Error 9600 12 1 –7 (F9h) 8929 7 19200 12 –1 (FFh) –20 (ECh) 19661 2.4 19200 11.0592 1 –3 (FDh) 19200 0 9600 12 –1 (FFh) –41 (D7h) 9591 0.1 9600 11.0592 0 –3 (FDh) 9600 0 2400 12 –1 (FFh) –164 (5Ch) 2398 0.1 2400 11.0592 0 –12 (F4h) 2400 0 1200 12 –2 (FEh) –72 (B8h) 1199 0.1 19200 11.0592 –1 (FFh) –18 (EEh) 19200 0 Timer 2 Generated Baud Rates 9600 11.0592 –1 (FFh) –36 (DCh) 9600 0 Baud rates can also be generated using Timer 2. Using Timer 2 is 2400 11.0592 –1 (FFh) –144 (70h) 2400 0 similar to using Timer 1 in that the timer must overflow 16 times 1200 11.0592 –2 (FFh) –32 (E0h) 1200 0 before a bit is transmitted/received. Because Timer 2 has a 16-bit Autoreload mode a wider range of baud rates is possible using Timer 2. TIMER 1

OVERFLOW

NOTE: OSCILLATOR FREQUENCY 2 IS DIVIDED BY 2, NOT 12. 0 1 CORE CONTROL SMOD CLK 2 C/T2 = 0 TIMER 2 TL2 TH2 OVERFLOW10(8-BITS) (8-BITS) RCLK T2 C/T2 = 1 PIN 16

RX CLOCK

1 0 TR2 TCLK

RELOAD

16 TX

CLOCK

RCAP2L RCAP2H NOTE: AVAILABILITY OF ADDITIONAL EXTERNAL INTERRUPT T2EX EXF TIMER 2 PIN 2 INTERRUPT

CONTROL TRANSITION DETECTOR

EXEN2 Figure 34. Timer 2, UART Baud Rates –36– REV. C, INTERRUPT SYSTEM The ADuC812 provides a total of nine interrupt sources with two priority levels. The control and configuration of the interrupt system is carried out through three Interrupt-related SFRs. IE Interrupt Enable Register IP Interrupt Priority Register IE2 Secondary Interrupt Enable Register Interrupt Enable IE Register SFR Address A8H Power-On Default Value 00H Bit Addressable Yes EA EADC ET2 ES ET1 EX1 ET0 EX0 Table XXII. IE SFR Bit Designations Bit Name Description 7 EA Written by User to Enable “1” or Disable “0” All Interrupt Sources 6 EADC Written by User to Enable “1” or Disable “0” ADC Interrupt 5 ET2 Written by User to Enable “1” or Disable “0” Timer 2 Interrupt 4 ES Written by User to Enable “1” or Disable “0” UART Serial Port Interrupt 3 ET1 Written by User to Enable “1” or Disable “0” Timer 1 Interrupt 2 EX1 Written by User to Enable “1” or Disable “0” External Interrupt11ET0 Written by User to Enable “1” or Disable “0” Timer 0 Interrupt 0 EX0 Written by User to Enable “1” or Disable “0” External Interrupt 0 Interrupt Priority IP Register SFR Address B8H Power-On Default Value 00H Bit Addressable Yes PSI PADC PT2 PS PT1 PX1 PT0 PX0 Table XXIII. IP SFR Bit Designations Bit Name Description 7 PSI Written by User to Select SPI Priority (“1” = High; “0” = Low) 6 PADC Written by User to Select ADC Interrupt Priority (“1” = High; “0” = Low) 5 PT2 Written by User to Select Timer 2 Interrupt Priority (“1” = High; “0” = Low) 4 PS Written by User to Select UART Serial Port Interrupt Priority (“1” = High; “0” = Low) 3 PT1 Written by User to Select Timer 1 Interrupt Priority (“1” = High; “0” = Low) 2 PX1 Written by User to Select External Interrupt 1 Priority (“1” = High; “0” = Low) 1 PT0 Written by User to Select Timer 0 Interrupt Priority (“1” = High; “0” = Low) 0 PX0 Written by User to Select External Interrupt 0 Priority (“1” = High; “0” = Low) REV. C –37–, Secondary Interrupt IE2 Enable Register SFR Address A9H Power-On Default Value 00H Bit Addressable No — — — — — — EPSMI ESI Table XXIV. IE2 SFR Bit Designations Bit Name Description 7 — Reserved for Future Use. 6 — Reserved for Future Use. 5 — Reserved for Future Use. 4 — Reserved for Future Use. 3 — Reserved for Future Use. 2 — Reserved for Future Use. 1 EPSMI Written by User to Enable “1” or Disable “0” Power Supply Monitor Interrupt. 0 ESI Written by User to Enable “1” or Disable “0” SPI Serial Port Interrupt. Interrupt Priority Interrupt Vectors The Interrupt Enable registers are written by the user to enable When an interrupt occurs, the program counter is pushed onto individual interrupt sources, while the Interrupt Priority registers the stack and the corresponding interrupt vector address is allow the user to select one of two priority levels for each interrupt. loaded into the program counter. The Interrupt Vector Addresses An interrupt of high priority may interrupt the service routine of are shown in the Table XXVI. a low priority interrupt. If two interrupts of different priorities occur at the same time, the higher level interrupt will be served Table XXVI. Interrupt Vector Addresses first. An interrupt cannot be interrupted by another interrupt of the same priority level. If two interrupts of the same priority level Source Vector Address occur simultaneously, a polling sequence is observed as shown IE0 0003 Hex in Table XXV. TF0 000B Hex IE1 0013 Hex Table XXV. Priority within an Interrupt Level TF1 001B Hex Source Priority Description RI + TI 0023 Hex TF2 + EXF2 002B Hex PSMI 1 (Highest) Power Supply Monitor Interrupt ADCI 0033 Hex IE0 2 External Interrupt 0 ISPI 003B Hex ADCI 3 ADC Interrupt PSMI 0043 Hex TF0 4 Timer/Counter 0 Interrupt IE1 5 External Interrupt 1 TF1 6 Timer/Counter 1 Interrupt ISPI 7 SPI Interrupt RI + TI 8 Serial Interrupt TF2 + EXF2 9 (Lowest) Timer/Counter 2 Interrupt –38– REV. C, ADuC812 HARDWARE DESIGN CONSIDERATIONS External program memory (if used) must be connected to the This section outlines some of the key hardware design consider- ADuC812 as illustrated in Figure 37. Note that 16 I/O lines ations that must be addressed when integrating the ADuC812 (Ports 0 and 2) are dedicated to bus functions during external into any hardware system. program memory fetches. Port 0 (P0) serves as a multiplexed Clock Oscillator address/data bus. It emits the low byte of the program counter The clock source for the ADuC812 can come either from an (PCL) as an address, and then goes into a float state awaiting external source or from the internal clock oscillator. To use the the arrival of the code byte from the program memory. During internal clock oscillator connect a parallel resonant crystal the time that the low byte of the program counter is valid on P0, between Pins 32 and 33, and connect a capacitor from each pin the signal ALE (Address Latch Enable) clocks this byte into an to ground as shown below. address latch. Meanwhile, Port 2 (P2) emits the high byte of the program counter (PCH), then PSEN strobes the EPROM and the code byte is read into the ADuC812. ADuC812 XTAL1 ADuC812 EPROM P0 D0–D7(INSTRUCTION) TO INTERNAL TIMING CIRCUITS A0–A7 XTAL2

LATCH ALE

Figure 35. External Parallel Resonant Crystal Connections P2 A8–A15 ADuC812 PSEN OE XTAL1

EXTERNAL CLOCK SOURCE

Figure 37. External Program Memory Interface TO INTERNAL TIMING CIRCUITS Note that program memory addresses are always 16 bits wide, even XTAL2 in cases where the actual amount of program memory used is less than 64 Kbytes. External program execution sacrifices two of the Figure 36. Connecting an External Clock Source 8-bit ports (P0 and P2) to the function of addressing the program memory. While executing from external program memory, Ports 0 Whether using the internal oscillator or an external clock source, and 2 can be used simultaneously for read/write access to external the ADuC812’s specified operational clock speed range is 300 kHz data memory, but not for general-purpose I/O. to 16 MHz. The core is static, and will function all the way down to dc. But at clock speeds slower that 400 kHz the ADC Though both external program memory and external data memory will no longer function correctly. Therefore, to ensure specified are accessed by some of the same pins, the two are completely operation, use a clock frequency of at least 400 kHz and no independent of each other from a software point of view. For example, more than 16 MHz. the chip can read/write external data memory while executing from external program memory. External Memory Interface In addition to its internal program and data memories, the Figure 38 shows a hardware configuration for accessing up to ADuC812 can access up to 64 Kbytes of external program 64 Kbytes of external RAM. This interface is standard to any memory (ROM/PROM/etc.) and up to 16 Mbytes of external 8051-compatible MCU. data memory (SRAM). To select from which code space (internal or external program ADuC812 SRAM memory) to begin executing instructions, tie the EA (external P0 D0–D7 access) pin high or low, respectively. When EA is high (pulled (DATA) up to VDD), user program execution will start at address 0 of the LATCH A0–A7 internal 8 Kbytes Flash/EE code space. When EA is low (tied to

ALE

ground) user program execution will start at address 0 of the external code space. In either case, addresses above 1FFF hex P2 A8–A15 (8K) are mapped to the external space.

OE

Note that a second very important function of the EA pin is RD described in the Single Pin Emulation Mode section of this WR WE data sheet. Figure 38. External Data Memory Interface (64 K Address Space) REV. C –39–, If access to more than 64K bytes of RAM is desired, a feature The best way to implement an external POR function to meet the unique to the ADuC812 allows addressing up to 16 M bytes above requirements involves the use of a dedicated POR chip, such of external RAM simply by adding an additional latch as illustrated as the ADM809/ADM810 SOT-23 packaged PORs from Analog in Figure 39. Devices. Recommended connection diagrams for both active-high ADM810 and active-low ADM809 PORs are shown in Figure 41 ADuC812 SRAM and Figure 42, respectively. P0 D0–D7(DATA) ADuC812 POWER SUPPLY 20

LATCH

A0–A7 34 DVDD ALE 48 P2 A8–A15 POR 15 (ACTIVE HIGH) RESET

LATCH

A16–A23

Figure 41. External Active High POR Circuit

RD OE WR WE Some active-low POR chips, such as the ADM809 can be used with a manual push-button as an additional reset source as illustrated

Figure 39. External Data Memory Interface (16 M Bytes by the dashed line connection in Figure 42. Address Space)

ADuC812 In either implementation, Port 0 (P0) serves as a multiplexed POWER SUPPLY 20 address/data bus. It emits the low byte of the data pointer (DPL) as 1k 34 DVDD an address, which is latched by a pulse of ALE prior to data being placed on the bus by the ADuC812 (write operation) or the POR SRAM (read operation). Port 2 (P2) provides the data pointer (ACTIVE LOW) page byte (DPP) to be latched by ALE, followed by the data 15 RESET pointer high byte (DPH). If no latch is connected to P2, DPP is

OPTIONAL

ignored by the SRAM, and the 8051 standard of 64K byte external MANUAL data memory access is maintained. RESETPUSH-BUTTON Detailed timing diagrams of external program and data memory Figure 42. External Active Low POR Circuit read and write access can be found in the timing specification Power Supplies sections of this data sheet. The ADuC812’s operational power supply voltage range is 2.7 V Power-On Reset Operation to 5.25 V. Although the guaranteed data sheet specifications are External POR (power-on reset) circuitry must be implemented to given only for power supplies within 2.7 V to 3.6 V or ±10% of drive the RESET pin of the ADuC812. The circuit must hold the nominal5Vlevel, the chip will function equally well at any the RESET pin asserted (high) whenever the power supply power supply level between 2.7 V and 5.5 V. (DVDD) is below 2.5 V. Furthermore, VDD must remain above Separate analog and digital power supply pins (AV and DV 2.5 V for at least 10 ms before the RESET signal is deasserted DD DDrespectively) allow AV to be kept relatively free of noisy digital (low) by which time, the power supply must have reached at least DDsignals often present on the system DVDD line. However, thougha 2.7 V level. The external POR circuit must be operational you can power AV and DV from two separate supplies if down to 1.2 V or less. The timing diagram of Figure 40 illus- DD DDdesired, you must ensure that they remain within ±0.3 V of one trates this functionality under three separate events: power-up, another at all times in order to avoid damaging the chip (as per the brownout, and power-down. Notice that when RESET is asserted Absolute Maximum Ratings section of this data sheet). Therefore (high) it tracks the voltage on DVDD. These recommendations it is recommended that unless AV and DV are connected must be adhered to through the manufacturing flow of your DD DDdirectly together, you connect back-to-back Schottky diodes ADuC812-based system as well as during its normal power-on between them as shown in Figure 43. operation. Failure to adhere to these recommendations can result in permanent damage to device functionality. DIGITAL SUPPLY ANALOG SUPPLY + 10F 10F 2.5V MIN – + – DVDD ADuC812 1.2V MAX 10ms 10ms 1.2V MAX 20 MIN MIN 34 DV AVDD 5DD 0.1F 0.1F RESET 21 35 DGND AGND 6

Figure 40. External POR Timing Figure 43. External Dual-Supply Connections

–40– REV. C, As an alternative to providing two separate power supplies, the Table XXVII. Typical IDD of Core and Peripherals user can help keep AVDD quiet by placing a small series resistor and/or ferrite bead between it and DV , and then decoupling VDD = 5 V VDD = 3 VDD AVDD separately to ground. An example of this configuration is Core: shown in Figure 44. With this configuration other analog cir- (Normal Mode) (1.6 nAs × MCLK) + (0.8 nAs × MCLK) + cuitry (such as op amps, voltage reference, etc.) can be powered 6 mA 3 mA from the AVDD supply line as well. The user will still want to Core: include back-to-back Schottky diodes between AVDD and DVDD (Idle Mode) (0.75 nAs × MCLK) + (0.25 nAs × MCLK) + in order to protect from power-up and power-down transient 5 mA 3 mA conditions that could separate the two supply voltages momentarily. ADC: 1.3 mA 1.0 mA DAC (Each): 250 µA 200 µA Voltage Ref: 200 µA 150 µA DIGITAL SUPPLY + 10F BEAD 1.6V 10F Since operating DVDD current is primarily a function of clock – ADuC812 speed, the expressions for “CORE” supply current in Table XXVII 20 are given as functions of MCLK, the oscillator frequency. Plug 34 DV AVDD DD 0.1F in a value for MCLK in hertz to determine the current consumed 48 by the core at that oscillator frequency. Since the ADC and DACs 0.1F can be enabled or disabled in software, add only the currents 21 from the peripherals you expect to use. The internal voltage refer- 35 DGND AGND 6 ence is automatically enabled whenever either the ADC or at47 least one DAC is enabled. And again, do not forget to include current sourced by I/O pins, serial port pins, DAC outputs, etc., Figure 44. External Single-Supply Connections plus the additional current drawn during Flash/EE erase and Notice that in both Figure 43 and Figure 44, a large value (10 µF) program cycles. reservoir capacitor sits on DVDD and a separate 10 µF capacitor A software switch allows the chip to be switched from normal sits on AVDD. Also, local small-value (0.1 µF) capacitors are mode into idle mode, and also into full power-down mode. Below located at each VDD pin of the chip. As per standard design prac- are brief descriptions of power-down and idle modes. tice, be sure to include all of these capacitors, and ensure the smaller capacitors are close to each AV pin with trace lengths as In idle mode, the oscillator continues to run, but is gated off toDD short as possible. Connect the ground terminal of each of these the core only. The on-chip peripherals continue to receive the capacitors directly to the underlying ground plane. Finally, it clock, and remain functional. Port pins and DAC output pins should also be noted that, at all times, the analog and digital retain their states in this mode. The chip will recover from idle ground pins on the ADuC812 must be referenced to the same mode upon receiving any enabled interrupt, or on receiving a system ground reference point. hardware reset. Power Consumption In full power-down mode, the on-chip oscillator stops, and all The currents consumed by the various sections of the ADuC812 on-chip peripherals are shut down. Port pins retain their logic levels are shown in Table XXVII. The “CORE” values given represent in this mode, but the DAC output goes to a high-impedance the current drawn by DV , while the rest (“ADC,” “DAC,” state (three-state). The chip will only recover from power-downDD “voltage ref”) are pulled by the AV pin and can be disabled in mode upon receiving a hardware reset or when power is cycled.DD software when not in use. The other on-chip peripherals (watch- During full power-down mode, the ADuC812 consumes a total dog timer, power supply monitor, etc.) consume negligible current of approximately 5 µA. and are therefore lumped in with the “CORE” operating current here. Of course, the user must add any currents sourced by the parallel and serial I/O pins, and that sourced by the DAC, in order to determine the total current needed at the ADuC812’s supply pins. Also, current drawn from the DVDD supply will increase by approximately 10 mA during Flash/EE erase and program cycles. REV. C –41–, Grounding and Board Layout Recommendations In all of these scenarios, and in more complicated real-life appli- As with all high resolution data converters, special attention must cations, keep in mind the flow of current from the supplies and be paid to grounding and PC board layout of ADuC812-based back to ground. Make sure the return paths for all currents are designs in order to achieve optimum performance from the ADCs as close as possible to the paths the currents took to reach their and DAC. destinations. For example, do not power components on the Although the ADuC812 has separate pins for analog and digital analog side of Figure 45b with DVDD since that would force ground (AGND and DGND), the user must not tie these to two return currents from DVDD to flow through AGND. Also, try to separate ground planes unless the two ground planes are con- avoid digital currents flowing under analog circuitry, which could nected together very close to the ADuC812, as illustrated in the happen if the user placed a noisy digital chip on the left half simplified example of Figure 45a. In systems where digital and of the board in Figure 45c. Whenever possible, avoid large analog ground planes are connected together somewhere else discontinuities in the ground plane(s) (formed by a long trace (at the system’s power supply for example), they cannot be con- on the same layer), since they force return signals to travel a nected again near the ADuC812 since a ground loop would result. longer path. And of course, make all connections to the ground In these cases, tie the ADuC812’s AGND and DGND pins all plane directly, with little or no trace separating the pin from its to the analog ground plane, as illustrated in Figure 45b. In systems via to ground. with only one ground plane, ensure that the digital and analog If the user plans to connect fast logic signals (rise/fall time < 5 ns) components are physically separated onto separate halves of the to any of the ADuC812’s digital inputs, add a series resistor to board such that digital return currents do not flow near analog each relevant line to keep rise and fall times longer than 5 ns at circuitry and vice versa. The ADuC812 can then be placed between the ADuC812 input pins. A value of 100 Ω or 200 Ω is usually the digital and analog sections, as illustrated in Figure 45c. sufficient to prevent high-speed signals from coupling capacitively into the ADuC812 and affecting the accuracy of ADC conversions. A PLACE ANALOG PLACE DIGITAL COMPONENTS COMPONENTS HERE HERE AGND DGND B PLACE ANALOG PLACE DIGITAL COMPONENTS COMPONENTS HERE HERE AGND DGND C PLACE ANALOG PLACE DIGITAL COMPONENTS COMPONENTS HERE HERE

GND

Figure 45. System Grounding Schemes –42– REV. C, DOWNLOAD/DEBUG ENABLE JUMPER (NORMALLY OPEN) DVDD 1k DVDD 1k 2-PIN HEADER FOR EMULATION ACCESS 52 51 50 49 48 47 46 45 44 43 42 41 40 (NORMALLY OPEN) ANALOG INPUT ADC0 39 AVDD 36 DVDD AVDD DGND 35 AGND ADuC812 DVDD 34

C

V OUTPUT REF XTAL2 REF 11.0592MHz VREF XTAL1 32 DAC0 31 DAC1 30 DAC OUTPUT 29

DVDD

ADM810 NOT CONNECTED IN THIS EXAMPLE VCC RST DVDD

GND

ADM202 DVDD 9-PIN D-SUB C1+ VCC FEMALE V+ GND 1 C1– T1OUT 2 C2+ R1IN 3 C2– R1OUT 4 V– T1IN 5 T2OUT T2IN 6 R2IN R2OUT 7

Figure 46. Typical System Configuration

OTHER HARDWARE CONSIDERATIONS the PSEN pin, as shown in Figure 46. To get the ADuC812 To facilitate in-circuit programming, plus in-circuit debug and into download mode, simply connect this jumper and power- emulation options, users will want to implement some simple cycle the device (or manually reset the device, if a manual reset connection points in their hardware that will allow easy access button is available) and it will be ready to receive a new program to download, debug, and emulation modes. serially. With the jumper removed, the device will come up in In-Circuit Serial Download Access normal mode (and run the program) whenever power is cycled Nearly all ADuC812 designs will want to take advantage of the or RESET is toggled. in-circuit reprogrammability of the chip. This is accomplished by Note that PSEN is normally an output (as described in the External a connection to the ADuC812’s UART, which requires an external Memory Interface section) and it is sampled as an input only on RS-232 chip for level translation if downloading code from a the falling edge of RESET (i.e., at power-up or upon an external PC. Basic configuration of an RS-232 connection is illustrated in manual reset). Note also that if any external circuitry uninten- Figure 46 with a simple ADM202-based circuit. If users would tionally pulls PSEN low during power-up or reset events, it could rather not design an RS-232 chip onto a board, refer to the Appli- cause the chip to enter download mode and therefore fail to begin cation Note, uC006–A 4-Wire UART-to-PC Interface, (available user code execution as it should. To prevent this, ensure that no at www.analog.com/microconverter) for a simple (and zero-cost- external signals are capable of pulling the PSEN pin low, except per-board) method of gaining in-circuit serial download access for the external PSEN jumper itself. to the ADuC812. Embedded Serial Port Debugger In addition to the basic UART connections, users will also need From a hardware perspective, entry to serial port debug mode is a way to trigger the chip into download mode. This is accom- identical to the serial download entry sequence described above. plished viaa1kΩ pull-down resistor that can be jumpered onto In fact, both serial download and serial port debug modes can be thought of as essentially one mode of operation used in two different ways.

REV. C –43–

ADC7

RESET

RxD TxD

DVDD DGND DVDD DGND PSEN EA

, Note that the serial port debugger is fully contained on the ADuC812 device, (unlike “ROM monitor” type debuggers) and therefore no external memory is needed to enable in-system debug sessions. Single-Pin Emulation Mode Also built into the ADuC812 is a dedicated controller for single-pin in-circuit emulation (ICE) using standard production ADuC812 devices. In this mode, emulation access is gained by connection to a single pin, the EA pin. Normally, this pin is hard-wired either high or low to select execution from internal or external program memory space, as described earlier. To enable single-pin emulation mode, however, users will need to pull the EA pin high througha1kΩ resistor as shown in Figure 46. The emulator will then connect to the 2-pin header also shown in Figure 46. To be com- patible with the standard connector that comes with the single-pin emulator available from Accutron Limited (www.accutron.com), Figure 47. Components of the QuickStart Development use a 2-pin 0.1-inch pitch “Friction Lock” header from Molex System (www.molex.com) such as their part number 22-27-2021. Be sure to observe the polarity of this header. As represented in Figure 46, when the Friction Lock tab is at the right, the ground pin should be the lower of the two pins (when viewed from the top). Enhanced-Hooks Emulation Mode ADuC812 also supports enhanced-hooks emulation mode. An enhanced-hooks-based emulator is available from Metalink Corporation (www.metaice.com). No special hardware support for these emulators needs to be designed onto the board since these are “pod-style” emulators where users must replace the chip on their board with a header device that the emulator pod plugs into. The only hardware concern is then one of determin- ing if adequate space is available for the emulator pod to fit into the system enclosure. Typical System Configuration A typical ADuC812 configuration is shown in Figure 46. It sum- Figure 48. Typical Debug Session marizes some of the hardware considerations discussed in the previous paragraphs. Download—In-Circuit Serial Downloader The Serial Downloader is a Windows application that allows the QUICKSTART DEVELOPMENT SYSTEM user to serially download an assembled program (Intel Hex format The QuickStart Development System is a full featured, low cost file) to the on-chip program FLASH memory via the serial COM1 development tool suite supporting the ADuC812. The system port on a standard PC. Application Note, uC004 detailing this consists of the following PC-based (Windows-compatible) hard- serial download protocol is available at www.analog.com/ ware and software development tools. microconverter. Hardware: ADuC812 Evaluation Board, Plug-In DeBug—In-Circuit Debugger Power Supply and Serial Port Cable The Debugger is a Windows application that allows the user to debug code execution on silicon using the MicroConverter UART Code Development: 8051 Assembler serial port. The debugger provides access to all on-chip periph- Code Functionality: Windows Based Simulator erals during a typical debug session as well as single-step and In-Circuit Code Download: Serial Downloader break-point code execution control. In-Circuit Debugger: Serial Port Debugger ADSIM—Windows Simulator The Simulator is a Windows application that fully simulates all Miscellaneous Other: CD-ROM Documentation and the MicroConverter functionality including ADC and DAC Two Additional Prototype Devices peripherals. The simulator provides an easy-to-use, intuitive, inter- Figure 47 shows the typical components of a QuickStart face to the MicroConverter functionality and integrates many Development System. A brief description of some of the software standard debug features; including multiple breakpoints, single tools components in the QuickStart Development System is stepping; and code execution trace capability. This tool can be given below. used both as a tutorial guide to the part as well as an efficient way to prove code functionality before moving to a hardware platform. The QuickStart development tool-suite software is freely available at the Analog Devices MicroConverter website, www.analog.com/ microconverter. –44– REV. C,

TIMING SPECIFICATIONS1, 2, 3 (AVDD = DVDD = 3.0 V or 5.0 V 10%. All specifications TA = TMIN to TMAX unless otherwise noted.)

12 MHz Variable Clock

Parameter Min Typ Max Min Typ Max Unit Figure CLOCK INPUT (External Clock Driven XTAL1)

tCK XTAL1 Period 83.33 62.5 1000 ns 49 tCKL XTAL1 Width Low 20 20 ns 49 tCKH XTAL1 Width High 20 20 ns 49 tCKR XTAL1 Rise Time 20 20 ns 49 tCKF XTAL1 Fall Time 20 20 ns 49 t 4CYC ADuC812 Machine Cycle Time 1 12tCK µs

NOTES

1AC inputs during testing are driven at DVDD – 0.5 V for a Logic 1 and 0.45 V for a Logic 0. Timing measurements are made at V IH min for a Logic 1 and VIL max for a Logic 0. 2For timing purposes, a port pin is no longer floating when a 100 mV change from load voltage occurs. A port pin begins to float when a 100 mV change from the loaded VOH/VOL level occurs. 3CLOAD for Port0, ALE, PSEN outputs = 100 pF; CLOAD for all other outputs = 80 pF unless otherwise noted. 4ADuC812 Machine Cycle Time is nominally defined as MCLKIN/12. tCKH tCKR tCKL tCKF tCK

Figure 49. XTAL 1 Input

DVDD – 0.5V 0.2V + 0.9V VLOAD – 0.1VCC TIMING VLOAD – 0.1V TEST POINTS VLOAD REFERENCE VLOAD 0.2V – 0.1V POINTSCC 0.45V VLOAD + 0.1V VLOAD – 0.1V

Figure 50. Timing Waveform Characteristics REV. C –45–

, 12 MHz Variable Clock Parameter Min Max Min Max Unit Figure EXTERNAL PROGRAM MEMORY READ CYCLE tLHLL ALE Pulsewidth 127 2tCK – 40 ns 51 tAVLL Address Valid to ALE Low 43 tCK – 40 ns 51 tLLAX Address Hold After ALE Low 53 tCK – 30 ns 51 tLLIV ALE Low to Valid Instruction In 234 4tCK – 100 ns 51 tLLPL ALE Low to PSEN Low 53 tCK – 30 ns 51 tPLPH PSEN Pulsewidth 205 3tCK – 45 ns 51 tPLIV PSEN Low to Valid Instruction In 145 3tCK – 105 ns 51 tPXIX Input Instruction Hold After PSEN00ns 51 tPXIZ Input Instruction Float After PSEN 59 tCK – 25 ns 51 tAVIV Address to Valid Instruction In 312 5tCK – 105 ns 51 tPLAZ PSEN Low to Address Float 25 25 ns 51 tPHAX Address Hold after PSEN High00ns 51

MCLK

tLHLL ALE (O) tAVLL tLLPL tPLPH tLLIV tPLIV PSEN (O) t t PXIZPLAZ tLLAX tPXIX

INSTRUCTION

PORT 0 (I/O) PCL (OUT) (IN) tAVIV tPHAX PORT 2 (O) PCH Figure 51. External Program Memory Read Cycle –46– REV. C, 12 MHz Variable Clock Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY READ CYCLE tRLRH RD Pulsewidth 400 6tCK – 100 ns 52 tAVLL Address Valid After ALE Low 43 tCK – 40 ns 52 tLLAX Address Hold After ALE Low 48 tCK – 35 ns 52 tRLDV RD Low to Valid Data In 252 5tCK – 165 ns 52 tRHDX Data and Address Hold After RD00ns 52 tRHDZ Data Float After RD 97 2tCK –70 ns 52 tLLDV ALE Low to Valid Data In 517 8tCK – 150 ns 52 tAVDV Address to Valid Data In 585 9tCK – 165 ns 52 tLLWL ALE Low to RD or WR Low 200 300 3tCK – 50 3tCK + 50 ns 52 tAVWL Address Valid to RD or WR Low 203 4tCK – 130 ns 52 tRLAZ RD Low to Address Float00ns 52 tWHLH RD or WR High to ALE High 43 123 tCK – 40 6tCK – 100 ns 52

MCLK

ALE (O) tWHLH PSEN (O) tLLDV tLLWL tRLRH RD (O) tAVWL tRLDV tRHDZttLLAX tAVLL RHDX tRLAZ PORT 0 (I/O) A0–A7 (OUT) DATA (IN) tAVDV PORT 2 (O) A16–A23 A8–A15

Figure 52. External Data Memory Read Cycle REV. C –47–

, 12 MHz Variable Clock Parameter Min Max Min Max Unit Figure EXTERNAL DATA MEMORY WRITE CYCLE tWLWH WR Pulsewidth 400 6tCK – 100 ns 53 tAVLL Address Valid After ALE Low 43 tCK – 40 ns 53 tLLAX Address Hold After ALE Low 48 tCK – 35 ns 53 tLLWL ALE Low to RD or WR Low 200 300 3tCK – 50 3tCK + 50 ns 53 tAVWL Address Valid to RD or WR Low 203 4tCK – 130 ns 53 tQVWX Data Valid to WR Transition 33 tCK – 50 ns 53 tQVWH Data Setup Before WR 433 7tCK – 150 ns 53 tWHQX Data and Address Hold After WR 33 tCK – 50 ns 53 tWHLH RD or WR High to ALE High 43 123 tCK – 40 6tCK – 100 ns 53

MCLK

ALE (O) tWHLH PSEN (O) tLLWL tWLWH WR (O) tAVWL tQVWXttWHQX t LLAXAVLL tQVWH A0–A7 DATA PORT 2 (O) A16–A23 A8–A15 Figure 53. External Data Memory Write Cycle –48– REV. C, 12 MHz Variable Clock Parameter Min Typ Max Min Typ Max Unit Figure UART TIMING (Shift Register Mode) tXLXL Serial Port Clock Cycle Time 1.0 12tCK µs 54 tQVXH Output Data Setup to Clock 700 10tCK – 133 ns 54 tDVXH Input Data Setup to Clock 300 2tCK + 133 ns 54 tXHDX Input Data Hold After Clock00ns 54 tXHQX Output Data Hold After Clock 50 2tCK – 117 ns 54 ALE (O) tXLXL TxD0167(OUTPUT CLOCK) t SET RIQVXH OR t SET TIXHQX RxD MSB BIT6 BIT1 LSB (OUTPUT DATA) tDVXH tXHDX RxD MSB BIT6 BIT1 LSB (INPUT DATA)

Figure 54. UART Timing in Shift Register Mode REV. C –49–

, Parameter Min Typ Max Unit Figure SPI MASTER MODE TIMING (CPHA = 1) tSL SCLOCK Low Pulsewidth 330 ns 55 tSH SCLOCK High Pulsewidth 330 ns 55 tDAV Data Output Valid After SCLOCK Edge 50 ns 55 tDSU Data Input Setup Time Before SCLOCK Edge 100 ns 55 tDHD Data Input Hold Time After SCLOCK Edge 100 ns 55 tDF Data Output Fall Time 10 25 ns 55 tDR Data Output Rise Time 10 25 ns 55 tSR SCLOCK Rise Time 10 25 ns 55 tSF SCLOCK Fall Time 10 25 ns 55

SCLOCK

(CPOL = 0) tSH tSL tSR tSF

SCLOCK

(CPOL = 1) tDAV tDF tDR MOSI MSB BIT 6–1 LSB MISO MSB IN BIT 6–1 LSB IN tDSU tDHD Figure 55. SPI Master Mode Timing (CPHA = 1) –50– REV. C, Parameter Min Typ Max Unit Figure SPI MASTER MODE TIMING (CPHA = 0) tSL SCLOCK Low Pulsewidth 330 ns 56 tSH SCLOCK High Pulsewidth 330 ns 56 tDAV Data Output Valid After SCLOCK Edge 50 ns 56 tDOSU Data Output Setup Before SCLOCK Edge 150 ns 56 tDSU Data Input Setup Time Before SCLOCK Edge 100 ns 56 tDHD Data Input Hold Time After SCLOCK Edge 100 ns 56 tDF Data Output Fall Time 10 25 ns 56 tDR Data Output Rise Time 10 25 ns 56 tSR SCLOCK Rise Time 10 25 ns 56 tSF SCLOCK Fall Time 10 25 ns 56

SCLOCK

(CPOL = 0) tSH tSL tSR tSF

SCLOCK

(CPOL = 1) tDAV tDOSU tDF tDR MOSI MSB BIT 6–1 LSB MISO MSB IN BIT 6–1 LSB IN tDSU tDHD

Figure 56. SPI Master Mode Timing (CPHA = 0) REV. C –51–

, Parameter Min Typ Max Unit Figure SPI SLAVE MODE TIMING (CPHA = 1) tSS SS to SCLOCK Edge 0 ns 57 tSL SCLOCK Low Pulsewidth 330 ns 57 tSH SCLOCK High Pulsewidth 330 ns 57 tDAV Data Output Valid After SCLOCK Edge 50 ns 57 tDSU Data Input Setup Time Before SCLOCK Edge 100 ns 57 tDHD Data Input Hold Time After SCLOCK Edge 100 ns 57 tDF Data Output Fall Time 10 25 ns 57 tDR Data Output Rise Time 10 25 ns 57 tSR SCLOCK Rise Time 10 25 ns 57 tSF SCLOCK Fall Time 10 25 ns 57 tSFS SS High after SCLOCK Edge 0 ns 57

SS

tSS tSFS

SCLOCK

(CPOL = 0) tSH tSL tSR tSF

SCLOCK

(CPOL = 1) tDAV tDF tDR MISO MSB BIT 6–1 LSB MOSI MSB IN BIT 6–1 LSB IN tDSU tDHD Figure 57. SPI Slave Mode Timing (CPHA = 1) –52– REV. C, Parameter Min Typ Max Unit Figure SPI SLAVE MODE TIMING (CPHA = 0) tSS SS to SCLOCK Edge 0 ns 58 tSL SCLOCK Low Pulsewidth 330 ns 58 tSH SCLOCK High Pulsewidth 330 ns 58 tDAV Data Output Valid after SCLOCK Edge 50 ns 58 tDSU Data Input Setup Time before SCLOCK Edge 100 ns 58 tDHD Data Input Hold Time after SCLOCK Edge 100 ns 58 tDF Data Output Fall Time 10 25 ns 58 tDR Data Output Rise Time 10 25 ns 58 tSR SCLOCK Rise Time 10 25 ns 58 tSF SCLOCK Fall Time 10 25 ns 58 tDOSS Data Output Valid after SS Edge 20 ns 58 tSFS SS High after SCLOCK Edge ns 58

SS

tSS tSFS

SCLOCK

(CPOL = 0) tSH tSL tSR tSF

SCLOCK

(CPOL = 1) tDAV tDF tDR MISO MSB BIT 6–1 LSB MOSI MSB IN BIT 6–1 LSB IN tDSU tDHD Figure 58. SPI Slave Mode Timing (CPHA = 0) REV. C –53–,

OUTLINE DIMENSIONS

Dimensions shown in inches and (mm). 52-Lead Plastic Quad Flatpack (S-52) 0.094 (2.39) 0.084 (2.13) 0.557 (14.15) 0.537 (13.65)SQ 0.037 (0.95) 0.026 (0.65) 52 40 1 39 PIN 1

SEATING PLANE

TOP VIEW 0.398 (10.11) (PINS DOWN) 0.390 (9.91) SQ 0.012 (0.30) 13 27 0.006 (0.15) 14 26 0.008 (0.20) 0.006 (0.15) 0.025 (0.65) 0.014 (0.35) 0.082 (2.09) BSC 0.010 (0.25) 0.078 (1.97) –54– REV. C,

Revision History

Location Page 03/02—Data Sheet changed from REV. B to REV. C. Edits to FEATURES .1 Edits to GENERAL DESCRIPTION .1 Edits to FUNCTIONAL BLOCK DIAGRAM .1 Edits to SPECIFICATIONS .3 Edits to PIN CONFIGURATION .6 Edits to PIN FUNCTION DESCRIPTIONS .7 Edits to Figure 4 .11 Edits to SERIAL PERIPHERAL INTERFACE Section .25 Edits to TABLE XI .26 Edits to TABLE XXIII .37 Edits to TABLES XXIV, XXV, and XXVI .38 10/01—Data Sheet changed from REV. A to REV. B. Entire Data Sheet Revised .All REV. C –55–, –56– PRINTED IN U.S.A. C00208–0–3/02(C)]

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