Download: FSDH321, FSDL321 Green Mode Fairchild Power Switch (FPSTM) Features

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FSDH321, FSDL321 Green Mode Fairchild Power Switch (FPSTM) Features

• Internal Avalanche Rugged Sense FET OUTPUT POWER TABLE • Consumes only 0.65W at 240VAC & 0.3W load with 230VAC ±15%(3) 85-265VAC Advanced Burst-Mode Operation PRODUCT Adapt- Open Adapt- Open • Frequency Modulation for low EMI er(1) Frame(2) er(1) Frame(2) • Precision Fixed Operating Frequency FSDL321 11W 17W 8W 12W • Internal Start-up Circuit FSDH321 11W 17W 8W 12W • Pulse by Pulse Current Limiting • Abnormal Over Current Protection FSDL0165RN 13W 23W 11W 17W • Over Voltage Protection FSDM0265RN 16W 27W 13W 20W • Over Load Protection FSDH0265RN 16W 27W 13W 20W • Internal Thermal Shutdown Function FSDL0365RN 19W 30W 16W 24W • Auto-Restart Mode • Under Voltage Lockout FSDM0365RN 19W 30W 16W 24W • Low Operating Current (max 3mA) FSDL321L 11W 17W 8W 12W • Adjustable Peak Current Limit FSDH321L 11W 17W 8W 12W • Built-in Soft Start FSDL0165RL 13W 23W 11W 17W

Applications FSDM0265RL 16W 27W 13W 20W

FSDH0265RL 16W 27W 13W 20W • SMPS for STB, Low cost DVD FSDL0365RL 19W 30W 16W 24W • Auxiliary Power for PC • Adaptor for Charger FSDM0365RL 19W 30W 16W 24W

Description Table 1. Notes: 1. Typical continuous power in a non-ven-

tilated enclosed adapter measured at 50°C ambient. 2. The FSDx321(x stands for H, L) are integrated Pulse Width Maximum practical continuous power in an open frame Modulators (PWM) and Sense FETs specifically designed design at 50°C ambient. 3. 230 VAC or 100/115 VAC with for high performance offline Switch Mode Power Supplies doubler. (SMPS) with minimal external components. Both devices are integrated high voltage power switching regulators Typical Circuit which combine an avalanche rugged Sense FET with a cur- rent mode PWM control block. The integrated PWM con- troller features include: a fixed oscillator with frequency modulation for reduced EMI, Under Voltage Lock Out AC (UVLO) protection, Leading Edge Blanking (LEB), opti- IN DC mized gate turn-on/turn-off driver, Thermal Shut Down OUT (TSD) protection, Abnormal Over Current Protection (AOCP) and temperature compensated precision current Vstr Drain sources for loop compensation and fault protection circuitry. Ipk When compared to a discrete MOSFET and controller or PWM RCC switching converter solution, the FSDx321 reduce total Vfb Vcc Source component count, design size, weight and at the same time increase efficiency, productivity, and system reliability. Both devices are a basic platform well suited for cost effective designs of flyback converters. Figure 1. Typical Flyback Application Rev.1.0.2 ©2004 Fairchild Semiconductor Corporation,

Internal Block Diagram

Vcc Vstr Drain256,7,8 + Istart VBURL/VBURH - Soft start 8V/12V Vcc good Vcc Vref InternalVBURH Freq. Bias I ModulationB_PEAK Vcc Vcc

OSC

Idelay IVFB FB NormalSQ3PWM 2.5R GateBurstRQdriver Ipk R

LEB VSD

Vcc 1 GNDSQVovp Vcc goodRQAOCPTSD Vocp

Figure 2. Functional Block Diagram of FSDx321

,

Pin Definitions

Pin Number Pin Name Pin Function Description 1 GND Sense FET source terminal on primary side and internal control ground. Positive supply voltage input. Although connected to an auxiliary transform- er winding, current is supplied from pin 5 (Vstr) via an internal switch during 2 Vcc startup (see Internal Block Diagram section). It is not until Vcc reaches the UVLO upper threshold (12V) that the internal start-up switch opens and de- vice power is supplied via the auxiliary transformer winding. The feedback voltage pin is the non-inverting input to the PWM comparator. It has a 0.9mA current source connected internally while a capacitor and op- tocoupler are typically connected externally. A feedback voltage of 6V trig- 3 Vfb gers over load protection (OLP). There is a time delay while charging between 3V and 6V using an internal 5uA current source, which prevents false triggering under transient conditions but still allows the protection mechanism to operate under true overload conditions. Pin to adjust the current limit of the Sense FET. The feedback 0.9mA current 4 Ipk source is diverted to the parallel combination of an internal 2.8kΩ resistorand any external resistor to GND on this pin to determine the current limit. If this pin is tied to Vcc or left floating, the typical current limit will be 0.7A. This pin connects directly to the rectified AC line voltage source. At start up 5 Vstr the internal switch supplies internal bias and charges an external storagecapacitor placed between the Vcc pin and ground. Once the Vcc reaches 12V, the internal switch is disabled. The Drain pin is designed to connect directly to the primary lead of the trans- 6, 7, 8 Drain former and is capable of switching a maximum of 650V. Minimizing thelength of the trace connecting this pin to the transformer will decrease leak- age inductance.

Pin Configuration

8DIP 8LSOP GND18Drain Vcc27Drain Vfb36Drain Ipk45Vstr Figure 3. Pin Configuration (Top View),

Absolute Maximum Ratings

(Ta=25°C, unless otherwise specified) Parameter Symbol Value Unit Maximum Vstr Pin Voltage VSTR,MAX 650 V Maximum Drain Pin Voltage VDRAIN,MAX 650 V Drain-Gate Voltage (RGS=1MΩ) VDGR 650 V Gate-Source (GND) Voltage VGS ±20 V Drain Current Pulsed (1) IDM 1.5 ADC Continuous Drain Current (Tc=25°C) ID 0.7 ADC Continuous Drain Current (Tc=100°C) ID 0.32 ADC Single Pulsed Avalanche Energy (2) EAS 10 mJ Maximum Supply Voltage VCC,MAX 20 V Input Voltage Range VFB −0.3 to Vstop V Total Power Dissipation PD 1.25 W Operating Junction Temperature. TJ +150 °C Operating Ambient Temperature. TA -25 to +85 °C Storage Temperature Range. TSTG -55 to +150 °C Note: 1. Repetitive rating: Pulse width limited by maximum junction temperature 2. L = 24mH, starting Tj = 25°C,

Electrical Characteristics (Sense FET Part)

(Ta = 25°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit Sense FET SECTION Drain-Source Breakdown Voltage BVDSS VGS=0V, ID=50µA 650 720 - V Startup Voltage (Vstr) Breakdown BVSTR VCC=0V, ID=1mA 650 720 - V VDS=Max. Rating, V =0V - - 25 µAGS Zero Gate Voltage Drain Current IDSS VDS=0.8Max. Rating, VGS=0V, TC=125°C - - 200 µA Static Drain-Source on Resistance (Note) RDS(ON) VGS=10V, ID=0.5A - 14 19 Ω Forward Trans conductance (Note) gfs VDS=50V, ID=0.5A 1.0 1.3 - S Input Capacitance CISS - 162 - Output Capacitance C VGS=0V, VDS=25V,OSS f=1MHz - 18 - pF Reverse Transfer Capacitance CRSS - 3.8 - Turn on Delay Time td(on) VDD=0.5B VDSS, - 9.5 - Rise Time tr ID=1.0A - 19 - (MOSFET switching time Turn Off Delay Time td(off) is essentially - 33 - ns Fall Time tf independent ofoperating temperature) - 42 - Total Gate Charge Qg VGS=10V, ID=1.0A, (Gate-Source + Gate-Drain) V =0.5B V - 7.0 -DS DSS Gate-Source Charge Qgs (MOSFET switching time - 3.1 - is essentially nC Gate-Drain (Miller) Charge Qgd independent of operating - 0.4 - temperature) Note: 1. Pulse test: Pulse width ≤ 300µS, duty ≤ 2% 2. S = -1-

R

,

Electrical Characteristics (Control Part) (Continued)

(Ta=25°C unless otherwise specified) Parameter Symbol Condition Min. Typ. Max. Unit UVLO SECTION Start Threshold Voltage VSTART VFB=GND 11 12 13 V Stop Threshold Voltage VSTOP VFB=GND789VOSCILLATOR SECTION Initial Accuracy FOSC 90 100 110 FSDH321 kHz Frequency Modulation FMOD ±2.5 ±3 ±3.5 Initial Accuracy FOSC 45 50 55 FSDL321 kHz Frequency Modulation FMOD ±1.0 ±1.5 ±2.0 Frequency Change With Temperature (2) ∆F/∆T -25°C ≤ Ta ≤ +85°C - ±5 ±10 % FSDH321 62 67 72 % Maximum Duty Cycle Dmax FSDL321 71 77 83 % FEEDBACK SECTION Feedback Source Current IFB Ta=25°C, Vfb = 0V 0.70 0.90 1.1 mA Shutdown Feedback Voltage VSD 5.5 6.0 6.5 V Shutdown Delay Current IDELAY Ta=25°C, Vfb = 4V 3.5 5.0 6.5 µA BURST MODE SECTION VBURH 0.4 0.5 0.6 V Burst Mode Voltage VBURL Tj = 25°C 0.25 0.35 0.45 V Hysteresis - 150 - mV CURRENT LIMIT(SELF-PROTECTION)SECTION Peak Current Limit(3) ILIM Tj = 25°C 0.60 0.70 0.80 A Current Limit Delay(1) TCLD Tj = 25°C - 600 - ns SOFT START SECTION Soft Start Time TSS Vfb = 4V 10 15 20 ms PROTECTION SECTION Thermal Shutdown Temperature (1) TSD - 125 145 - °C Over Voltage Protection VOVP 18 19 20 V TOTAL STANDBY CURRENT SECTION Startup Charging Current ICH VCC=0V 0.7 0.85 1.0 mA Operating Supply Current (Control Part Only) IOP VCC = 14V, Vfb = 0V135mA Note: 1. These parameters, although guaranteed, are not 100% tested in production 2. These parameters, although guaranteed, are tested in EDS (wafer test) process 3. di/dt = 250mA/uS,

Comparison Between FSDM311 and FSDx321

Function FSDM311 FSDx321 FSDx321 Advantages Soft-Start 15mS 15mS • Gradually increasing current limit during soft-start further reduces peak current and voltage component stresses • Eliminates external components used for soft-start in most applications • Reduces or eliminates output overshoot External Current Limit not applicable Programmable of • Smaller transformer default current limit • Allows power limiting (constant over- load power) • Allows use of larger device for lower losses and higher efficiency. Frequency Modulation not applicable ±1.5KHz @50KHz • Reduced conducted EMI ±3.0KHz @100KHz Burst Mode Operation Yes-built into Yes-built into • Improve light load efficiency controller controller • Reduces no-load consumption • Transformer audible noise reduction Drain Creepage at 7.62mm 7.62mm • Greater immunity to arcing as a result Package of build-up of dust, debris and other contaminants,

Typical Performance Characteristics (Control Part)

(These characteristic graphs are normalized at Ta = 25°C) 1.20 1.20 1.00 1.00 0.80 0.80 0.60 0.60 0.40 0.40 0.20 0.20 0.00 0.00 -50 0 50 100 150 -50 0 50 100 150 Temp[℃] T emp[℃] Operating Frequency (Fosc) Frequency Modulation (FMOD) 1.20 1.20 1.00 1.00 0.80 0.80 0.60 0.60 0.40 0.40 0.20 0.20 0.00 0.00 -50 0 50 100 150 -50 0 50 100 150 Temp[℃] Temp[℃] Maximum duty cycle (Dmax) Operating supply current (Iop) 1.20 1.20 1.00 1.00 0.80 0.80 0.60 0.60 0.40 0.40 0.20 0.20 0.00 0.00 -50 0 50 100 150 -50 0 50 100 150 Temp[℃] T emp[℃] Start Threshold Voltage (Vstart) Stop Threshold Voltage (Vstop) Nomalized Normalized Normalized Normalized Normalized Normalized,

Typical Performance Characteristics (Continued)

1.20 1.20 1.00 1.00 0.80 0.80 0.60 0.60 0.40 0.40 0.20 0.20 0.00 0.00 -50 0 50 100 150 -50 0 50 100 150 Temp[℃] T emp[℃] Feedback Source Current (Ifb) Peak current limit (ILIM) 1.20 1.20 1.00 1.00 0.80 0.80 0.60 0.60 0.40 0.40 0.20 0.20 0.00 0.00 -50 0 50 100 150 -50 0 50 100 150 Temp[℃] T emp[℃] Start up Current (Istart) Startup Charging Current (Ich) 1.20 1.20 1.00 1.00 0.80 0.80 0.60 0.60 0.40 0.40 0.20 0.20 0.00 0.00 -50 0 50 100 150 -50 0 50 100 150 T emp[℃] Temp[℃] Burst peak current (Iburst) Over Voltage Protection (Vovp) Normalized Normalized Normalized Normalized Normalized Normalized,

Functional Description

1. Startup : In previous generations of Fairchild Power Vcc Vref Switches (FPSTM) the Vstr pin had an external resistor to the 2uA 0.9mA DC input voltage line. In this generation the startup resistor Vo Vfb FB is replaced by an internal high voltage current source anda3OSC D1 D2 switch that shuts off when 15mS goes by after the supply Cfb 28R voltage, Vcc, gets above 12V. The source turns back on if Vfb* Gate Vcc drops below 8V. R driver

OLP VSD

Vin,dc Istr Figure 5. Pulse width modulation (PWM) circuit Vstr Vcc UVLO <8V on 4. Protection Circuit : The FPSTM has several protective func-J-FET tions such as over load protection (OLP), over voltage pro- 15mS After UVLO start(>12V) tection (OVP), abnormal over current protection (AOCP), off under voltage lock out (UVLO) and thermal shutdown (TSD). Because these protection circuits are fully integrated inside the IC without external components, the reliability is improved without increasing cost. Once the fault condition occurs, switching is terminated and the Sense FET remains Figure 4. High voltage current source off. This causes Vcc to fall. When Vcc reaches the UVLO stop voltage, 8V, the protection is reset and the internal high voltage current source charges the Vcc capacitor via the Vstr pin. When Vcc reaches the UVLO start voltage,12V, the 2. Feedback Control : The FSDx321 employs current mode FPSTM resumes its normal operation. In this manner, the control, shown in figure 5. An opto-coupler (such as the auto-restart can alternately enable and disable the switching H11A817A) and shunt regulator (such as the KA431) are of the power Sense FET until the fault condition is elimi- typically used to implement the feedback network. Compar- nated. ing the feedback voltage with the voltage across the Rsense resistor plus an offset voltage makes it possible to control the switching duty cycle. When the reference pin voltage of the KA431 exceeds the internal reference voltage of 2.5V, the 4.1 Over Load Protection (OLP) : Overload is defined as the H11A817A LED current increases, thus pulling down the load current exceeding a pre-set level due to an unexpected feedback voltage and reducing the duty cycle. This event event. In this situation, the protection circuit should be acti- typically happens when the input voltage is increased or the vated in order to protect the SMPS. However, even when the output load is decreased. SMPS is in the normal operation, the over load protection circuit can be activated during the load transition. In order to avoid this undesired operation, the over load protection cir- cuit is designed to be activated after a specified time to deter- 3. Leading edge blanking (LEB) : At the instant the internal mine whether it is a transient situation or an overload Sense FET is turned on, there usually exists a high current situation. In conjunction with the Ipk current limit pin (if spike through the Sense FET, caused by the primary side used) the current mode feedback path would limit the current capacitance and secondary side rectifier diode reverse recov- in the Sense FET when the maximum PWM duty cycle is ery. Excessive voltage across the Rsense resistor would lead attained. If the output consumes more than this maximum to incorrect feedback operation in the current mode PWM power, the output voltage (Vo) decreases below the set volt- control. To counter this effect, the FPSTM employs a leading age. This reduces the current through the opto-coupler LED, edge blanking (LEB) circuit. This circuit inhibits the PWM which also reduces the opto-coupler transistor current, thus comparator for a short time (TLEB) after the Sense FET is increasing the feedback voltage (Vfb). If Vfb exceeds 3V, the feed- turned on. back input diode is blocked and the 5uA Idelay current source starts to charge Cfb slowly up to Vcc. In this condition, Vfb continues increasing until it reaches 6V, when the switching operation is ter- minated as shown in figure 6. The delay time for shutdown is the time required to charge Cfb from 3V to 6V with 5uA., enabled and monitors the current through the sensing resis- tor. The voltage across the resistor is then compared with a preset AOCP level. If the sensing resistor voltage is greater Vcc than the AOCP level, pulse by pulse AOCP is triggered regardless of uncontrollable LEB time. Here, pulse by pulse 8V AOCP stops Sense FET within 350nS after it is activated.

OLP

6V FPS switching Following Vcc 3V 4.4 Over Voltage Protection (OVP) : In case of malfunc- tion in the secondary side feedback circuit, or feedback loop Delay current (5uA) charges the Cfb open caused by a defect of solder, the current through the t1 t2 t3 t4 opto-coupler transistor becomes almost zero. Then, Vfb t climbs up in a similar manner to the over load situation, forc- 1 V (t1) ing the preset maximum current to be supplied to the SMPS t1 = − In (1 − ); V (t1) = 3V , R = 2.8KΩ , C RC R fb = C fb _ fig .2 fb until the over load protection is activated. Because excess (V(t1+ t2) −V(t1)) energy is provided to the output, the output voltage may t2 = Cfb ;II delay = 5uA,V(t1+ t2) −V(t1) = 3V exceed the rated voltage before the over load protection is delay activated, resulting in the breakdown of the devices in the secondary side. In order to prevent this situation, an over Figure 6. Over load protection voltage protection (OVP) circuit is employed. In general, Vcc is proportional to the output voltage and the FPSTM uses Vcc instead of directly monitoring the output voltage. If 4.2 Thermal Shutdown (TSD) : The Sense FET and the con- VCC exceeds 19V, OVP circuit is activated resulting in ter- trol IC are integrated, making it easier for the control IC to mination of the switching operation. In order to avoid undes- detect the temperature of the Sense FET. When the tempera- ired activation of OVP during normal operation, Vcc should ture exceeds approximately 140°C, thermal shutdown is acti- be properly designed to be below 19V. vated. 5. Soft Start : The FPSTM has an internal soft start circuit that 4.3 Abnormal Over Current Protection (AOCP) : increases the feedback voltage together with the Sense FET current slowly after it starts up. The typical soft start time is 15msec, as shown in figure 8, where progressive increments of Sense FET current are allowed during the start-up phase.

PWM

COMPARATOR The pulse width to the power switching device is progres- Vfb CLK sively increased to establish the correct working conditions LEB Out Driver Drain for transformers, inductors, and capacitors. The voltage on Vsense the output capacitors is progressively increased with the AOCP intention of smoothly establishing the required output volt- COMPARATORSQage. It also helps to prevent transformer saturation and R reduce the stress on the secondary diode. VAOCP Rsense Drain current [A] Figure 7. AOCP Function & Block 0.7A Even though the FPSTM has OLP (Over Load Protection) 0.4A and current mode PWM feedback, these are not enough to protect the FPSTM when a secondary side diode short or a transformer pin short occurs. In addition to start-up, soft- start is also activated at each restart attempt during auto- Tss restart and when restarting after latch mode is activated. The FPSTM has an internal AOCP (Abnormal Over Current Pro- tection) circuit as shown in figure 7. When the gate turn-on signal is applied to the power Sense FET, the AOCP block is, 5VDRAIN Burst Operation Burst Operation Feedback Normal OperationSWITCHGNDOFF00.5.5VVRsenseI_over00.3.3V5V Current waveform Switching OFF Switching OFF Figure 8. Soft Start Function Figure 10. Circuit for Burst Operation 6. Burst operation :In order to minimize power dissipation in standby mode, the FPSTM enters burst mode operation. 7. Frequency Modulation : EMI reduction can be accom- plished by modulating the switching frequency of a switched + power supply. Frequency modulation can reduce EMI by 0.350V.3//0..5V - spreading the energy over a wider frequency range than the 0..5V band width measured by the EMI test equipment. The Vcc amount of EMI reduction is directly related to the depth of IB_PEAK the reference frequency. As can be seen in Figure 11, the fre- Vcc Vcc quency changes from 97KHz to 100KHz (from 48.5KHz toIIFB delay FB 51.5KHz ; FSDL321)in 4mS for the FSDH321. Frequency Normal 3 PWM modulation allows the use of a cost effective inductor instead 2.5R Burst of an AC input mode choke to satisfy the requirements of

R

MOSFET world wide EMI limits. Current Internal Figure 9. Circuit for Burst operation Oscillator 103kHz As the load decreases, the feedback voltage decreases. As shown in figure 10, the device automatically enters burst mode when the feedback voltage drops below VBURH(500mV). Switching still con- Drain toSource tinues but the current limit is set to a fixed limit internally to mini- voltage mize flux density in the transformer. The fixed current limit is larger than that defined by Vfb = VBURH and therefore, Vfb is driven down further. Switching continues until the feedback this point switching Drain tovoltage drops below VBURL(350mV). At Vds Waveform stops and the output voltages start to drop at a rate dependent on the standby current load. This causes the feedback volt- 6kHz97kHz age to rise. Once it passes VBURH(500mV) switching resumes. 100kHz The feedback voltage then falls and the process repeats. Burst 103kHz mode operation alternately enables and disables switching of Turn-off the power Sense FET thereby reducing switching loss in Turn-on Standby mode. Figure 11. Frequency Modulation Waveform for FSDH321, 8. Adjusting Current limit function: As shown in fig 12, a combined 2.8KΩ internal resistance is connected into the non-inverting lead on the PWM comparator. A external resistance of Y on the current limit pin forms a parallel resis- tance with the 2.8KΩ when the internal diodes are biased by the main current source of 900uA. 5uA 900uA Feed Back 2KΩ PWM comparator Current 4 Limit 0.8KΩ AKΩ Rsense SenseFET Sense Figure 12. Peak current adjustment For example, FSDH321 has a typical Sense FET current limit (ILIM) of 0.7A. The Sense FET current can be limited to 0.5 by inserting a kΩ between the current limit pin and ground which is derived from the following equations: 0.7: 0.5 = 2.8KΩ : XKΩ , X = 2KΩ, Since X represents the resistance of the parallel network, Y can be calculated using the following equation: Y = X / (1 - (X/2.8KΩ)) ; Y = 7KΩ,

Typical application circuit

1. PC Auxiliary Power Circuit (10W Output Power) D201 L201T1 10uH 140~375 EE1625 SB360 5V VDC 10 (+/-5%) INPUT 1 C201 C203 2A R102 C101 1000uF 470uF 100kΩ 10nF 16V 16V 1W 630V27R101 680kΩ D101 1W UF 4007 D102 R103 M Vcc 1N4937 10Ω5 4 IC101 Vstr C102 FSDx321 Drain 6,7,8 47uF 3 D103 50V Vfb 1N4937 R104 2 10ΩVcc C104 GND C103 22nF 1 10uF 50V R202 6 330Ω PC301 H11A817A R203 2kΩ R201 1k C202Ω 100nF C301 R204 2.2nF IC201KA431 2kΩ 10W PC Auxiliary Power Circuit 10W PC Auxiliary Power, 150~375VDC Input Power C101, keeping the DRAIN voltage below 650 V under all supply: conditions. And R102 dissipates power to prevent rising of DRAIN Voltage caused by leakage inductance. The fre- It shows a auxiliary power for PC. Efficiency at 10W, 150/ quency modulation feature of FSDH321 allows the circuit 375VDC is ≥70%. shown to meet CISPR2AB with simple EMI filtering. The secondary is rectified and smoothed by D201. Similarly The PC application has the standard of standby power con- D102 and D103 are also rectifiers for main power control IC sumption, under 1W at the output load, 0.5W and height and FSDH321 respectively. The 5V output voltage require input voltage, 230VAC. For this the FSDH321 also has the two capacitors in parallel to meet the ripple current require- burst operating function like the any other green mode FPS ment. Switching noise filtering is provided by L201. The like FSDM0265RN or FSDM0365RN and so on. This skill output is regulated by the reference (TL431) voltage in sec- reduces the MOSFET switching numbers and power MOS- ondary. It is sensed via R203 and R204. Resistor R201 pro- FET switching loss. This design takes advantage of self pro- vides bias for TL431 and R202 sets the overall DC gain. tection without external components and high switching R2012, C202 and R203 provide loop compensation. frequency, 100kHz. The frequency makes using a small size transformer core possible. The EE16 or EE1625 can be used for 10W application. This is achieved by preventing the green FPS from switching when the input voltage goes below a level needed to main- tain output regulation, and keeping it off until the input volt- age goes above the under-voltage threshold, when the AC is turned on again. For example with the resistor, R101, 680kΩ, the threshold voltage is around 150VAC(210VDC) at the room temperature. Leakage inductance clamping is provided by R102 and, 2. Transformer Specification (10W Output Power) 1. Schematic Diagram EE1625 N 1p/2 N /2 2 10 Np N a5V N /239pNM VccN48M Vcc N5VN57N/2a p 2. Winding Specification P in ( S ! F ) W ire Tu rns W ind ingMethodNp/2 3 ! 2 0.15φ× 1 80 So leno id w ind ing Insu la tio n : Po lye s terTape t = 0 .050m m , 3Laye rs N 10 ! 75V 0 .55φ× 1 12 So leno id w ind ing Insu la tio n : Po lye s terTape t = 0 .050m m , 3Laye rsN4! 6M VCC0.20φ× 1 40 So leno id w ind ing Insu la tio n : Po lye s terTape t = 0 .050m m , 3Laye rsNp/2 2 ! 1 0.15φ× 1 80 So leno id w ind ing Insu la tio n : Po lye s terTape t = 0 .050m m , 3Laye rsNa5! 6 0.20φ× 1 34 So leno id w ind ingOute r Insu la tion : Po lyes te r Tape t = 0 .050m m , 3Laye rs 3. Electric Specification and Core and Bobbin Pin Spec. Remark Inductance 1 – 3 1.8 mH 1kHz, 1V Leakage 1 - 3 100uH 2nd side all short Core EE1625 Bobb in EE1625,

Layout Considerations

SURFACE MOUNTED COPPER AREA FOR HEAT

SINKING

DC_link Capacitor #1 : GND #2 : VCC #3 : Vfb #4 : Ipk #5 : Vstr #6 : Drain #7 : Drain - + #8 : Drain DC Y1- OUT

CAPACITOR

Figure 13. Layout Considerations for FSDx321 using 8DIP,

Package Dimensions

8DIP, Package Dimensions (Continued) 8LSOP,

Ordering Information

Product Number Package Marking Code BVDSS FOSC RDS(on) FSDH321 8DIP DH321 650V 100KHz 14Ω FSDL321 8DIP DL321 650V 50KHz 14Ω FSDH321L 8LSOP DH321 650V 100KHz 14Ω FSDL321L 8LSOP DL321 650V 50KHz 14Ω,

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support which, (a) are intended for surgical implant into the body, device or system whose failure to perform can be or (b) support or sustain life, and (c) whose failure to reasonably expected to cause the failure of the life support perform when properly used in accordance with device or system, or to affect its safety or effectiveness. instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user. www.fairchildsemi.com 10/1/04 0.0m 001 Stock#DSxxxxxxxx 2004 Fairchild Semiconductor Corporation, This datasheet has been download from: www.datasheetcatalog.com Datasheets for electronics components.]

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