Download: LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC 1. General description

LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC Rev. 05 — 9 April 2009 Product data sheet 1. General description The LPC2364/65/66/67/68 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with up to 512 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorit...
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LPC2364/65/66/67/68 Single-chip 16-bit/32-bit microcontrollers; up to 512 kB flash

with ISP/IAP, Ethernet, USB 2.0, CAN, and 10-bit ADC/DAC Rev. 05 — 9 April 2009 Product data sheet 1. General description The LPC2364/65/66/67/68 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S CPU with real-time emulation that combines the microcontroller with up to 512 kB of embedded high-speed flash memory. A 128-bit wide memory interface and a unique accelerator architecture enable 32-bit code execution at the maximum clock rate. For critical performance in interrupt service routines and DSP algorithms, this increases performance up to 30 % over Thumb mode. For critical code size applications, the alternative 16-bit Thumb mode reduces code by more than 30 % with minimal performance penalty. The LPC2364/65/66/67/68 are ideal for multi-purpose serial communication applications. They incorporate a 10/100 Ethernet Media Access Controller (MAC), USB full speed device with 4 kB of endpoint RAM (LPC2364/66/68 only), four UARTs, two CAN channels (LPC2364/66/68 only), an SPI interface, two Synchronous Serial Ports (SSP), three I2C interfaces, and an I2S interface. This blend of serial communications interfaces combined with an on-chip 4 MHz internal oscillator, SRAM of up to 32 kB, 16 kB SRAM for Ethernet, 8 kB SRAM for USB and general purpose use, together with 2 kB battery powered SRAM make these devices very well suited for communication gateways and protocol converters. Various 32-bit timers, an improved 10-bit ADC, 10-bit DAC, one PWM unit, a CAN control unit (LPC2364/66/68 only), and up to 70 fast GPIO lines with up to 12 edge or level sensitive external interrupt pins make these microcontrollers particularly suitable for industrial control and medical systems. 2. Features n ARM7TDMI-S processor, running at up to 72 MHz n Up to 512 kB on-chip flash program memory with In-System Programming (ISP) and In-Application Programming (IAP) capabilities. Flash program memory is on the ARM local bus for high performance CPU access. n 8 kB/32 kB of SRAM on the ARM local bus for high performance CPU access. n 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM. n 8 kB SRAM for general purpose DMA use also accessible by the USB. n Dual Advanced High-performance Bus (AHB) system that provides for simultaneous Ethernet DMA, USB DMA, and program execution from on-chip flash with no contention between those functions. A bus bridge allows the Ethernet DMA to access the other AHB subsystem. n Advanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored interrupts. n General Purpose DMA controller (GPDMA) on AHB that can be used with the SSP serial interfaces, the I2S port, and the Secure Digital/MultiMediaCard (SD/MMC) card port, as well as for memory-to-memory transfers., n Serial interfaces: u Ethernet MAC with associated DMA controller. These functions reside on an independent AHB. u USB 2.0 full-speed device with on-chip PHY and associated DMA controller (LPC2364/66/68 only). u Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO. u CAN controller with two channels (LPC2364/66/68 only). u SPI controller. u Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt and pins. These can be used with the GPDMA controller. u Three I2C-bus interfaces (one with open-drain and two with standard port pins). u I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA. n Other peripherals: u SD/MMC memory card interface (LPC2367/68 only). u 70 general purpose I/O pins with configurable pull-up/down resistors. u 10-bit ADC with input multiplexing among 6 pins. u 10-bit DAC. u Four general purpose timers/counters with a total of 8 capture inputs and 10 compare outputs. Each timer block has an external count input. u One PWM/timer block with support for three-phase motor control. The PWM has two external count inputs. u Real-Time Clock (RTC) with separate power pin, clock source can be the RTC oscillator or the APB clock. u 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off. u WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock. n Standard ARM test/debug interface for compatibility with existing tools. n Emulation trace module supports real-time trace. n Single 3.3 V power supply (3.0 V to 3.6 V). n Three reduced power modes: idle, sleep, and power-down. n Four external interrupt inputs configurable as edge/level sensitive. All pins on PORT0 and PORT2 can be used as edge sensitive interrupt sources. n Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt). n Two independent power domains allow fine tuning of power consumption based on needed features. n Each peripheral has its own clock divider for further power saving. n Brownout detect with separate thresholds for interrupt and forced reset. n On-chip power-on reset. n On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz. n 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as the system clock. When used as the CPU clock, does not allow CAN and USB to run. Product data sheet Rev. 05 — 9 April 2009 2 of 53, n On-chip PLL allows CPU operation up to the maximum CPU rate without the need for a high frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator. n Boundary scan for simplified board testing is available in LPC2364FET100 and LPC2368FET100 (TFBGA package). n Versatile pin function selections allow more possibilities for using on-chip peripheral functions. 3. Applications n Industrial control n Medical systems n Protocol converter n Communications 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC2364FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1 LPC2364HBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1 LPC2364FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 × 9 × 0.7 mm SOT926-1 LPC2365FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1 LPC2366FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1 LPC2367FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1 LPC2368FBD100 LQFP100 plastic low profile quad flat package; 100 leads; body 14 × 14 × 1.4 mm SOT407-1 LPC2368FET100 TFBGA100 plastic thin fine-pitch ball grid array package; 100 balls; body 9 × 9 × 0.7 mm SOT926-1 Product data sheet Rev. 05 — 9 April 2009 3 of 53, Single-chip 16-bit/32-bit microcontrollers LPC2364_65_66_67_68_5 Product data she xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx 4.1 Ordering options Table 2. Ordering options Type number Flash SRAM (kB) Ethernet USB SD/MMC GP DMA Channels Temp range (kB) Local Ethernet GP/USB RTC Total device + CAN ADC DAC261−40 °C to +85 °C261−40 °C to +125 °C261−40 °C to +85 °C - 6 1 −40 °C to +85 °C261−40 °C to +85 °C - 6 1 −40 °C to +85 °C261−40 °C to +85 °C261−40 °C to +85 °C © NXP B.V. 2009. All rights reserved. et Rev. 05 — 9 April 2009 4 of 53 bus buffers 4 kB

FIFO

LPC2364FBD100 128 8 168234 RMII yes no yes LPC2364HBD100 128 8 168234 RMII yes no yes LPC2364FET100 128 8 168234 RMII yes no yes LPC2365FBD100 256 32 168258 RMII no no yes LPC2366FBD100 256 32 168258 RMII yes no yes LPC2367FBD100 512 32 168258 RMII no yes yes LPC2368FBD100 512 32 168258 RMII yes yes yes LPC2368FET100 512 32 168258 RMII yes yes yes, 5. Block diagram XTAL1 TMS TDI trace signals XTAL2

VDDA

TRST TCK TDO RESET VDD(3V3) EXTIN0 LPC2364/65/66/67/68 128/256/ VREFSYSTEM P0, P1, P2, 8/32 kB V , V512 kB PLL SSA SSTEST/DEBUG FUNCTIONS P3, P4 SRAM FLASH VINTERFACE DD(DCDC)(3V3) system HIGH-SPEED INTERNAL RCclock GPI/O INTERNAL ARM7TDMI-S OSCILLATOR 70 PINS CONTROLLERS TOTAL SRAM FLASH

VECTORED INTERRUPT CONTROLLER

AHB2 AHB1 AHB AHB BRIDGE BRIDGE

VBUS

ETHERNET MASTER AHB TO SLAVE USB WITH 8 kB USB_D+, USB_D− RMII(8) 16 kBMAC WITH PORT AHB BRIDGE PORT 4 kB RAM

SRAM

SRAM AND DMA(2) USB_CONNECT DMA USB_UP_LED AHB TO APB BRIDGE GP DMA

CONTROLLER

EINT3 to EINT0 EXTERNAL INTERRUPTS I2SRX_CLK P0, P2 I2STX_CLK I2SRX_WS 2 × CAP0/CAP1/ 2 CAPTURE/COMPAREISINTERFACE I2STX_WS CAP2/CAP3 4 × MAT2, TIMER0/TIMER1/ I2SRX_SDA I2STX_SDA 2 × MAT0/MAT1/ TIMER2/TIMER3 MAT3 SCK, SCK0 MOSI, MOSI0 6 × PWM1 PWM1 SPI, SSP0 INTERFACE MISO, MISO0 2 × PCAP1 SSEL, SSEL0 SCK1 LEGACY GPI/O P0, P1 MOSI1 52 PINS TOTAL SSP1 INTERFACE MISO1 SSEL1 6 × AD0 A/D CONVERTER SD/MMC CARD MCICLK, MCIPWR INTERFACE(1) MCICMD, MCIDAT[3:0] AOUT D/A CONVERTER TXD0, TXD2, TXD3 UART0, UART2, UART3 RXD0, RXD2, RXD3 VBAT 2 kB BATTERY RAM powerr domaiin 2 TXD1 RXD1 RTCX1 REAL-RTC UART1 DTR1, RTS1 RTCX2 TIMEOSCILLATOR CLOCK DSR1, CTS1, DCD1, RI1 WATCHDOG TIMER CAN1, CAN2(2) RD1, RD2 TD1, TD2 SCL0, SCL1, SCL2 SYSTEM CONTROL I2C0, I2C1, I2C2 SDA0, SDA1, SDA2 002aac566 (1) LPC2367/68 only. (2) LPC2364/66/68 only.

Fig 1. LPC2364/65/66/67/68 block diagram EMULATION

TRACE MODULE Product data sheet Rev. 05 — 9 April 2009 5 of 53, 6. Pinning information 6.1 Pinning 1 75 LPC2364FBD100 LPC2365FBD100 LPC2366FBD100 LPC2367FBD100 LPC2368FBD100 25 51 002aac576 Fig 2. LPC2364/65/66/67/68 pinning ball A1 LPC2364FET100/LPC2368FET100 index area12345678910

A B C D E F G H J K

002aad225 Transparent top view Fig 3. LPC2364/68 pinning TFBGA100 package Table 3. Pin allocation table Pin Symbol Pin Symbol Pin Symbol Pin Symbol RowA1TDO 2 P0[3]/RXD0 3 VDD(3V3) 4 P1[4]/ENET_TX_EN 5 P1[10]/ENET_RXD1 6 P1[16]/ENET_MDC 7 VDD(DCDC)(3V3) 8 P0[4]/I2SRX_CLK/ RD2/CAP2[0] 9 P0[7]/I2STX_CLK/ 10 P0[9]/I2STX_SDA/ 11 - 12 - SCK1/MAT2[1] MOSI1/MAT2[3] RowB1TMS 2 RTCK 3 VSS 4 P1[1]/ENET_TXD1 26 100 50 76 Product data sheet Rev. 05 — 9 April 2009 6 of 53, Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol 5 P1[9]/ENET_RXD0 6 P1[17]/ 7 VSS 8 P0[6]/I2SRX_SDA/ ENET_MDIO SSEL1/MAT2[0] 9 P2[0]/PWM1[1]/ 10 P2[1]/PWM1[2]/ 11 - 12 - TXD1/TRACECLK RXD1/PIPESTAT0 RowC1TCK 2 TRST 3 TDI 4 P0[2]/TXD0 5 P1[8]/ENET_CRS 6 P1[15]/ 7 P4[28]/MAT2[0]/ 8 P0[8]/I2STX_WS/ ENET_REF_CLK TXD3 MISO1/MAT2[2] 9 VSS 10 VDD(3V3) 11 - 12 - RowD1P0[24]/AD0[1]/ 2 P0[25]/AD0[2]/ 3 P0[26]/AD0[3]/ 4 DBGEN I2SRX_WS/CAP3[1] I2SRX_SDA/TXD3 AOUT/RXD3 5 P1[0]/ENET_TXD0 6 P1[14]/ENET_RX_ER 7 P0[5]/I2SRX_WS/ 8 P2[2]/PWM1[3]/ TD2/CAP2[1] CTS1/PIPESTAT1 9 P2[4]/PWM1[5]/ 10 P2[5]/PWM1[6]/ 11 - 12 - DSR1/TRACESYNC DTR1/TRACEPKT0 RowE1VSSA 2 VDDA 3 VREF 4 VDD(DCDC)(3V3) 5 P0[23]/AD0[0]/ 6 P4[29]/MAT2[1]/ 7 P2[3]/PWM1[4]/ 8 P2[6]/PCAP1[0]/RI1/ I2SRX_CLK/CAP3[0] RXD3 DCD1/PIPESTAT2 TRACEPKT1 9 P2[7]/RD2/ 10 P2[8]/TD2/ 11 - 12 - RTS1/TRACEPKT2 TXD2/TRACEPKT3 RowF1VSS 2 RTCX1 3 RESET 4 P1[31]/SCK1/ AD0[5] 5 P1[21]/PWM1[3]/ 6 P0[18]/DCD1/ 7 P2[9]/USB_CONNECT/ 8 P0[16]/RXD1/ SSEL0 MOSI0/MOSI RXD2/EXTIN0 SSEL0/SSEL 9 P0[17]/CTS1/ 10 P0[15]/TXD1/ 11 - 12 - MISO0/MISO SCK0/SCK RowG1RTCX2 2 VBAT 3 XTAL2 4 P0[30]/USB_D− 5 P1[25]/MAT1[1] 6 P1[29]/PCAP1[1]/ 7 VSS 8 P0[21]/RI1/ MAT0[1] MCIPWR/RD1 9 P0[20]/DTR1/ 10 P0[19]/DSR1/ 11 - 12 - MCICMD/SCL1 MCICLK/SDA1 RowH1P1[30]/VBUS/ 2 XTAL1 3 P3[25]/MAT0[0]/ 4 P1[18]/USB_UP_LED/ AD0[4] PWM1[2] PWM1[1]/CAP1[0] 5 P1[24]/PWM1[5]/ 6 VDD(DCDC)(3V3) 7 P0[10]/TXD2/ 8 P2[11]/EINT1/ MOSI0 SDA2/MAT3[0] MCIDAT1/I2STX_CLK 9 VDD(3V3) 10 P0[22]/RTS1/ 11 - 12 - MCIDAT0/TD1 Product data sheet Rev. 05 — 9 April 2009 7 of 53, Table 3. Pin allocation table …continued Pin Symbol Pin Symbol Pin Symbol Pin Symbol RowJ1P0[28]/SCL0 2 P0[27]/SDA0 3 P0[29]/USB_D+ 4 P1[19]/CAP1[1] 5 P1[22]/MAT1[0] 6 VSS 7 P1[28]/PCAP1[0]/ 8 P0[1]/TD1/RXD3/SCL1 MAT0[0] 9 P2[13]/EINT3/ 10 P2[10]/EINT0 11 - 12 - MCIDAT3/I2STX_SDA RowK1P3[26]/MAT0[1]/ 2 VDD(3V3) 3 VSS 4 P1[20]/PWM1[2]/ PWM1[3] SCK0 5 P1[23]/PWM1[4]/ 6 P1[26]/PWM1[6]/ 7 P1[27]/CAP0[1] 8 P0[0]/RD1/TXD3/SDA1 MISO0 CAP0[0] 9 P0[11]/RXD2/ 10 P2[12]/EINT2/ 11 - 12 - SCL2/MAT3[1] MCIDAT2/I2STX_WS 6.2 Pin description Table 4. Pin description Symbol Pin Ball Type Description P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. Pins 12, 13, 14, and 31 of this port are not available. P0[0]/RD1/TXD3/ 46[1] K8[1] I/O P0[0] — General purpose digital input/output pin. SDA1 I RD1 — CAN1 receiver input. (LPC2364/66/68 only) O TXD3 — Transmitter output for UART3. I/O SDA1 — I2C1 data input/output (this is not an open-drain pin). P0[1]/TD1/RXD3/ 47[1] J8[1] I/O P0[1] — General purpose digital input/output pin. SCL1 O TD1 — CAN1 transmitter output. (LPC2364/66/68 only) I RXD3 — Receiver input for UART3. I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin). P0[2]/TXD0 98[1] C4[1] I/O P0[2] — General purpose digital input/output pin. O TXD0 — Transmitter output for UART0. P0[3]/RXD0 99[1] A2[1] I/O P0[3] — General purpose digital input/output pin. I RXD0 — Receiver input for UART0. P0[4]/ 81[1] A8[1] I/O P0[4] — General purpose digital input/output pin. I2SRX_CLK/ I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by RD2/CAP2[0] the slave. Corresponds to the signal SCK in the I2S-bus specification. I RD2 — CAN2 receiver input. (LPC2364/66/68 only) I CAP2[0] — Capture input for Timer 2, channel 0. P0[5]/ 80[1] D7[1] I/O P0[5] — General purpose digital input/output pin. I2SRX_WS/ I/O I2SRX_WS — Receive Word Select. It is driven by the master and received TD2/CAP2[1] by the slave. Corresponds to the signal WS in the I2S-bus specification. O TD2 — CAN2 transmitter output. (LPC2364/66/68 only) I CAP2[1] — Capture input for Timer 2, channel 1. Product data sheet Rev. 05 — 9 April 2009 8 of 53, Table 4. Pin description …continued Symbol Pin Ball Type Description P0[6]/ 79[1] B8[1] I/O P0[6] — General purpose digital input/output pin. I2SRX_SDA/ I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the SSEL1/MAT2[0] receiver. Corresponds to the signal SD in the I2S-bus specification. I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0. P0[7]/ 78[1] A9[1] I/O P0[7] — General purpose digital input/output pin. I2STX_CLK/ I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by SCK1/MAT2[1] the slave. Corresponds to the signal SCK in the I2S-bus specification. I/O SCK1 — Serial Clock for SSP1. O MAT2[1] — Match output for Timer 2, channel 1. P0[8]/ 77[1] C8[1] I/O P0[8] — General purpose digital input/output pin. I2STX_WS/ I/O I2STX_WS — Transmit Word Select. It is driven by the master and received MISO1/MAT2[2] by the slave. Corresponds to the signal WS in the I2S-bus specification. I/O MISO1 — Master In Slave Out for SSP1. O MAT2[2] — Match output for Timer 2, channel 2. P0[9]/ 76[1] A10[1] I/O P0[9] — General purpose digital input/output pin. I2STX_SDA/ I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the MOSI1/MAT2[3] receiver. Corresponds to the signal SD in the I2S-bus specification. I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer 2, channel 3. P0[10]/TXD2/ 48[1] H7[1] I/O P0[10] — General purpose digital input/output pin. SDA2/MAT3[0] O TXD2 — Transmitter output for UART2. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). O MAT3[0] — Match output for Timer 3, channel 0. P0[11]/RXD2/ 49[1] K9[1] I/O P0[11] — General purpose digital input/output pin. SCL2/MAT3[1] I RXD2 — Receiver input for UART2. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer 3, channel 1. P0[15]/TXD1/ 62[1] F10[1] I/O P0[15] — General purpose digital input/output pin. SCK0/SCK O TXD1 — Transmitter output for UART1. I/O SCK0 — Serial clock for SSP0. I/O SCK — Serial clock for SPI. P0[16]/RXD1/ 63[1] F8[1] I/O P0[16] — General purpose digital input/output pin. SSEL0/SSEL I RXD1 — Receiver input for UART1. I/O SSEL0 — Slave Select for SSP0. I/O SSEL — Slave Select for SPI. P0[17]/CTS1/ 61[1] F9[1] I/O P0[17] — General purpose digital input/output pin. MISO0/MISO I CTS1 — Clear to Send input for UART1. I/O MISO0 — Master In Slave Out for SSP0. I/O MISO — Master In Slave Out for SPI. Product data sheet Rev. 05 — 9 April 2009 9 of 53, Table 4. Pin description …continued Symbol Pin Ball Type Description P0[18]/DCD1/ 60[1] F6[1] I/O P0[18] — General purpose digital input/output pin. MOSI0/MOSI I DCD1 — Data Carrier Detect input for UART1. I/O MOSI0 — Master Out Slave In for SSP0. I/O MOSI — Master Out Slave In for SPI. P0[19]/DSR1/ 59[1] G10[1] I/O P0[19] — General purpose digital input/output pin. MCICLK/SDA1 I DSR1 — Data Set Ready input for UART1. O MCICLK — Clock output line for SD/MMC interface. (LPC2367/68 only) I/O SDA1 — I2C1 data input/output (this is not an open-drain pin). P0[20]/DTR1/ 58[1] G9[1] I/O P0[20] — General purpose digital input/output pin. MCICMD/SCL1 O DTR1 — Data Terminal Ready output for UART1. I MCICMD — Command line for SD/MMC interface. (LPC2367/68 only) I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin). P0[21]/RI1/ 57[1] G8[1] I/O P0[21] — General purpose digital input/output pin. MCIPWR/RD1 I RI1 — Ring Indicator input for UART1. O MCIPWR — Power Supply Enable for external SD/MMC power supply. (LPC2367/68 only) I RD1 — CAN1 receiver input. (LPC2364/66/68 only) P0[22]/RTS1/ 56[1] H10[1] I/O P0[22] — General purpose digital input/output pin. MCIDAT0/TD1 O RTS1 — Request to Send output for UART1. O MCIDAT0 — Data line for SD/MMC interface. (LPC2367/68 only) O TD1 — CAN1 transmitter output. (LPC2364/66/68 only) P0[23]/AD0[0]/ 9[2] E5[2] I/O P0[23] — General purpose digital input/output pin. I2SRX_CLK/ I AD0[0] — A/D converter 0, input 0. CAP3[0] I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. I CAP3[0] — Capture input for Timer 3, channel 0. P0[24]/AD0[1]/ 8[2] D1[2] I/O P0[24] — General purpose digital input/output pin. I2SRX_WS/ I AD0[1] — A/D converter 0, input 1. CAP3[1] I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I CAP3[1] — Capture input for Timer 3, channel 1. P0[25]/AD0[2]/ 7[2] D2[2] I/O P0[25] — General purpose digital input/output pin. I2SRX_SDA/ I AD0[2] — A/D converter 0, input 2. TXD3 I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. O TXD3 — Transmitter output for UART3. P0[26]/AD0[3]/ 6[3] D3[3] I/O P0[26] — General purpose digital input/output pin. AOUT/RXD3 I AD0[3] — A/D converter 0, input 3. O AOUT — D/A converter output. I RXD3 — Receiver input for UART3. Product data sheet Rev. 05 — 9 April 2009 10 of 53, Table 4. Pin description …continued Symbol Pin Ball Type Description P0[27]/SDA0 25[4] J2[4] I/O P0[27] — General purpose digital input/output pin. Output is open-drain. I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance). P0[28]/SCL0 24[4] J1[4] I/O P0[28] — General purpose digital input/output pin. Output is open-drain. I/O SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance). P0[29]/USB_D+ 29[5] J3[5] I/O P0[29] — General purpose digital input/output pin. I/O USB_D+ — USB bidirectional D+ line. (LPC2364/66/68 only) P0[30]/USB_D− 30[5] G4[5] I/O P0[30] — General purpose digital input/output pin. I/O USB_D− — USB bidirectional D− line. (LPC2364/66/68 only) P1[0] to P1[31] I/O Port 1: Port 1 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. Pins 2, 3, 5, 6, 7, 11, 12, and 13 of this port are not available. P1[0]/ 95[1] D5[1] I/O P1[0] — General purpose digital input/output pin. ENET_TXD0 O ENET_TXD0 — Ethernet transmit data 0. P1[1]/ 94[1] B4[1] I/O P1[1] — General purpose digital input/output pin. ENET_TXD1 O ENET_TXD1 — Ethernet transmit data 1. P1[4]/ 93[1] A4[1] I/O P1[4] — General purpose digital input/output pin. ENET_TX_EN O ENET_TX_EN — Ethernet transmit data enable. P1[8]/ 92[1] C5[1] I/O P1[8] — General purpose digital input/output pin. ENET_CRS I ENET_CRS — Ethernet carrier sense. P1[9]/ 91[1] B5[1] I/O P1[9] — General purpose digital input/output pin. ENET_RXD0 I ENET_RXD0 — Ethernet receive data. P1[10]/ 90[1] A5[1] I/O P1[10] — General purpose digital input/output pin. ENET_RXD1 I ENET_RXD1 — Ethernet receive data. P1[14]/ 89[1] D6[1] I/O P1[14] — General purpose digital input/output pin. ENET_RX_ER I ENET_RX_ER — Ethernet receive error. P1[15]/ 88[1] C6[1] I/O P1[15] — General purpose digital input/output pin. ENET_REF_CLK I ENET_REF_CLK — Ethernet reference clock. P1[16]/ 87[1] A6[1] I/O P1[16] — General purpose digital input/output pin. ENET_MDC O ENET_MDC — Ethernet MIIM clock. P1[17]/ 86[1] B6[1] I/O P1[17] — General purpose digital input/output pin. ENET_MDIO I/O ENET_MDIO — Ethernet MIIM data input and output. P1[18]/ 32[1] H4[1] I/O P1[18] — General purpose digital input/output pin. USB_UP_LED/ O USB_UP_LED — USB GoodLink LED indicator. It is LOW when device is PWM1[1]/ configured (non-control endpoints enabled). It is HIGH when the device is CAP1[0] not configured or during global suspend. (LPC2364/66/68 only) O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I CAP1[0] — Capture input for Timer 1, channel 0. P1[19]/CAP1[1] 33[1] J4[1] I/O P1[19] — General purpose digital input/output pin. I CAP1[1] — Capture input for Timer 1, channel 1. Product data sheet Rev. 05 — 9 April 2009 11 of 53, Table 4. Pin description …continued Symbol Pin Ball Type Description P1[20]/PWM1[2]/ 34[1] K4[1] I/O P1[20] — General purpose digital input/output pin. SCK0 O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I/O SCK0 — Serial clock for SSP0. P1[21]/PWM1[3]/ 35[1] F5[1] I/O P1[21] — General purpose digital input/output pin. SSEL0 O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I/O SSEL0 — Slave Select for SSP0. P1[22]/MAT1[0] 36[1] J5[1] I/O P1[22] — General purpose digital input/output pin. O MAT1[0] — Match output for Timer 1, channel 0. P1[23]/PWM1[4]/ 37[1] K5[1] I/O P1[23] — General purpose digital input/output pin. MISO0 O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. P1[24]/PWM1[5]/ 38[1] H5[1] I/O P1[24] — General purpose digital input/output pin. MOSI0 O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I/O MOSI0 — Master Out Slave in for SSP0. P1[25]/MAT1[1] 39[1] G5[1] I/O P1[25] — General purpose digital input/output pin. O MAT1[1] — Match output for Timer 1, channel 1. P1[26]/PWM1[6]/ 40[1] K6[1] I/O P1[26] — General purpose digital input/output pin. CAP0[0] O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I CAP0[0] — Capture input for Timer 0, channel 0. P1[27]/CAP0[1] 43[1] K7[1] I/O P1[27] — General purpose digital input/output pin. I CAP0[1] — Capture input for Timer 0, channel 1. P1[28]/ 44[1] J7[1] I/O P1[28] — General purpose digital input/output pin. PCAP1[0]/ I PCAP1[0] — Capture input for PWM1, channel 0. MAT0[0] O MAT0[0] — Match output for Timer 0, channel 0. P1[29]/ 45[1] G6[1] I/O P1[29] — General purpose digital input/output pin. PCAP1[1]/ I PCAP1[1] — Capture input for PWM1, channel 1. MAT0[1] O MAT0[1] — Match output for Timer 0, channel 0. P1[30]/VBUS/ 21[2] H1[2] I/O P1[30] — General purpose digital input/output pin. AD0[4] I VBUS — Monitors the presence of USB bus power. (LPC2364/66/68 only) Note: This signal must be HIGH for USB reset to occur. I AD0[4] — A/D converter 0, input 4. P1[31]/SCK1/ 20[2] F4[2] I/O P1[31] — General purpose digital input/output pin. AD0[5] I/O SCK1 — Serial Clock for SSP1. I AD0[5] — A/D converter 0, input 5. P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. Pins 14 through 31 of this port are not available. P2[0]/PWM1[1]/ 75[1] B9[1] I/O P2[0] — General purpose digital input/output pin. TXD1/ O PWM1[1] — Pulse Width Modulator 1, channel 1 output.

TRACECLK

O TXD1 — Transmitter output for UART1. O TRACECLK — Trace Clock. Product data sheet Rev. 05 — 9 April 2009 12 of 53, Table 4. Pin description …continued Symbol Pin Ball Type Description P2[1]/PWM1[2]/ 74[1] B10[1] I/O P2[1] — General purpose digital input/output pin. RXD1/ O PWM1[2] — Pulse Width Modulator 1, channel 2 output. PIPESTAT0 I RXD1 — Receiver input for UART1. O PIPESTAT0 — Pipeline Status, bit 0. P2[2]/PWM1[3]/ 73[1] D8[1] I/O P2[2] — General purpose digital input/output pin. CTS1/ O PWM1[3] — Pulse Width Modulator 1, channel 3 output. PIPESTAT1 I CTS1 — Clear to Send input for UART1. O PIPESTAT1 — Pipeline Status, bit 1. P2[3]/PWM1[4]/ 70[1] E7[1] I/O P2[3] — General purpose digital input/output pin. DCD1/ O PWM1[4] — Pulse Width Modulator 1, channel 4 output. PIPESTAT2 I DCD1 — Data Carrier Detect input for UART1. O PIPESTAT2 — Pipeline Status, bit 2. P2[4]/PWM1[5]/ 69[1] D9[1] I/O P2[4] — General purpose digital input/output pin. DSR1/ O PWM1[5] — Pulse Width Modulator 1, channel 5 output.

TRACESYNC

I DSR1 — Data Set Ready input for UART1. O TRACESYNC — Trace Synchronization. P2[5]/PWM1[6]/ 68[1] D10[1] I/O P2[5] — General purpose digital input/output pin. DTR1/ O PWM1[6] — Pulse Width Modulator 1, channel 6 output. TRACEPKT0 O DTR1 — Data Terminal Ready output for UART1. O TRACEPKT0 — Trace Packet, bit 0. P2[6]/PCAP1[0]/ 67[1] E8[1] I/O P2[6] — General purpose digital input/output pin. RI1/ I PCAP1[0] — Capture input for PWM1, channel 0. TRACEPKT1 I RI1 — Ring Indicator input for UART1. O TRACEPKT1 — Trace Packet, bit 1. P2[7]/RD2/ 66[1] E9[1] I/O P2[7] — General purpose digital input/output pin. RTS1/ I RD2 — CAN2 receiver input. (LPC2364/66/68 only) TRACEPKT2 O RTS1 — Request to Send output for UART1. O TRACEPKT2 — Trace Packet, bit 2. P2[8]/TD2/ 65[1] E10[1] I/O P2[8] — General purpose digital input/output pin. TXD2/ O TD2 — CAN2 transmitter output. (LPC2364/66/68 only) TRACEPKT3 O TXD2 — Transmitter output for UART2. O TRACEPKT3 — Trace Packet, bit 3. P2[9]/ 64[1] F7[1] I/O P2[9] — General purpose digital input/output pin. USB_CONNECT/ O USB_CONNECT — Signal used to switch an external 1.5 kΩ resistor under RXD2/EXTIN0 software control. Used with the SoftConnect USB feature. (LPC2364/66/68 only) I RXD2 — Receiver input for UART2. I EXTIN0 — External Trigger Input. P2[10]/EINT0 53[6] J10[6] I/O P2[10] — General purpose digital input/output pin. Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take over control of the part after a reset. I EINT0 — External interrupt 0 input. Product data sheet Rev. 05 — 9 April 2009 13 of 53, Table 4. Pin description …continued Symbol Pin Ball Type Description P2[11]/EINT1/ 52[6] H8[6] I/O P2[11] — General purpose digital input/output pin. MCIDAT1/ I EINT1 — External interrupt 1 input. I2STX_CLK O MCIDAT1 — Data line for SD/MMC interface. (LPC2367/68 only) I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. P2[12]/EINT2/ 51[6] K10[6] I/O P2[12] — General purpose digital input/output pin. MCIDAT2/ I EINT2 — External interrupt 2 input. I2STX_WS O MCIDAT2 — Data line for SD/MMC interface. (LPC2367/68 only) I/O I2STX_WS — Transmit Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. P2[13]/EINT3/ 50[6] J9[6] I/O P2[13] — General purpose digital input/output pin. MCIDAT3/ I EINT3 — External interrupt 3 input. I2STX_SDA O MCIDAT3 — Data line for SD/MMC interface. (LPC2367/68 only) I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. Pins 0 through 24, and 27 through 31 of this port are not available. P3[25]/MAT0[0]/ 27[1] H3[1] I/O P3[25] — General purpose digital input/output pin. PWM1[2] O MAT0[0] — Match output for Timer 0, channel 0. O PWM1[2] — Pulse Width Modulator 1, output 2. P3[26]/MAT0[1]/ 26[1] K1[1] I/O P3[26] — General purpose digital input/output pin. PWM1[3] O MAT0[1] — Match output for Timer 0, channel 1. O PWM1[3] — Pulse Width Modulator 1, output 3. P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. Pins 0 through 27, 30, and 31 of this port are not available. P4[28]/MAT2[0]/ 82[1] C7[1] I/O P4[28] — General purpose digital input/output pin. TXD3 O MAT2[0] — Match output for Timer 2, channel 0. O TXD3 — Transmitter output for UART3. P4[29]/MAT2[1]/ 85[1] E6[1] I/O P4[29] — General purpose digital input/output pin. RXD3 O MAT2[1] — Match output for Timer 2, channel 1. I RXD3 — Receiver input for UART3. DBGEN - D4[1] I DBGEN — JTAG interface control signal. Also used for boundary scanning. Note: This pin is available in LPC2364FET100 and LPC2368FET100 devices only (TFBGA package). TDO 1[1] A1[1] O TDO — Test Data out for JTAG interface. TDI 2[1] C3[1] I TDI — Test Data in for JTAG interface. TMS 3[1] B1[1] I TMS — Test Mode Select for JTAG interface. TRST 4[1] C2[1] I TRST — Test Reset for JTAG interface. TCK 5[1] C1[1] I TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG interface to operate Product data sheet Rev. 05 — 9 April 2009 14 of 53, Table 4. Pin description …continued Symbol Pin Ball Type Description RTCK 100[1] B2[1] I/O RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as trace port after reset. RSTOUT 14 - O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2364/65/66/67/68 being in Reset state. Note: This pin is available in LPC2364FBD100, LPC2365FBD100, LPC2366FBD100, LPC2367FBD100, and LPC2368FBD100 devices only (LQFP100 package). RESET 17[7] F3[7] I External reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. XTAL1 22[8] H2[8] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 23[8] G3[8] O Output from the oscillator amplifier. RTCX1 16[8] F2[8] I Input to the RTC oscillator circuit. RTCX2 18[8] G1[8] O Output from the RTC oscillator circuit. VSS 15, 31, B3, B7, I ground: 0 V reference. 41, 55, C9, F1, 72, 97, G7, J6, 83[9] K3 [9] VSSA 11[10] E1[10] I analog ground: 0 V reference. This should nominally be the same voltage as VSS, but should be isolated to minimize noise and error. VDD(3V3) 28, 54, A3, C10, I 3.3 V supply voltage: This is the power supply voltage for the I/O ports. 71, H9, 96[11] K2[11] VDD(DCDC)(3V3) 13, 42, A7, E4, I 3.3 V DC-to-DC converter supply voltage: This is the supply voltage for 84[12] H6[12] the on-chip DC-to-DC converter only. V [13]DDA 10 E2[13] I analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. VREF 12[13] E3[13] I ADC reference: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. Level on this pin is used as a reference for ADC and DAC. VBAT 19[13] G2[13] I RTC pin power supply: 3.3 V on this pin supplies the power to the RTC peripheral. [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. [2] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a DAC input, digital section of the pad is disabled. [3] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. [4] Open-drain5Vtolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. This pad requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [5] Pad provides digital I/O and USB functions (LPC2364/66/68 only). It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). [6] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. [7] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. [8] Pad provides special analog functionality. [9] Pad provides special analog functionality. Product data sheet Rev. 05 — 9 April 2009 15 of 53, [10] Pad provides special analog functionality. [11] Pad provides special analog functionality. [12] Pad provides special analog functionality. [13] Pad provides special analog functionality. 7. Functional description 7.1 Architectural overview The LPC2364/65/66/67/68 microcontroller consists of an ARM7TDMI-S CPU with emulation support, the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip memory, the AMBA AHB interfacing to high-speed on-chip peripherals, and the AMBA APB for connection to other on-chip peripheral functions. The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order. The LPC2364/65/66/67/68 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC and GPDMA controller. The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1. In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2 are the ARM7 and the Ethernet block. AHB peripherals are allocateda2MB range of addresses at the very top of the 4 GB ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB address space. Lower speed peripheral functions are connected to the APB. The AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocateda2MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is allocated a 16 kB address space within the APB address space. The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: Product data sheet Rev. 05 — 9 April 2009 16 of 53, • The standard 32-bit ARM set • A 16-bit Thumb set The Thumb set’s 16-bit instruction length allows it to approach twice the density of standard ARM code while retaining most of the ARM’s performance advantage over a traditional 16-bit processor using 16-bit registers. This is possible because Thumb code operates on the same 32-bit register set as ARM code. Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the performance of an equivalent ARM processor connected to a 16-bit memory system. 7.2 On-chip flash programming memory The LPC2364/65/66/67/68 incorporate a 128 kB, 256 kB, and 512 kB flash memory system respectively. This memory may be used for both code and data storage. Programming of the flash memory may be accomplished in several ways. It may be programmed In System via the serial port (UART0). The application program may also erase and/or program the flash while the application is running, allowing a great degree of flexibility for data storage field and firmware upgrades. The flash memory is 128 bits wide and includes pre-fetching and buffering techniques to allow it to operate at SRAM speeds of 72 MHz. LPC2364HBD flash operates up to 72 MHz from −40 °C to +85 °C, up to 60 MHz from 85 °C to 125 °C. The LPC2364/65/66/67/68 provides a minimum of 100000 write/erase cycles and 20 years of data retention. 7.3 On-chip SRAM The LPC2364/65/66/67/68 include SRAM memory of 8 kB or 32 kB, reserved for the ARM processor exclusive use. This RAM may be used for code and/or data storage and may be accessed as 8 bits, 16 bits, and 32 bits. A 16 kB SRAM block serving as a buffer for the Ethernet controller and an 8 kB SRAM used by the GPDMA controller or the USB device can be used both for data and code storage. The 2 kB RTC SRAM can be used for data storage only. The RTC SRAM is battery powered and retains the content in the absence of the main power supply. 7.4 Memory map The LPC2364/65/66/67/68 memory map incorporates several distinct regions as shown in Figure 4. In addition, the CPU interrupt vectors may be remapped to allow them to reside in either flash memory (default), boot ROM, or SRAM (see Section 7.25.6). Product data sheet Rev. 05 — 9 April 2009 17 of 53, 4.0 GB 0xFFFF FFFF AHB PERIPHERALS 3.75 GB 0xF000 0000 APB PERIPHERALS 3.5 GB 0xE000 0000 3.0 GB 0xC000 0000 RESERVED ADDRESS SPACE 2.0 GB 0x8000 0000 BOOT ROM AND BOOT FLASH (BOOT FLASH REMAPPED FROM ON-CHIP FLASH) RESERVED ADDRESS SPACE 0x7FE0 3FFF ETHERNET RAM (16 kB) 0x7FE0 0000 0x7FD0 1FFF GENERAL PURPOSE OR USB RAM (8 KB) 0x7FD0 0000 RESERVED ADDRESS SPACE 0x4000 8000 0x4000 7FFF 32 kB LOCAL ON-CHIP STATIC RAM (LPC2365/66/67/68) 0x4000 2000 0x4000 1FFF 8 kB LOCAL ON-CHIP STATIC RAM (LPC2364) 1.0 GB 0x4000 0000 RESERVED FOR ON-CHIP MEMORY 0x0008 0000 TOTAL OF 512 kB ON-CHIP NON-VOLATILE MEMORY (LPC2367/68) 0x0007 FFFF 0x0004 0000 TOTAL OF 256 kB ON-CHIP NON-VOLATILE MEMORY (LPC2365/66) 0x0003 FFFF 0x0002 0000 0x0001 FFFF 0.0 GB TOTAL OF 128 kB ON-CHIP NON-VOLATILE MEMORY (LPC2364) 0x0000 0000 002aac577 Fig 4. LPC2364/65/66/67/68 memory map 7.5 Interrupt controller

The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be

programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. Product data sheet Rev. 05 — 9 April 2009 18 of 53, FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt. Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have a programmable interrupt priority. When more than one interrupt is assigned the same priority and occur simultaneously, the one connected to the lowest numbered VIC channel will be serviced first. The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping to the address supplied by that register. 7.5.1 Interrupt sources Each peripheral device has one interrupt line connected to the VIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on PORT0 and PORT2 (total of 42 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. Such interrupt request coming from PORT0 and/or PORT2 will be combined with the EINT3 interrupt requests. 7.6 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.7 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2364/65/66/67/68 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. 7.7.1 Features • Two DMA channels. Each channel can support a unidirectional transfer. • The GPDMA can transfer data between the 8 kB SRAM and peripherals such as the SD/MMC, two SSP, and I2S interfaces. Product data sheet Rev. 05 — 9 April 2009 19 of 53, • Single DMA and burst DMA request signals. Each peripheral connected to the GPDMA can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the GPDMA. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. Each DMA channel has a specific hardware priority. DMA channel 0 has the highest priority and channel 1 has the lowest priority. If requests from two channels become active at the same time the channel with the highest priority is serviced first. • AHB slave DMA programming interface. The GPDMA is programmed by writing to the DMA control registers over the AHB slave interface. • One AHB master for transferring data. This interface transfers data when a DMA request goes active. • 32-bit AHB master bus width. • Incrementing or non-incrementing addressing for source and destination. • Programmable DMA burst size. The DMA burst size can be programmed to more efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the peripheral. • Internal four-word FIFO per channel. • Supports 8-bit, 16-bit, and 32-bit wide transactions. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Interrupt masking. The DMA error and DMA terminal count interrupt requests can be masked. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 7.8 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC2364/65/66/67/68 use accelerated GPIO functions: • GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • All GPIO registers are byte and half-word addressable. • Entire port value can be written in one instruction. Product data sheet Rev. 05 — 9 April 2009 20 of 53, Additionally, any pin on PORT0 and PORT2 (total of 42 pins) providing a digital function can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 7.8.1 Features • Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset. • Backward compatibility with other earlier devices is maintained with legacy PORT0 and PORT1 registers appearing at the original addresses on the APB. 7.9 Ethernet The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. The Ethernet block and the CPU share a dedicated AHB subsystem that is used to access the Ethernet SRAM for Ethernet data, control, and status information. All other AHB traffic in the LPC2364/65/66/67/68 takes place on a different AHB subsystem, effectively separating Ethernet activity from the rest of the system. The Ethernet DMA can also access the USB SRAM if it is not being used by the USB block. The Ethernet block interfaces between an off-chip Ethernet PHY using the Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 7.9.1 Features • Ethernet standards support: – Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x full duplex flow control and half duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. • Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. • Enhanced Ethernet features: Product data sheet Rev. 05 — 9 April 2009 21 of 53, – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through standard RMII interface. – PHY register access is available via the MIIM interface. 7.10 USB interface (LPC2364/66/68 only) The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a host and a number (127 maximum) of peripherals. The host controller allocates the USB bandwidth to attached devices through a token based protocol. The bus supports hot plugging, unplugging, and dynamic configuration of the devices. All transactions are initiated by the host controller. 7.10.1 USB device controller The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of register interface, serial interface engine, endpoint buffer memory, and the DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate end point buffer memory. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. The DMA controller when enabled transfers data between the endpoint buffer and the USB RAM. 7.10.2 Features • Fully compliant with USB 2.0 specification (full speed). • Supports 32 physical (16 logical) endpoints witha4kB USB endpoint buffer RAM. • Supports Control, Bulk, Interrupt and Isochronous endpoints. • Scalable realization of endpoints at run time. • Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, LPC2364/65/66/67/68 can enter one of the reduced power modes and wake up on a USB activity. • Supports DMA transfers with the DMA RAM of 8 kB on all non-control endpoints. • Allows dynamic switching between CPU-controlled and DMA modes. Product data sheet Rev. 05 — 9 April 2009 22 of 53, • Double buffer implementation for Bulk and Isochronous endpoints. 7.11 CAN controller and acceptance filters (LPC2364/66/68 only) The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router among a number of CAN buses in industrial or automotive applications. Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN Library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the ARM environment. The main operational difference is that the recognition of received Identifiers, known in CAN terminology as Acceptance Filtering, has been removed from the CAN controllers and centralized in a global Acceptance Filter. 7.11.1 Features • Two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • Full CAN messages can generate interrupts. 7.12 10-bit ADC The LPC2364/65/66/67/68 contain one ADC. It is a single 10-bit successive approximation ADC with six channels. 7.12.1 Features • 10-bit successive approximation ADC. • Input multiplexing among 6 pins. • Power-down mode. • Measurement range0Vto Vi(VREF). • 10-bit conversion time ≥ 2.44 µs. • Burst conversion mode for single or multiple inputs. • Optional conversion on transition of input pin or Timer Match signal. • Individual result registers for each ADC channel to reduce interrupt overhead. Product data sheet Rev. 05 — 9 April 2009 23 of 53, 7.13 10-bit DAC The DAC allows the LPC2364/65/66/67/68 to generate a variable analog output. The maximum output value of the DAC is Vi(VREF). 7.13.1 Features • 10-bit DAC • Resistor string architecture • Buffered output • Power-down mode • Selectable output drive 7.14 UARTs The LPC2364/65/66/67/68 each contain four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.14.1 Features • 16 B Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). • UART3 includes an IrDA mode to support infrared communication. 7.15 SPI serial I/O controller The LPC2364/65/66/67/68 each contain one SPI controller. SPI is a full duplex serial interface designed to handle multiple masters and slaves connected to a given bus. Only a single master and a single slave can communicate on the interface during a given data transfer. During a data transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 7.15.1 Features • Compliant with SPI specification • Synchronous, serial, full duplex communication • Combined SPI master and slave • Maximum data bit rate of one eighth of the input clock rate • 8 bits to 16 bits per transfer Product data sheet Rev. 05 — 9 April 2009 24 of 53, 7.16 SSP serial I/O controller The LPC2364/65/66/67/68 each contain two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.16.1 Features • Compatible with Motorola SPI, 4-wire Texas Instruments SSI, and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame • DMA transfers supported by GPDMA 7.17 SD/MMC card interface (LPC2367/68 only) The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD memory cards. The SD card interface conforms to the SD Multimedia Card Specification Version 2.11. 7.17.1 Features • The MCI interface provides all functions specific to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer. • Conforms to Multimedia Card Specification v2.11. • Conforms to Secure Digital Memory Card Physical Layer Specification, v0.96. • Can be used as a multimedia card bus or a secure digital memory card bus host. The SD/MMC can be connected to several multimedia cards or a single secure digital memory card. • DMA supported through the GPDMA controller. 7.18 I2C-bus serial I/O controllers The LPC2364/65/66/67/68 each contain three I2C-bus controllers. The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C is a multi-master bus, it can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2364/65/66/67/68 supports bit rates up to 400 kbit/s (Fast I2C-bus). Product data sheet Rev. 05 — 9 April 2009 25 of 53, 7.18.1 Features • I2C0 is a standard I2C compliant bus interface with open-drain pins. • I2C1 and I2C2 use standard I/O pins and do not support powering off of individual devices connected to the same bus lines. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. 7.19 I2S-bus serial I/O controllers The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S connection has one master, which is always the master, and one slave. The I2S interface on the LPC2364/65/66/67/68 provides a separate transmit and receive channel, each of which can operate as either a master or a slave. 7.19.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. • Mono and stereo audio data supported. • The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1, 48) kHz. • Configurable word select period in master mode (separately for I2S input and output). • Two 8-word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I2S input and I2S output. Product data sheet Rev. 05 — 9 April 2009 26 of 53, 7.20 General purpose 32-bit timers/external event counters The LPC2364/65/66/67/68 include four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. The Timer/Counter also includes two capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.20.1 Features • A 32-bit Timer/Counter with a programmable 32-bit prescaler. • Counter or Timer operation. • Two 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. 7.21 Pulse width modulator The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC2364/65/66/67/68. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers. The PWM function is in addition to these features, and is based on match register events. The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. One match register (PWMMR0) controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Product data sheet Rev. 05 — 9 April 2009 27 of 53, Three match registers can be used to provide a PWM output with both edges controlled. Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 7.21.1 Features • LPC2364/65/66/67/68 has one PWM block with Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). • Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go high at the beginning of each cycle unless the output is a constant low. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. • Pulse period and width can be any number of timer counts. This allows complete flexibility in the trade-off between resolution and repetition rate. All PWM outputs will occur at the same repetition rate. • Double edge controlled PWM outputs can be programmed to be either positive going or negative going pulses. • Match register updates are synchronized with pulse outputs to prevent generation of erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard timer if the PWM mode is not enabled. • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. 7.22 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. 7.22.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. Product data sheet Rev. 05 — 9 April 2009 28 of 53, • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal prescaler. • Selectable time period from (T 32cy(WDCLK) × 256 × 4) to (Tcy(WDCLK) × 2 × 4) in multiples of Tcy(WDCLK) × 4. • The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring, for increased reliability. 7.23 RTC and battery RAM The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in Power-down mode. On the LPC2364/65/66/67/68, the RTC can be clocked by a separate 32.768 kHz oscillator, or by a programmable prescale divider based on the APB clock. Also, the RTC is powered by its own power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V supply used by the rest of the device. The VBAT pin supplies power only to the RTC and the battery RAM. These two functions require a minimum of power to operate, which can be supplied by an external battery. 7.23.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Dedicated 32 kHz oscillator or programmable prescaler from APB clock. • Dedicated power supply pin can be connected to a battery or to the main 3.3 V. • Periodic interrupts can be generated from increments of any field of the time registers, and selected fractional second values. • 2 kB data SRAM powered by VBAT. • RTC and battery RAM power supply is isolated from the rest of the chip. 7.24 Clocking and power control 7.24.1 Crystal oscillators The LPC2364/65/66/67/68 includes three independent oscillators. These are the Main Oscillator, the Internal RC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the PLL and ultimately the CPU. Following reset, the LPC2364/65/66/67/68 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. Product data sheet Rev. 05 — 9 April 2009 29 of 53, 7.24.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to ±1 % accuracy. Upon power-up or any chip reset, the LPC2364/65/66/67/68 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.24.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to Section 7.24.2 for additional information. 7.24.1.3 RTC oscillator The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the RTC oscillator can be used to drive the PLL and the CPU. 7.24.2 PLL The PLL accepts an input clock frequency in the range of 32 kHz to 50 MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and the USB block. The USB block is available in LPC2364/66/68 only. The PLL input, in the range of 32 kHz to 50 MHz, may initially be divided down by a value ‘N’, which may be in the range of 1 to 256. This input division provides a wide range of output frequencies from the same input frequency. Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency. The PLL is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL is enabled by software only. The program must configure and activate the PLL, wait for the PLL to Lock, then connect to the PLL as a clock source. 7.24.3 Wake-up timer The LPC2364/65/66/67/68 begins operation at power-up and when awakened from Power-down mode by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. Product data sheet Rev. 05 — 9 April 2009 30 of 53, When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down mode, any wake-up of the processor from Power-down mode makes use of the wake-up Timer. The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. 7.24.4 Power control The LPC2364/65/66/67/68 supports a variety of power control features. There are three special modes of processor power reduction: Idle mode, Sleep mode, and Power-down mode. The CPU clock rate may also be controlled as needed by changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. This allows a trade-off of power versus processing speed based on application requirements. In addition, Peripheral Power Control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. The LPC2364/65/66/67/68 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small SRAM, referred to as the battery RAM. 7.24.4.1 Idle mode In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.24.4.2 Sleep mode In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The 32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The CCLK and USB clock dividers automatically get reset to zero. The Sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Sleep mode reduces chip power consumption to a very low value. The flash memory is left on in Sleep mode, allowing a very quick wake-up. Product data sheet Rev. 05 — 9 April 2009 31 of 53, On the wake-up of Sleep mode, if the IRC was used before entering Sleep mode, the code execution and peripherals activities will resume after 4 cycles expire. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. The customers need to reconfigure the PLL and clock dividers accordingly. 7.24.4.3 Power-down mode Power-down mode does everything that Sleep mode does, but also turns off the IRC oscillator and the flash memory. This saves more power, but requires waiting for resumption of flash operation before execution of code or data access in the flash memory can be accomplished. On the wake-up of Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 µs to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 4 MHz IRC clock cycles to make the 100 µs flash start-up time. When it times out, access to the flash will be allowed. The customers need to reconfigure the PLL and clock dividers accordingly. 7.24.4.4 Power domains The LPC2364/65/66/67/68 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the battery RAM. On the LPC2364/65/66/67/68, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the VDD(DCDC)(3V3) pin powers the on-chip DC-to-DC converter which in turn provides power to the CPU and most of the peripherals. Depending on the LPC2364/65/66/67/68 application, a design can use two power options to manage power consumption. The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(DCDC)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(DCDC)(3V3)). Having the on-chip DC-to-DC converter powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly”, while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC and the battery RAM. These two functions require a minimum of power to operate, which can be supplied by an external battery. When the CPU and the rest of chip functions are stopped and power removed, the RTC can supply an alarm output that may be used by external hardware to restore chip power and resume operation. Product data sheet Rev. 05 — 9 April 2009 32 of 53, 7.25 System control 7.25.1 Reset Reset has four sources on the LPC2364/65/66/67/68: the RESET pin, the Watchdog reset, power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable level, starts the Wake-up timer (see description in Section 7.24.3 “Wake-up timer”), causing reset to remain asserted until the external Reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the flash controller has completed its initialization. When the internal Reset is removed, the processor begins executing at address 0, which is initially the Reset vector mapped from the Boot Block. At that point, all of the processor and peripheral registers have been initialized to predetermined values. 7.25.2 Brownout detection The LPC2364/65/66/67/68 includes 2-stage monitoring of the voltage on the VDD(3V3) pins. If this voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts Reset to inactivate the LPC2364/65/66/67/68 when the voltage on the VDD(3V3) pins falls below 2.65 V. This Reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall Reset. Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly executed event loop to sense the condition. 7.25.3 Code security (Code Read Protection - CRP) This feature of the LPC2364/65/66/67/68 allows user to enable different levels of security in the system so that access to the on-chip flash and use of the JTAG and ISP can be restricted. When needed, CRP is invoked by programming a specific pattern into a dedicated flash location. IAP commands are not affected by the CRP. There are three levels of the Code Read Protection. CRP1 disables access to chip via the JTAG and allows partial flash update (excluding flash sector 0) using a limited set of the ISP commands. This mode is useful when CRP is required and flash field updates are needed but all sectors can not be erased. CRP2 disables access to chip via the JTAG and only allows full flash erase and update using a reduced set of the ISP commands. Running an application with level CRP3 selected fully disables any access to chip via the JTAG pins and the ISP. This mode effectively disables ISP override using P2[10] pin, too. It is up to the user’s application to provide (if needed) flash update mechanism using IAP calls or call reinvoke ISP command to enable flash update via UART0. Product data sheet Rev. 05 — 9 April 2009 33 of 53,

CAUTION

If level three Code Read Protection (CRP3) is selected, no future factory testing can be performed on the device. 7.25.4 AHB The LPC2364/65/66/67/68 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 8 kB SRAM primarily intended for use by the USB. The USB interface is available on LPC2364/66/68 only. The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into unused space in memory residing on AHB1. In summary, bus masters with access to AHB1 are the ARM7 itself, the USB block, the GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2 are the ARM7 and the Ethernet block. 7.25.5 External interrupt inputs The LPC2364/65/66/67/68 include up to 46 edge sensitive interrupt inputs combined with up to four level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. 7.25.6 Memory mapping control The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot ROM or the SRAM. This allows code running in different memory spaces to have control of the interrupts. 7.26 Emulation and debugging The LPC2364/65/66/67/68 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself. 7.26.1 EmbeddedICE The EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present on the target system. Product data sheet Rev. 05 — 9 April 2009 34 of 53, The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The DCC is accessed as a co-processor 14 by the program running on the ARM7TDMI-S core. The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG interface to operate. 7.26.2 Embedded trace Since the LPC2364/65/66/67/68 have significant amounts of on-chip memories, it is not possible to determine how the processor core is operating simply by observing the external pins. The ETM provides real-time trace capability for deeply embedded processor cores. It outputs information about processor execution to a trace port. A software debugger allows configuration of the ETM using a JTAG interface and displays the trace information that has been captured. The ETM is connected directly to the ARM core and not to the main AMBA system bus. It compresses the trace information and exports it through a narrow trace port. An external Trace Port Analyzer captures the trace information under software debugger control. The trace port can broadcast the Instruction trace information. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. 7.26.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2364/65/66/67/68 contain a specific configuration of RealMonitor software programmed into the on-chip ROM memory. Product data sheet Rev. 05 — 9 April 2009 35 of 53, 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134).[1] Symbol Parameter Conditions Min Max Unit VDD(3V3) supply voltage (3.3 V) core and external 3.0 3.6 V rail VDD(DCDC)(3V3) DC-to-DC converter supply voltage 3.0 3.6 V (3.3 V) VDDA analog 3.3 V pad supply voltage −0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT for the RTC −0.5 +4.6 V Vi(VREF) input voltage on pin VREF −0.5 +4.6 V VIA analog input voltage on ADC related −0.5 +5.1 V pins VI input voltage5Vtolerant I/O [2] −0.5 +6.0 V pins; only valid when the VDD(3V3) supply voltage is present other I/O pins [2][3] −0.5 VDD(3V3) + V 0.5 IDD supply current per supply pin [4] - 100 mA ISS ground current per ground pin [4] - 100 mA Tstg storage temperature [5] −40 +125 °C Ptot(pack) total power dissipation (per package) based on package - 1.5 W heat transfer, not device power consumption Vesd electrostatic discharge voltage human body [6] −4000 +4000 V model; all pins [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSS unless otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] Not to exceed 4.6 V. [4] The peak current is limited to 25 times the corresponding maximum current. [5] Dependent on package type. [6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. Product data sheet Rev. 05 — 9 April 2009 36 of 53, 9. Static characteristics Table 6. Static characteristics Tamb = −40 °C to +85 °C for standard devices, −40 °C to +125 °C for LPC2364HBD only, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit VDD(3V3) supply voltage (3.3 V) core and external rail 3.0 3.3 3.6 V VDD(DCDC)(3V3) DC-to-DC converter 3.0 3.3 3.6 V supply voltage (3.3 V) VDDA analog 3.3 V pad supply 3.0 3.3 3.6 V voltage Vi(VBAT) input voltage on pin [2] 2.0 3.3 3.6 V

VBAT

Vi(VREF) input voltage on pin 2.5 3.3 VDDA V

VREF

Standard port pins, RESET, RTCK IIL LOW-level input current VI = 0 V; no pull-up - - 3 µA IIH HIGH-level input current VI = VDD(3V3); no - - 3 µA pull-down IOZ OFF-state output VO = 0 V; VO = VDD(3V3); - - 3 µA current no pull-up/down Ilatch I/O latch-up current −(0.5VDD(3V3)) < VI < - - 100 mA (1.5VDD(3V3)); Tj < 125 °C VI input voltage pin configured to provide [3][4][5] 0 - 5.5Vadigital function VO output voltage output active 0 - VDD(3V3) V VIH HIGH-level input 2.0 - - V voltage VIL LOW-level input voltage - - 0.8 V Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output IOH = −4 mA [6] VDD(3V3) − - - V voltage 0.4 VOL LOW-level output I [6]OL = −4 mA - - 0.4 V voltage IOH HIGH-level output VOH = VDD(3V3) − 0.4 V [6] −4 - - mA current I LOW-level output V = 0.4 V [6]OL OL 4 - - mA current IOHS HIGH-level short-circuit V [7]OH = 0 V - - −45 mA output current IOLS LOW-level short-circuit VOL = V [7]DDA - - 50 mA output current Ipd pull-down current VI = 5 V [8] 10 50 150 µA Ipu pull-up current VI = 0 V; −40 °C to +85 °C −15 −50 −85 µA VI = 0 V; > 85 °C [9] −15 −50 −100 µA V [8]DD(3V3) < VI < 5V000µA Product data sheet Rev. 05 — 9 April 2009 37 of 53, Table 6. Static characteristics …continued Tamb = −40 °C to +85 °C for standard devices, −40 °C to +125 °C for LPC2364HBD only, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit IDD(DCDC)act(3V3) active mode DC-to-DC VDD(DCDC)(3V3) = 3.3 V; converter supply Tamb = 25 °C; code current (3.3 V) while(1){} executed from flash; no peripherals enabled; PCLK = CCLK CCLK = 10 MHz - 15 - mA CCLK = 72 MHz - 63 - mA all peripherals enabled; PCLK = CCLK / 8 CCLK = 10 MHz - 21 - mA CCLK = 72 MHz - 92 - mA all peripherals enabled; PCLK = CCLK CCLK = 10 MHz - 27 - mA CCLK = 72 MHz - 125 - mA IDD(DCDC)pd(3V3) power-down mode VDD(DCDC)(3V3) = 3.3 V; - 150 - µA DC-to-DC converter Tamb = 25 °C supply current (3.3 V) IBATact active mode battery DC-to-DC converter on [10] - 20 - µA supply current DC-to-DC converter off [10] - 28 - µA I2C-bus pins (P0[27] and P0[28]) VIH HIGH-level input 0.7VDD(3V3) - - V voltage VIL LOW-level input voltage - - 0.3VDD(3V3) V Vhys hysteresis voltage - 0.5VDD(3V3) - V V [6]OL LOW-level output IOLS = 3 mA - - 0.4 V voltage ILI input leakage current VI = V [11]DD(3V3) - 2 4 µA VI = 5 V - 10 22 µA Oscillator pins Vi(XTAL1) input voltage on pin 0 - 1.8 V XTAL1 Vo(XTAL2) output voltage on pin 0 - 1.8 V XTAL2 Vi(RTCX1) input voltage on pin 0 - 1.8 V RTCX1 Vo(RTCX2) output voltage on pin 0 - 1.8 V RTCX2 Product data sheet Rev. 05 — 9 April 2009 38 of 53, Table 6. Static characteristics …continued Tamb = −40 °C to +85 °C for standard devices, −40 °C to +125 °C for LPC2364HBD only, unless otherwise specified. Symbol Parameter Conditions Min Typ[1] Max Unit USB pins (LPC2364/66/68 only) IOZ OFF-state output0V< VI < 3.3 V - - ±10 µA current VBUS bus supply voltage - - 5.25 V VDI differential input |(D+) − (D−)| 0.2 - - V sensitivity voltage VCM differential common includes VDI range 0.8 - 2.5 V mode voltage range Vth(rs)se single-ended receiver 0.8 - 2.0 V switching threshold voltage VOL LOW-level output RL of 1.5 kΩ to 3.6 V - - 0.18 V voltage for low-/full-speed VOH HIGH-level output RL of 15 kΩ to GND 2.8 - 3.5 V voltage (driven) for low-/full-speed Ctrans transceiver capacitance pin to GND - - 20 pF Z driver output with 33 Ω series resistor; [12]DRV 36 - 44.1 Ω impedance for driver steady state drive which is not high-speed capable [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. [2] The RTC typically fails when Vi(VBAT) drops below 1.6 V. [3] Including voltage on outputs in 3-state mode. [4] VDD(3V3) supply voltages must be present. [5] 3-state outputs go into 3-state mode when VDD(3V3) is grounded. [6] Accounts for 100 mV voltage drop in all supply lines. [7] Only allowed for a short time period. [8] Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V. [9] LPC2364HBD only. [10] On pin VBAT. [11] To VSS. [12] Includes external resistors of 33 Ω ± 1 % on D+ and D−. Product data sheet Rev. 05 — 9 April 2009 39 of 53, Table 7. ADC static characteristics VDDA = 2.5 V to 3.6 V; Tamb = −40 °C to +85 °C, unless otherwise specified; ADC frequency 4.5 MHz. Symbol Parameter Conditions Min Typ Max Unit VIA analog input voltage 0 - VDDA V Cia analog input capacitance - - 1 pF ED differential linearity error [1][2][3] - - ±1 LSB EL(adj) integral non-linearity [1][4] - - ±2 LSB E offset error [1][5]O - - ±3 LSB EG gain error [1][6] - - ±0.5 % E absolute error [1][7]T - - ±4 LSB Rvsi voltage source interface [8] - - 40 kΩ resistance [1] Conditions: VSSA = 0 V, VDDA = 3.3 V. [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 5. [4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 5. [5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 5. [6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 5. [7] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 5. [8] See Figure 6. Product data sheet Rev. 05 — 9 April 2009 40 of 53, offset gain error error EO EG (2) code (1) out (5) (4) (3) 1 1 LSB (ideal) 12345671018 1019 1020 1021 1022 1023 1024 V (LSB ) offset error IA ideal EOV1LSB = i(VREF) − VSSA 002aae604 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve.

Fig 5. ADC characteristics

Product data sheet Rev. 05 — 9 April 2009 41 of 53, LPC23XX 20 kΩ AD0[y] Rvsi AD0[y]SAMPLE 3 pF 5 pF

VEXT VSS

002aac610 Fig 6. Suggested ADC interface - LPC2364/65/66/67/68 AD0[y] pin Product data sheet Rev. 05 — 9 April 2009 42 of 53, 10. Dynamic characteristics Table 8. Dynamic characteristics Tamb = −40 °C to +85 °C for standard devices, −40 °C to +125 °C for LPC2364HBD only, unless otherwise specified; VDD(3V3) over specified ranges.[1] Symbol Parameter Conditions Min Typ[2] Max Unit ARM processor clock frequency foper operating frequency CCLK; −40 °C to +85 °C 1 - 72 MHz CCLK; > 85 °C [3] 1 - 60 MHz IRC; −40 °C to +85 °C 3.96 4 4.04 MHz IRC; > 85 °C [3] 3.98 4.02 4.06 MHz External clock fosc oscillator frequency 1 - 25 MHz Tcy(clk) clock cycle time 42 - 1000 ns tCHCX clock HIGH time Tcy(clk) × 0.4 - - ns tCLCX clock LOW time Tcy(clk) × 0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns I2C-bus pins (P0[27] and P0[28]) tf(o) output fall time VIH to VIL 20 + 0.1 × C [4]b - - ns SSP interface tsu(SPI_MISO) SPI_MISO set-up time Tamb = 25 °C; measured - 11 - ns in SPI Master mode; see Figure 9 [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. [3] LPC2364HBD only. [4] Bus capacitance Cb in pF, from 10 pF to 400 pF. Table 9. Dynamic characteristics of USB pins (full-speed) (LPC2364/66/68 only) CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(3V3), unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.7 ns tFRFM differential rise and fall time tr / tf - - 109 % matching VCRS output signal crossover voltage 1.3 - 2.0 V tFEOPT source SE0 interval of EOP see Figure 8 160 - 175 ns tFDEOP source jitter for differential transition see Figure 8 −2 - +5 ns to SE0 transition tJR1 receiver jitter to next transition −18.5 - +18.5 ns Product data sheet Rev. 05 — 9 April 2009 43 of 53, Table 9. Dynamic characteristics of USB pins (full-speed) …continued (LPC2364/66/68 only) CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(3V3), unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit tJR2 receiver jitter for paired transitions 10 % to 90 % −9 - +9 ns t EOP width at receiver must reject as [1]EOPR1 40 - - ns EOP; see Figure 8 tEOPR2 EOP width at receiver must accept as [1] 82 - - ns EOP; see Figure 8 [1] Characterized but not implemented as production test. Guaranteed by design. Table 10. Dynamic characteristics of flash Tamb = −40 °C to +85 °C for standard devices, −40 °C to +125 °C for LPC2364HBD only, unless otherwise specified; VDD(3V3) = 3.0 V to 3.6 V; all voltages are measured with respect to ground. Symbol Parameter Conditions Min Typ Max Unit Nendu endurance [1] 100000 - - cycles tret retention time powered; < 100 cycles [2] 10 - - years unpowered; < 100 cycles 20 - - years [1] Number of program/erase cycles. [2] tret specified for < 1ppm. Product data sheet Rev. 05 — 9 April 2009 44 of 53, 10.1 Timing tCHCX tCHCL tCLCX tCLCH Tcy(clk) 002aaa907 Fig 7. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) TPERIOD crossover point extended crossover point differential data lines source EOP width: tFEOPT differential data to SE0/EOP skew n × TPERIOD + tFDEOP receiver EOP width: tEOPR1, tEOPR2 002aab561 Fig 8. Differential data-to-EOP transition skew and EOP width shifting edges

SCK

sampling edges

MOSI MISO

tsu(SPI_MISO) 002aad326 Fig 9. MISO line set-up time in SSP Master mode Product data sheet Rev. 05 — 9 April 2009 45 of 53, 11. Application information 11.1 Suggested USB interface solutions (LPC2364/66/68 only) VDD(3V3) USB_UP_LED USB_CONNECT LPC23XX SoftConnect switch R1 1.5 kΩ

VBUS

USB_D+ RS = 33 Ω USB-B connector USB_D− RS = 33 Ω

VSS

002aac578 Fig 10. LPC2364/66/68 USB interface on a self-powered device VDD(3V3) R2 LPC23XX R1 USB_UP_LED 1.5 kΩ

VBUS

USB_D+ RS = 33 Ω USB-B connector USB_D− RS = 33 Ω

VSS

002aac579 Fig 11. LPC2364/66/68 USB interface on a bus-powered device Product data sheet Rev. 05 — 9 April 2009 46 of 53, 12. Package outline

LQFP100: plastic low profile quad flat package; 100 leads; body 14 x 14 x 1.4 mm SOT407-1

cyXA75 51 76 50

ZE

e E HE A A2 A (A 3 )1wMθbpLppin 1 index L 100 26 detailX125 ZDvMAewMbpDBHDvMB0510 mm scale DIMENSIONS (mm are the original dimensions)

A

UNIT A (1) (1) (1) (1)max. 1 A2 A3 bpcDEeHD HE L LpvwyZD ZE θ mm 1.6 0.15 1.45 0.27 0.20 14.1 14.1 16.25 16.25 0.75 1.15 1.15 o 0.25 0.5 1 0.2 0.08 0.08 7 0.05 1.35 0.17 0.09 13.9 13.9 15.75 15.75 0.45 0.85 0.85 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION ISSUE DATE IEC JEDEC JEITA PROJECTION 00-02-01 SOT407-1 136E20 MS-026 03-02-20

Fig 12. Package outline SOT407-1 (LQFP100)

Product data sheet Rev. 05 — 9 April 2009 47 of 53, TFBGA100: plastic thin fine-pitch ball grid array package; 100 balls; body9x9x0.7 mm SOT926-1DBAball A1 index area A2EAA1 detail X e1

C M

b ∅ vCABe 1/2 e ∅ wMCy1Cy

K J

e

H G F

e2

E

D 1/2 e

C B A

ball A1 index area12345678910

X

0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT Amax A1 A2bDEee1 e2vwyy1 mm 1.2 0.4 0.8 0.5 9.1 9.10.3 0.65 0.4 8.9 8.9 0.8 7.2 7.2 0.15 0.05 0.08 0.1 OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 05-12-09 SOT926-1 - - - - - - - - - 05-12-22

Fig 13. Package outline SOT926-1 (TFBGA100)

Product data sheet Rev. 05 — 9 April 2009 48 of 53, 13. Abbreviations Table 11. Abbreviations Acronym Description ADC Analog-to-Digital Converter AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BOD BrownOut Detection CAN Controller Area Network DAC Digital-to-Analog Converter DCC Debug Communication Channel DMA Direct Memory Access DSP Digital Signal Processing EOP End Of Packet ETM Embedded Trace Macrocell GPIO General Purpose Input/Output IrDA Infrared Data Association JTAG Joint Test Action Group MII Media Independent Interface MIIM Media Independent Interface Management PHY Physical Layer PLL Phase-Locked Loop PWM Pulse Width Modulator RMII Reduced Media Independent Interface SE0 Single Ended Zero SPI Serial Peripheral Interface SSI Serial Synchronous Interface SSP Synchronous Serial Port TTL Transistor-Transistor Logic UART Universal Asynchronous Receiver/Transmitter USB Universal Serial Bus Product data sheet Rev. 05 — 9 April 2009 49 of 53, 14. Revision history Table 12. Revision history Document ID Release date Data sheet status Change Supersedes notice LPC2364_65_66_67_68_5 20090409 Product data sheet - LPC2364_65_66_67_68_4 Modifications: • Added part LPC2364HBD100. • Section 7.2: Added sentence clarifying SRAM speeds for LPC2364HBD. • Table 5: Updated Vesd min/max. • Table 6: Updated ZDRV Table note [12]. • Table 6: Vhys, moved 0.4 from typ to min column. • Table 6: Ipu, added specs for >85 °C. • Table 6: Removed Rpu. • Table 8: CCLK and IRC, added specs for >85 °C. • Added Table 10. • Updated Figure 5. • Updated Figure 7. LPC2364_65_66_67_68_4 20080417 Product data sheet - LPC2364_66_68_3 LPC2364_66_68_3 20071220 Product data sheet - LPC2364_66_68_2 LPC2364_66_68_2 20071001 Preliminary data sheet - LPC2364_66_68_1 LPC2364_66_68_1 20070103 Preliminary data sheet - - Product data sheet Rev. 05 — 9 April 2009 50 of 53, 15. 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This document supersedes and replaces all information supplied prior authorization from national authorities. to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, 15.4 Trademarks authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or Notice: All referenced brands, product names, service names and trademarks malfunction of an NXP Semiconductors product can reasonably be expected are the property of their respective owners. to result in personal injury, death or severe property or environmental I2C-bus — logo is a trademark of NXP B.V. 16. Contact information

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Product data sheet Rev. 05 — 9 April 2009 51 of 53, 17. Contents 1 General description .1 7.20.1 Features .27 2 Features .1 7.21 Pulse width modulator .27 3 Applications .3 7.21.1 Features .28 7.22 Watchdog timer .28 4 Ordering information .3 7.22.1 Features .28 4.1 Ordering options .4 7.23 RTC and battery RAM .29 5 Block diagram .5 7.23.1 Features .29 6 Pinning information .6 7.24 Clocking and power control .29 6.1 Pinning .6 7.24.1 Crystal oscillators .29 6.2 Pin description .8 7.24.1.1 Internal RC oscillator .30 7 Functional description .16 7.24.1.2 Main oscillator .30 7.1 Architectural overview.16 7.24.1.3 RTC oscillator.30 7.2 On-chip flash programming memory .17 7.24.2 PLL.30 7.3 On-chip SRAM .17 7.24.3 Wake-up timer .30 7.4 Memory map.17 7.24.4 Power control .31 7.5 Interrupt controller .18 7.24.4.1 Idle mode .31 7.5.1 Interrupt sources.19 7.24.4.2 Sleep mode .31 7.6 Pin connect block .19 7.24.4.3 Power-down mode .32 7.7 General purpose DMA controller .19 7.24.4.4 Power domains.32 7.7.1 Features .19 7.25 System control .33 7.8 Fast general purpose parallel I/O .20 7.25.1 Reset .33 7.8.1 Features .21 7.25.2 Brownout detection .33 7.9 Ethernet .21 7.25.3 Code security (Code Read Protection - CRP) 33 7.9.1 Features .21 7.25.4 AHB .34 7.10 USB interface (LPC2364/66/68 only) .22 7.25.5 External interrupt inputs .34 7.10.1 USB device controller .22 7.25.6 Memory mapping control .34 7.10.2 Features .22 7.26 Emulation and debugging.34 7.11 CAN controller and acceptance filters 7.26.1 EmbeddedICE .34 (LPC2364/66/68 only).23 7.26.2 Embedded trace.35 7.11.1 Features .23 7.26.3 RealMonitor .35 7.12 10-bit ADC .23 8 Limiting values .36 7.12.1 Features .23 9 Static characteristics .37 7.13 10-bit DAC .24 10 Dynamic characteristics .43 7.13.1 Features .24 10.1 Timing .45 7.14 UARTs .24 11 Application information .46 7.14.1 Features .24 7.15 SPI serial I/O controller.24 11.1 Suggested USB interface solutions 7.15.1 Features .24 (LPC2364/66/68 only) .46 7.16 SSP serial I/O controller .25 12 Package outline .47 7.16.1 Features .25 13 Abbreviations .49 7.17 SD/MMC card interface (LPC2367/68 only) .25 14 Revision history .50 7.17.1 Features .25 7.18 I2C-bus serial I/O controllers.25 7.18.1 Features .26 7.19 I2S-bus serial I/O controllers.26 7.19.1 Features .26 7.20 General purpose 32-bit timers/external event counters .27 continued >> Product data sheet Rev. 05 — 9 April 2009 52 of 53, 15 Legal information.51 15.1 Data sheet status .51 15.2 Definitions .51 15.3 Disclaimers .51 15.4 Trademarks .51 16 Contact information.51 17 Contents .52 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: email is hidden Date of release: 9 April 2009 Document identifier: LPC2364_65_66_67_68_5]
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