Download: LPC2470DRDR D DA A RA RFFFATFDTDTDFlashless 16-bit/32-bit microcontroller; Ethernet,R ACAN,R LA RFCD, A USB 2.0 device/host/OTG, external memory interfaFcTeTFDRD

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LPC2470DRDR D DA A RA RFFFATFDTDTD Flashless 16-bit/32-bit microcontroller; Ethernet,R ACAN,R LA RFCD, A USB 2.0 device/host/OTG, external memory interfaFcTeTFDRD T

R D Rev. 01.01 — 24 September 2009 Preliminary dAFaTta sh AeFetDTRDA RF AT DR 1. General description AFT NXP Semiconductors designed the LPC2470 microcontroller, powered by the ARM7TDMI-S core, to be a highly integrated microcontroller for a wide range of applications that require advanced communications and high quality graphic displays. The LPC2470 microcontroller is flashless. The LPC2470, with real-time debug interfaces that include both JTAG and embedded trace, can execute both 32-bit ARM and 16-bit Thumb instructions. The LPC2470 microcontroller incorporates an LCD controller, a 10/100 Ethernet Media Access Controller (MAC), a USB full-speed device/host/OTG controller with 4 kB of endpoint RAM, four UARTs, two Controller Area Network (CAN) channels, an SPI interface, two Synchronous Serial Ports (SSP), three I2C interfaces, and an I2S interface. Supporting this collection of serial communications interfaces are the following feature components; an on-chip 4 MHz internal oscillator, 98 kB of total RAM consisting of 64 kB of local SRAM, 16 kB SRAM for Ethernet, 16 kB SRAM for general purpose DMA, 2 kB of battery powered SRAM, and an External Memory Controller (EMC). These features make this device optimally suited for portable electronics and Point-of-Sale (POS) applications. Complementing the many serial communication controllers, versatile clocking capabilities, and memory features are various 32-bit timers, a 10-bit ADC, 10-bit DAC, two PWM units, and up to 160 fast GPIO lines. The LPC2470 connects 64 of the GPIO pins to the hardware based Vector Interrupt Controller (VIC) that means these external inputs can generate edge-triggered interrupts. All of these features make the LPC2470 particularly suitable for industrial control and medical systems. 2. Features ARM7TDMI-S processor, running at up to 72 MHz. 98 kB on-chip SRAM includes: 64 kB of SRAM on the ARM local bus for high performance CPU access. 16 kB SRAM for Ethernet interface. Can also be used as general purpose SRAM. 16 kB SRAM for general purpose DMA use also accessible by the USB. 2 kB SRAM data storage powered from the Real-Time Clock (RTC) power domain. LCD controller, supporting both Super-Twisted Nematic (STN) and Thin-Film Transistors (TFT) displays. Dedicated DMA controller. Selectable display resolution (up to 1024 × 768 pixels). Supports up to 24-bit true-color mode. Dual Advanced High-performance Bus (AHB) system allows simultaneous Ethernet DMA, and USB DMA with no contention.,

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TTDTEMC provides support for asynchronous static memory devices such asD RAAM, RORMA

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and flash, as well as dynamic memories such as single data rate SDRAM. FTFDTDAdvanced Vectored Interrupt Controller (VIC), supporting up to 32 vectored inteRrArupts. RA General Purpose DMA controller (GPDMA) on AHB that can be used with the SSFPT, D I2S-bus, and Secure Digital/MultiMediaCard (SD/MMC) interface as well as for RA memory-to-memory transfers. FT Serial Interfaces: Ethernet MAC with MII/RMII interface and associated DMA controller. These functions reside on an independent AHB. USB 2.0 full-speed dual port device/host/OTG controller with on-chip PHY and associated DMA controller. Four UARTs with fractional baud rate generation, one with modem control I/O, one with IrDA support, all with FIFO. CAN controller with two channels. SPI controller. Two SSP controllers, with FIFO and multi-protocol capabilities. One is an alternate for the SPI port, sharing its interrupt. SSPs can be used with the GPDMA controller. Three I2C-bus interfaces (one with open-drain and two with standard port pins). I2S (Inter-IC Sound) interface for digital audio input or output. It can be used with the GPDMA. Other peripherals: SD/MMC memory card interface. 160 General purpose I/O pins with configurable pull-up/down resistors. 10-bit ADC with input multiplexing among 8 pins. 10-bit DAC. Four general purpose timers/counters with 8 capture inputs and 10 compare outputs. Each timer block has an external count input. Two PWM/timer blocks with support for three-phase motor control. Each PWM has an external count inputs. RTC with separate power domain. Clock source can be the RTC oscillator or the APB clock. 2 kB SRAM powered from the RTC power pin, allowing data to be stored when the rest of the chip is powered off. WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock. Single 3.3 V power supply (3.0 V to 3.6 V). 4 MHz internal RC oscillator trimmed to 1 % accuracy that can optionally be used as the system clock. Four reduced power modes: idle, sleep, power-down, and deep power-down. Four external interrupt inputs configurable as edge/level sensitive. All pins on port 0 and port 2 can be used as edge sensitive interrupt sources. Processor wake-up from Power-down mode via any interrupt able to operate during Power-down mode (includes external interrupts, RTC interrupt, USB activity, Ethernet wake-up interrupt, CAN bus activity, port 0/2 pin interrupt). Two independent power domains allow fine tuning of power consumption based on needed features. Preliminary data sheet Rev. 01.01 — 24 September 2009 2 of 83,

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TTDTEach peripheral has its own clock divider for further power saving. TheseD RdAividers RhAelp

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reduce active power by 20 % to 30 %. FTFDTDBrownout detect with separate thresholds for interrupt and forced reset. RA RA On-chip power-on reset. FT D On-chip crystal oscillator with an operating range of 1 MHz to 24 MHz. RAF On-chip PLL allows CPU operation up to the maximum CPU rate without the need forTahigh frequency crystal. May be run from the main oscillator, the internal RC oscillator, or the RTC oscillator. Boundary scan for simplified board testing. Versatile pin function selections allow more possibilities for using on-chip peripheral functions. Standard ARM test/debug interface for compatibility with existing tools. Emulation trace module supports real-time trace. 3. Applications Industrial control Medical systems Portable electronics Point-of-Sale (POS) equipment 4. Ordering information Table 1. Ordering information Type number Package Name Description Version LPC2470FBD208 LQFP208 plastic low profile quad flat package; 208 leads; body 28 × 28 × 1.4 mm SOT459-1 LPC2470FET208 TFBGA208 plastic thin fine-pitch ball grid array package; 208 balls; SOT950-1 body 15 × 15 × 0.7 mm 4.1 Ordering options Table 2. Ordering options Type number Flash SRAM (kB) External Ethernet USB SD/ GP Temp (kB) bus OTG/ MMC DMA range OHCI/ device + 4 kB

FIFO

LPC2470FBD208 n/a 64 16 16 2 98 Full MII/RMII yes 2 yes yes81−40 °C 32-bit to +85 °C LPC2470FET208 n/a 64 16 16 2 98 Full MII/RMII yes 2 yes yes81−40 °C 32-bit to +85 °C Local bus Ethernet buffer GP/USB

RTC

Total CAN channels ADC channels DAC channels Preliminary data sheet Rev. 01.01 — 24 September 2009 3 of 83,

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5. Block diagram D

T R D T D A RF ATFDT

R DA RF A XTAL1TDTMS TDI trace signals XTAL2 VDD(3V3) R V ADDA F TRST TCK TDO TRESET EXTIN0 DBGEN

VREF

LPC2470 SYSTEM P0, P1, P2, 64 kB PLL V , V , VTEST/DEBUG FUNCTIONS SSA SSCORE SSIO P3, P4 SRAM VINTERFACE DD(DCDC)(3V3) system HIGH-SPEED INTERNAL RCclock GPIO INTERNAL ARM7TDMI-S OSCILLATOR 160 PINS SRAM TOTAL CONTROLLER EXTERNAL D[31:0] 16 kB VIC MEMORY A[23:0]

SRAM

CONTROLLER control lines AHB2 AHB1 AHB AHB BRIDGE BRIDGE 16 kB MASTER AHB TO SLAVE USB DEVICE/ VBUS ETHERNET SRAM PORT AHB BRIDGE PORT HOST/OTG WITH port1MII/RMII MAC WITH 4 kB RAM AND DMA port2

DMA

AHB TO APB BRIDGE GP DMA

CONTROLLER

EINT3 to EINT0 EXTERNAL INTERRUPTS LCD INTERFACE 8 × LCD control P0, P2 LCDVD[23:0]WITH DMA LCDCLKIN 2 × CAP0/CAP1/ CAPTURE/COMPARE CAP2/CAP3 TIMER0/TIMER1/ 4 × MAT2/MAT3, TIMER2/TIMER3 2 × MAT0, 2 3 × I2SRX 3 × MAT1ISINTERFACE 3 × I2STX 6 × PWM0/PWM1 PWM0, PWM1 SCK, SCK0 1 × PCAP0, MOSI, MOSI0 2 × PCAP1 SPI, SSP0 INTERFACE MISO, MISO0 SSEL, SSEL0 LEGACY GPI/O P0, P1 64 PINS TOTAL SCK1 MOSI1 SSP1 INTERFACE MISO1 8 × AD0 A/D CONVERTER SSEL1 MCICLK, MCIPWR AOUT D/A CONVERTER SD/MMC CARD INTERFACE MCICMD, MCIDAT[3:0] VBAT 2 kB BATTERY RAM TXD0, TXD2, TXD3 UART0, UART2, UART3 RXD0, RXD2, RXD3 power domain 2 RTCX1 REAL-RTC TIME UART1 TXD1, DTR1, RTS1RTCX2 OSCILLATOR CLOCK RXD1, DSR1, CTS1, DCD1, RI1

ALARM

CAN1, CAN2 RD1, RD2 WATCHDOG TIMER TD1, TD2 SCL0, SCL1, SCL2 I2C0, I2C1, I2C2 SYSTEM CONTROL SDA0, SDA1, SDA2 002aad317

Fig 1. LPC2470 block diagram EMULATION

TRACE MODULE Preliminary data sheet Rev. 01.01 — 24 September 2009 4 of 83,

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6. Pinning information DR DR DAF ATFDTRDR 6.1 Pinning AF AT D

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1 156 LPC2470FBD208 52 105 002aad318 Fig 2. LPC2470 pinning LQFP208 package ball A1 index area246810 12 14 161357911 13 15 17

A B C D E F G H

J LPC2470FET208

K L M N P R T U

002aad319 Transparent top view Fig 3. LPC2470 pinning TFBGA208 package Table 3. Pin allocation table Pin Symbol Pin Symbol Pin Symbol Pin Symbol RowA1P3[27]/D27/ 2 VSSIO 3 P1[0]/ENET_TXD0 4 P4[31]/CS1 CAP1[0]/PWM1[4] 5 P1[4]/ENET_TX_EN 6 P1[9]/ENET_RXD0 7 P1[14]/ENET_RX_ER 8 P1[15]/ ENET_REF_CLK/ ENET_RX_CLK 9 P1[17]/ENET_MDIO 10 P1[3]/ENET_TXD3/ 11 P4[15]/A15 12 VSSIO MCICMD/PWM0[2] 53 208 104 157 Preliminary data sheet Rev. 01.01 — 24 September 2009 5 of 83,

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Table 3. Pin allocation tableDDD…continued RA RA Pin Symbol Pin Symbol Pin Symbol Pin Symbol FTFDTD13 P3[20]/D20/ 14 P1[11]/ENET_RXD2/ 15 P0[8]/I2STX_WS/ 16 P1[12]/ENET_RXRDA3/ RA PWM0[5]/DSR1 MCIDAT2/PWM0[6] LCDVD[16]/MISO1/ MCIDAT3/PCAP0[0]FT MAT2[2] DRA 17 P1[5]/ENET_TX_ER/ - - - FT MCIPWR/PWM0[3] RowB1P3[2]/D2 2 P3[10]/D10 3 P3[1]/D1 4 P3[0]/D0 5 P1[1]/ENET_TXD1 6 VSSIO 7 P4[30]/CS0 8 P4[24]/OE 9 P4[25]/WE 10 P4[29]/BLS3/MAT2[1]/ 11 P1[6]/ENET_TX_CLK/ 12 P0[4]/I2SRX_CLK/ LCDVD[7]/LCDVD[11]/ MCIDAT0/PWM0[4] LCDVD[0]/RD2/CAP2[0] LCDVD[3]/RXD3 13 VDD(3V3) 14 P3[19]/D19/ 15 P4[14]/A14 16 P4[13]/A13 PWM0[4]/DCD1 17 P2[0]/PWM1[1]/TXD1/ - - - TRACECLK/LCDPWR RowC1P3[13]/D13 2 TDI 3 RTCK 4 P0[2]/TXD0 5 P3[9]/D9 6 P3[22]/D22/ 7 P1[8]/ENET_CRS_DV/ 8 P1[10]/ENET_RXD1 PCAP0[0]/RI1 ENET_CRS 9 VDD(3V3) 10 P3[21]/D21/ 11 P4[28]/BLS2/MAT2[0]/ 12 P0[5]/I2SRX_WS/ PWM0[6]/DTR1 LCDVD[6]/LCDVD[10]/ LCDVD[1]/TD2/CAP2[1] LCDVD[2]/TXD3 13 P0[7]/I2STX_CLK/ 14 P0[9]/I2STX_SDA/ 15 P3[18]/D18/ 16 P4[12]/A12 LCDVD[9]/SCK1/ LCDVD[17]/MOSI1/ PWM0[3]/CTS1 MAT2[1] MAT2[3] 17 VDD(3V3) - - - RowD1TRST 2 P3[28]/D28/ 3 TDO 4 P3[12]/D12 CAP1[1]/PWM1[5] 5 P3[11]/D11 6 P0[3]/RXD0 7 VDD(3V3) 8 P3[8]/D8 9 P1[2]/ENET_TXD2/ 10 P1[16]/ENET_MDC 11 VDD(DCDC)(3V3) 12 VSSCORE MCICLK/PWM0[1] 13 P0[6]/I2SRX_SDA/ 14 P1[7]/ENET_COL/ 15 P2[2]/PWM1[3]/CTS1/ 16 P1[13]/ENET_RX_DV LCDVD[8]/SSEL1/ MCIDAT1/PWM0[5] PIPESTAT1/LCDDCLK MAT2[0] 17 P2[4]/PWM1[5]/ - - - DSR1/TRACESYNC/ LCDENAB/LCDM RowE1P0[26]/AD0[3]/ 2 TCK 3 TMS 4 P3[3]/D3 AOUT/RXD3 14 P2[1]/PWM1[2]/RXD1/ 15 VSSIO 16 P2[3]/PWM1[4]/DCD1/ 17 P2[6]/PCAP1[0]/RI1/ PIPESTAT0/LCDLE PIPESTAT2/LCDFP TRACEPKT1/ LCDVD[0]/LCDVD[4] RowF1P0[25]/AD0[2]/ 2 P3[4]/D4 3 P3[29]/D29/ 4 DBGEN I2SRX_SDA/TXD3 MAT1[0]/PWM1[6] Preliminary data sheet Rev. 01.01 — 24 September 2009 6 of 83,

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Table 3. Pin allocation tableDDD…continued RA RA Pin Symbol Pin Symbol Pin Symbol Pin Symbol FTFDTD14 P4[11]/A11 15 P3[17]/D17/ 16 P2[5]/PWM1[6]/ 17 P3[16]/D16/ RA RA PWM0[2]/RXD1 DTR1/TRACEPKT0/ PWM0[1]/TXD1 FT LCDLP DRA Row G FT 1 P3[5]/D5 2 P0[24]/AD0[1]/ 3 VDD(3V3) 4 VDDA I2SRX_WS/CAP3[1] 14 n.c. 15 P4[27]/BLS1 16 P2[7]/RD2/ 17 P4[10]/A10 RTS1/TRACEPKT2/ LCDVD[1]/LCDVD[5] RowH1P0[23]/AD0[0]/ 2 P3[14]/D14 3 P3[30]/D30/ 4 VDD(DCDC)(3V3) I2SRX_CLK/CAP3[0] MAT1[1]/RTS1 14 VSSIO 15 P2[8]/TD2/TXD2/ 16 P2[9]/ 17 P4[9]/A9 TRACEPKT3/ USB_CONNECT1/ LCDVD[2]/LCDVD[6] RXD2/EXTIN0/ LCDVD[3]/LCDVD[7] RowJ1P3[6]/D6 2 VSSA 3 P3[31]/D31/MAT1[2] 4 n.c. 14 P0[16]/RXD1/ 15 P4[23]/A23/ 16 P0[15]/TXD1/ 17 P4[8]/A8 SSEL0/SSEL RXD2/MOSI1 SCK0/SCK RowK1VREF 2 RTCX1 3 RSTOUT 4 VSSCORE 14 P4[22]/A22/ 15 P0[18]/DCD1/ 16 VDD(3V3) 17 P0[17]/CTS1/ TXD2/MISO1 MOSI0/MOSI MISO0/MISO RowL1P3[7]/D7 2 RTCX2 3 VSSIO 4 P2[30]/DQMOUT2/ MAT3[2]/SDA2 14 n.c. 15 P4[26]/BLS0 16 P4[7]/A7 17 P0[19]/DSR1/ MCICLK/SDA1 RowM1P3[15]/D15 2 RESET 3 VBAT 4 XTAL1 14 P4[6]/A6 15 P4[21]/A21/ 16 P0[21]/RI1/ 17 P0[20]/DTR1/ SCL2/SSEL1 MCIPWR/RD1 MCICMD/SCL1 RowN1ALARM 2 P2[31]/DQMOUT3/ 3 P2[29]/DQMOUT1 4 XTAL2 MAT3[3]/SCL2 14 P2[12]/EINT2/ 15 P2[10]/EINT0 16 VSSIO 17 P0[22]/RTS1/ LCDVD[4]/LCDVD[8]/ MCIDAT0/TD1 LCDVD[3]/LCDVD[18]/ MCIDAT2/I2STX_WS RowP1P1[31]/USB_OVRCR2/ 2 P1[30]/USB_PWRD2/ 3 P2[27]/CKEOUT3/ 4 P2[28]/DQMOUT0 SCK1/AD0[5] VBUS/AD0[4] MAT3[1]/MOSI0 5 P2[24]/CKEOUT0 6 VDD(3V3) 7 P1[18]/USB_UP_LED1/ 8 VDD(3V3) PWM1[1]/CAP1[0] Preliminary data sheet Rev. 01.01 — 24 September 2009 7 of 83,

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Table 3. Pin allocation tableDDD…continued RA RA Pin Symbol Pin Symbol Pin Symbol Pin Symbol FTFDTD9P1[23]/USB_RX_DP1/ 10 VSSCORE 11VRRDD(DCDC)(3V3) 12 VSSIOAALCDVD[9]/LCDVD[13]/ FT PWM1[4]/MISO0 DRA 13 P2[15]/CS3/ 14 P4[17]/A17 15 P4[18]/A18 16 P4[19]/A19 FT CAP2[1]/SCL1 17 VDD(3V3) - - - RowR1P0[12]/USB_PPWR2/ 2 P0[13]/USB_UP_LED2/ 3 P0[28]/SCL0 4 P2[25]/CKEOUT1 MISO1/AD0[6] MOSI1/AD0[7] 5 P3[24]/D24/ 6 P0[30]/USB_D−1 7 P2[19]/CLKOUT1 8 P1[21]/USB_TX_DM1/ CAP0[1]/PWM1[1] LCDVD[7]/LCDVD[11]/ PWM1[3]/SSEL0 9 VSSIO 10 P1[26]/USB_SSPND1/ 11 P2[16]/CAS 12 P2[14]/CS2/CAP2[0]/ LCDVD[12]/LCDVD[20]/ SDA1 PWM1[6]/CAP0[0] 13 P2[17]/RAS 14 P0[11]/RXD2/SCL2/ 15 P4[4]/A4 16 P4[5]/A5 MAT3[1] 17 P4[20]/A20/SDA2/SCK1 - - - RowT1P0[27]/SDA0 2 P0[31]/USB_D+2 3 P3[26]/D26/ 4 P2[26]/CKEOUT2/ MAT0[1]/PWM1[3] MAT3[0]/MISO0 5 VSSIO 6 P3[23]/D23/ 7 P0[14]/USB_HSTEN2/ 8 P2[20]/DYCS0 CAP0[0]/PCAP1[0] USB_CONNECT2/ SSEL1 9 P1[24]/USB_RX_DM1/ 10 P1[25]/USB_LS1/ 11 P4[2]/A2 12 P1[27]/USB_INT1/ LCDVD[10]/LCDVD[14]/ LCDVD[11]/LCDVD[15]/ LCDVD[13]/LCDVD[21]/ PWM1[5]/MOSI0 USB_HSTEN1/MAT1[1] USB_OVRCR1/CAP0[1] 13 P1[28]/USB_SCL1/ 14 P0[1]/TD1/RXD3/SCL1 15 P0[10]/TXD2/SDA2/ 16 P2[13]/EINT3/ LCDVD[14]/LCDVD[22]/ MAT3[0] LCDVD[5]/LCDVD[9]/ PCAP1[0]/MAT0[0] LCDVD[19]/MCIDAT3/ I2STX_SDA 17 P2[11]/EINT1/ - - - LCDCLKIN/ MCIDAT1/I2STX_CLK RowU1USB_D−2 2 P3[25]/D25/ 3 P2[18]/CLKOUT0 4 P0[29]/USB_D+1 MAT0[0]/PWM1[2] 5 P2[23]/DYCS3/ 6 P1[19]/USB_TX_E1/ 7 P1[20]/USB_TX_DP1/ 8 P1[22]/USB_RCV1/ CAP3[1]/SSEL0 USB_PPWR1/CAP1[1] LCDVD[6]/LCDVD[10]/ LCDVD[8]/LCDVD[12]/ PWM1[2]/SCK0 USB_PWRD1/MAT1[0] 9 P4[0]/A0 10 P4[1]/A1 11 P2[21]/DYCS1 12 P2[22]/DYCS2/ CAP3[0]/SCK0 13 VDD(3V3) 14 P1[29]/USB_SDA1/ 15 P0[0]/RD1/TXD3/SDA1 16 P4[3]/A3 LCDVD[15]/LCDVD[23]/ PCAP1[1]/MAT0[1] 17 P4[16]/A16 - - - Preliminary data sheet Rev. 01.01 — 24 September 2009 8 of 83,

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6.2 Pin description D

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R DAF AT FT Table 4. Pin descriptionDRDA RA Symbol Pin Ball Type Description FT D P0[0] to P0[31] I/O Port 0: Port 0 is a 32-bit I/O port with individual direction controls for eachR A bit. The operation of port 0 pins depends upon the pin function selected FT via the pin connect block. P0[0]/RD1/TXD3/ 94[1] U15[1] I/O P0[0] — General purpose digital input/output pin. SDA1 I RD1 — CAN1 receiver input. O TXD3 — Transmitter output for UART3. I/O SDA1 — I2C1 data input/output (this is not an open-drain pin). P0[1]/TD1/RXD3/ 96[1] T14[1] I/O P0[1] — General purpose digital input/output pin. SCL1 O TD1 — CAN1 transmitter output. I RXD3 — Receiver input for UART3. I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin). P0[2]/TXD0 202[1] C4[1] I/O P0[2] — General purpose digital input/output pin. O TXD0 — Transmitter output for UART0. P0[3]/RXD0 204[1] D6[1] I/O P0[3] — General purpose digital input/output pin. I RXD0 — Receiver input for UART0. P0[4]/I2SRX_CLK/ 168[1] B12[1] I/O P0[4] — General purpose digital input/output pin. LCDVD[0]/RD2/ I/O I2SRX_CLK — I2S Receive clock. It is driven by the master and received CAP2[0] by the slave. Corresponds to the signal SCK in the I2S-bus specification.[2] O LCDVD[0] — LCD data.[2] I RD2 — CAN2 receiver input. I CAP2[0] — Capture input for Timer 2, channel 0. P0[5]/I2SRX_WS/ 166[1] C12[1] I/O P0[5] — General purpose digital input/output pin. LCDVD[1]/TD2/ I/O I2SRX_WS — I2S Receive word select. It is driven by the master and CAP2[1] received by the slave. Corresponds to the signal WS in the I2S-bus specification.[2] O LCDVD[1] — LCD data.[2] O TD2 — CAN2 transmitter output. I CAP2[1] — Capture input for Timer 2, channel 1. P0[6]/I2SRX_SDA/ 164[1] D13[1] I/O P0[6] — General purpose digital input/output pin. LCDVD[8]/ I/O I2SRX_SDA — I2S Receive data. It is driven by the transmitter and read SSEL1/MAT2[0] by the receiver. Corresponds to the signal SD in the I2S-bus specification.[2] O LCDVD[8] — LCD data.[2] I/O SSEL1 — Slave Select for SSP1. O MAT2[0] — Match output for Timer 2, channel 0. Preliminary data sheet Rev. 01.01 — 24 September 2009 9 of 83,

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Table 4. Pin descriptionDDD…continued RA RA Symbol Pin Ball Type Description FTFDTDP0[7]/I2STX_CLK/ 162[1] C13[1] I/O P0[7] — General purpose digital input/output pin. RA RA LCDVD[9]/SCK1/ FI/O I2STX_CLK — I2S transmit clock. It is driven by the master and receivTe MAT2[1] D d by the slave. Corresponds to the signal SCK in the I2S-bus RA specification.[2] FT O LCDVD[9] — LCD data.[2] I/O SCK1 — Serial Clock for SSP1. O MAT2[1] — Match output for Timer 2, channel 1. P0[8]/I2STX_WS/ 160[1] A15[1] I/O P0[8] — General purpose digital input/output pin. LCDVD[16]/ I/O I2STX_WS — I2S Transmit word select. It is driven by the master and MISO1/MAT2[2] received by the slave. Corresponds to the signal WS in the I2S-bus specification.[2] O LCDVD[16] — LCD data.[2] I/O MISO1 — Master In Slave Out for SSP1. O MAT2[2] — Match output for Timer 2, channel 2. P0[9]/I2STX_SDA/ 158[1] C14[1] I/O P0[9] — General purpose digital input/output pin. LCDVD[17]/ I/O I2STX_SDA — I2S transmit data. It is driven by the transmitter and read MOSI1/MAT2[3] by the receiver. Corresponds to the signal SD in the I2S-bus specification.[2] O LCDVD[17] — LCD data.[2] I/O MOSI1 — Master Out Slave In for SSP1. O MAT2[3] — Match output for Timer 2, channel 3. P0[10]/TXD2/ 98[1] T15[1] I/O P0[10] — General purpose digital input/output pin. SDA2/MAT3[0] O TXD2 — Transmitter output for UART2. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). O MAT3[0] — Match output for Timer 3, channel 0. P0[11]/RXD2/ 100[1] R14[1] I/O P0[11] — General purpose digital input/output pin. SCL2/MAT3[1] I RXD2 — Receiver input for UART2. I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). O MAT3[1] — Match output for Timer 3, channel 1. P0[12]/ 41[3] R1[3] I/O P0[12] — General purpose digital input/output pin. USB_PPWR2/ O USB_PPWR2 — Port Power enable signal for USB port 2. MISO1/AD0[6] I/O MISO1 — Master In Slave Out for SSP1. I AD0[6] — A/D converter 0, input 6. P0[13]/ 45[3] R2[3] I/O P0[13] — General purpose digital input/output pin. USB_UP_LED2/ O USB_UP_LED2 — USB port 2 GoodLink LED indicator. It is LOW when MOSI1/AD0[7] device is configured (non-control endpoints enabled). It is HIGH when the device is not configured or during global suspend. I/O MOSI1 — Master Out Slave In for SSP1. I AD0[7] — A/D converter 0, input 7. Preliminary data sheet Rev. 01.01 — 24 September 2009 10 of 83,

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Table 4. Pin descriptionDDD…continued RA RA Symbol Pin Ball Type Description FTFDTDP0[14]/ 69[1] T7[1] I/O P0[14] — General purpose digital input/output pin. RA RA USB_HSTEN2/ FO USB_HSTEN2 — Host Enabled status for USB port 2. T USB_CONNECT2/ DR SSEL1 O USB_CONNECT2 — SoftConnect control for USB port 2. Signal used to

AF

switch an external 1.5 kΩ resistor under software control. Used with the T SoftConnect USB feature. I/O SSEL1 — Slave Select for SSP1. P0[15]/TXD1/ 128[1] J16[1] I/O P0[15] — General purpose digital input/output pin. SCK0/SCK O TXD1 — Transmitter output for UART1. I/O SCK0 — Serial clock for SSP0. I/O SCK — Serial clock for SPI. P0[16]/RXD1/ 130[1] J14[1] I/O P0 [16] — General purpose digital input/output pin. SSEL0/SSEL I RXD1 — Receiver input for UART1. I/O SSEL0 — Slave Select for SSP0. I/O SSEL — Slave Select for SPI. P0[17]/CTS1/ 126[1] K17[1] I/O P0[17] — General purpose digital input/output pin. MISO0/MISO I CTS1 — Clear to Send input for UART1. I/O MISO0 — Master In Slave Out for SSP0. I/O MISO — Master In Slave Out for SPI. P0[18]/DCD1/ 124[1] K15[1] I/O P0[18] — General purpose digital input/output pin. MOSI0/MOSI I DCD1 — Data Carrier Detect input for UART1. I/O MOSI0 — Master Out Slave In for SSP0. I/O MOSI — Master Out Slave In for SPI. P0[19]/DSR1/ 122[1] L17[1] I/O P0[19] — General purpose digital input/output pin. MCICLK/SDA1 I DSR1 — Data Set Ready input for UART1. O MCICLK — Clock output line for SD/MMC interface. I/O SDA1 — I2C1 data input/output (this is not an open-drain pin). P0[20]/DTR1/ 120[1] M17[1] I/O P0[20] — General purpose digital input/output pin. MCICMD/SCL1 O DTR1 — Data Terminal Ready output for UART1. I/O MCICMD — Command line for SD/MMC interface. I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin). P0[21]/RI1/ 118[1] M16[1] I/O P0[21] — General purpose digital input/output pin. MCIPWR/RD1 I RI1 — Ring Indicator input for UART1. O MCIPWR — Power Supply Enable for external SD/MMC power supply. I RD1 — CAN1 receiver input. P0[22]/RTS1/ 116[1] N17[1] I/O P0[22] — General purpose digital input/output pin. MCIDAT0/TD1 O RTS1 — Request to Send output for UART1. I/O MCIDAT0 — Data line 0 for SD/MMC interface. O TD1 — CAN1 transmitter output. Preliminary data sheet Rev. 01.01 — 24 September 2009 11 of 83,

DR

Table 4. Pin descriptionDDD…continued RA RA Symbol Pin Ball Type Description FTFDTDP0[23]/AD0[0]/ 18[3] H1[3] I/O P0[23] — General purpose digital input/output pin. RA RA I2SRX_CLK/ FI AD0[0] — A/D converter 0, input 0. T CAP3[0] DR I/O I2SRX_CLK — Receive Clock. It is driven by the master and received by AF the slave. Corresponds to the signal SCK in the I2S-bus specification. T I CAP3[0] — Capture input for Timer 3, channel 0. P0[24]/AD0[1]/ 16[3] G2[3] I/O P0[24] — General purpose digital input/output pin. I2SRX_WS/ I AD0[1] — A/D converter 0, input 1. CAP3[1] I/O I2SRX_WS — Receive Word Select. It is driven by the master and received by the slave. Corresponds to the signal WS in the I2S-bus specification. I CAP3[1] — Capture input for Timer 3, channel 1. P0[25]/AD0[2]/ 14[3] F1[3] I/O P0[25] — General purpose digital input/output pin. I2SRX_SDA/ I AD0[2] — A/D converter 0, input 2. TXD3 I/O I2SRX_SDA — Receive data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. O TXD3 — Transmitter output for UART3. P0[26]/AD0[3]/ 12[3][4] E1[3][4] I/O P0[26] — General purpose digital input/output pin. AOUT/RXD3 I AD0[3] — A/D converter 0, input 3. O AOUT — D/A converter output. I RXD3 — Receiver input for UART3. P0[27]/SDA0 50[5] T1[5] I/O P0[27] — General purpose digital input/output pin. I/O SDA0 — I2C0 data input/output. Open-drain output (for I2C-bus compliance). P0[28]/SCL0 48[5] R3[5] I/O P0[28] — General purpose digital input/output pin. I/O SCL0 — I2C0 clock input/output. Open-drain output (for I2C-bus compliance). P0[29]/USB_D+1 61[6] U4[6] I/O P0[29] — General purpose digital input/output pin. I/O USB_D+1 — USB port 1 bidirectional D+ line. P0[30]/USB_D−1 62[6] R6[6] I/O P0[30] — General purpose digital input/output pin. I/O USB_D−1 — USB port 1 bidirectional D− line. P0[31]/USB_D+2 51[6] T2[6] I/O P0[31] — General purpose digital input/output pin. I/O USB_D+2 — USB port 2 bidirectional D+ line. P1[0] to P1[31] I/O Port 1: Port 1 is a 32 bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. P1[0]/ 196[1] A3[1] I/O P1[0] — General purpose digital input/output pin. ENET_TXD0 O ENET_TXD0 — Ethernet transmit data 0 (RMII/MII interface). P1[1]/ 194[1] B5[1] I/O P1[1] — General purpose digital input/output pin. ENET_TXD1 O ENET_TXD1 — Ethernet transmit data 1 (RMII/MII interface). P1[2]/ 185[1] D9[1] I/O P1[2] — General purpose digital input/output pin. ENET_TXD2/ O ENET_TXD2 — Ethernet transmit data 2 (MII interface). MCICLK/ PWM0[1] O MCICLK — Clock output line for SD/MMC interface. O PWM0[1] — Pulse Width Modulator 0, output 1. Preliminary data sheet Rev. 01.01 — 24 September 2009 12 of 83,

DR

Table 4. Pin descriptionDDD…continued RA RA Symbol Pin Ball Type Description FTFDTDP1[3]/ 177[1] A10[1] I/O P1[3] — General purpose digital input/output pin. RA R ENET_TXD3/ F

A

O ENET_TXD3 — Ethernet transmit data 3 (MII interface). T MCICMD/ D R PWM0[2] I/O MCICMD — Command line for SD/MMC interface.

AFT

O PWM0[2] — Pulse Width Modulator 0, output 2. P1[4]/ 192[1] A5[1] I/O P1[4] — General purpose digital input/output pin. ENET_TX_EN O ENET_TX_EN — Ethernet transmit data enable (RMII/MII interface). P1[5]/ 156[1] A17[1] I/O P1[5] — General purpose digital input/output pin. ENET_TX_ER/ O ENET_TX_ER — Ethernet Transmit Error (MII interface). MCIPWR/ PWM0[3] O MCIPWR — Power Supply Enable for external SD/MMC power supply. O PWM0[3] — Pulse Width Modulator 0, output 3. P1[6]/ 171[1] B11[1] I/O P1[6] — General purpose digital input/output pin. ENET_TX_CLK/ I ENET_TX_CLK — Ethernet Transmit Clock (MII interface). MCIDAT0/ PWM0[4] I/O MCIDAT0 — Data line 0 for SD/MMC interface. O PWM0[4] — Pulse Width Modulator 0, output 4. P1[7]/ 153[1] D14[1] I/O P1[7] — General purpose digital input/output pin. ENET_COL/ I ENET_COL — Ethernet Collision detect (MII interface). MCIDAT1/ PWM0[5] I/O MCIDAT1 — Data line 1 for SD/MMC interface. O PWM0[5] — Pulse Width Modulator 0, output 5. P1[8]/ 190[1] C7[1] I/O P1[8] — General purpose digital input/output pin. ENET_CRS_DV/ I ENET_CRS_DV/ENET_CRS — Ethernet Carrier Sense/Data Valid (RMII ENET_CRS interface)/ Ethernet Carrier Sense (MII interface). P1[9]/ 188[1] A6[1] I/O P1[9] — General purpose digital input/output pin. ENET_RXD0 I ENET_RXD0 — Ethernet receive data 0 (RMII/MII interface). P1[10]/ 186[1] C8[1] I/O P1[10] — General purpose digital input/output pin. ENET_RXD1 I ENET_RXD1 — Ethernet receive data 1 (RMII/MII interface). P1[11]/ 163[1] A14[1] I/O P1[11] — General purpose digital input/output pin. ENET_RXD2/ I ENET_RXD2 — Ethernet Receive Data 2 (MII interface). MCIDAT2/ PWM0[6] I/O MCIDAT2 — Data line 2 for SD/MMC interface. O PWM0[6] — Pulse Width Modulator 0, output 6. P1[12]/ 157[1] A16[1] I/O P1[12] — General purpose digital input/output pin. ENET_RXD3/ I ENET_RXD3 — Ethernet Receive Data (MII interface). MCIDAT3/ PCAP0[0] I/O MCIDAT3 — Data line 3 for SD/MMC interface. I PCAP0[0] — Capture input for PWM0, channel 0. P1[13]/ 147[1] D16[1] I/O P1[13] — General purpose digital input/output pin. ENET_RX_DV I ENET_RX_DV — Ethernet Receive Data Valid (MII interface). P1[14]/ 184[1] A7[1] I/O P1[14] — General purpose digital input/output pin. ENET_RX_ER I ENET_RX_ER — Ethernet receive error (RMII/MII interface). P1[15]/ 182[1] A8[1] I/O P1[15] — General purpose digital input/output pin. ENET_REF_CLK/ I ENET_REF_CLK/ENET_RX_CLK — Ethernet Reference Clock (RMII ENET_RX_CLK interface)/ Ethernet Receive Clock (MII interface). Preliminary data sheet Rev. 01.01 — 24 September 2009 13 of 83,

DR

Table 4. Pin descriptionDDD…continued RA RA Symbol Pin Ball Type Description FTFDTDP1[16]/ 180[1] D10[1] I/O P1[16] — General purpose digital input/output pin. RA RA ENET_MDC FO ENET_MDC — Ethernet MIIM clock. T DR P1[17]/ 178[1] A9[1] I/O P1[17] — General purpose digital input/output pin. AF ENET_MDIO TI/O ENET_MDIO — Ethernet MIIM data input and output. P1[18]/ 66[1] P7[1] I/O P1[18] — General purpose digital input/output pin. USB_UP_LED1/ O USB_UP_LED1 — USB port 1 GoodLink LED indicator. It is LOW when PWM1[1]/CAP1[0] device is configured (non-control endpoints enabled). It is HIGH when the device is not configured or during global suspend. O PWM1[1] — Pulse Width Modulator 1, channel 1 output. I CAP1[0] — Capture input for Timer 1, channel 0. P1[19]/ 68[1] U6[1] I/O P1[19] — General purpose digital input/output pin. USB_TX_E1/ O USB_TX_E1 — Transmit Enable signal for USB port 1 (OTG USB_PPWR1/ transceiver). CAP1[1] O USB_PPWR1 — Port Power enable signal for USB port 1. I CAP1[1] — Capture input for Timer 1, channel 1. P1[20]/ 70[1] U7[1] I/O P1[20] — General purpose digital input/output pin. USB_TX_DP1/ O USB_TX_DP1 — D+ transmit data for USB port 1 (OTG transceiver).[7] LCDVD[6]/ LCDVD[10]/ O LCDVD[6]/LCDVD[10] — LCD data.[7] PWM1[2]/SCK0 O PWM1[2] — Pulse Width Modulator 1, channel 2 output. I/O SCK0 — Serial clock for SSP0. P1[21]/ 72[1] R8[1] I/O P1[21] — General purpose digital input/output pin. USB_TX_DM1/ O USB_TX_DM1 — D− transmit data for USB port 1 (OTG transceiver).[7] LCDVD[7]/ LCDVD[11]/ O LCDVD[7]/LCDVD[11] — LCD data.[7] PWM1[3]/SSEL0 O PWM1[3] — Pulse Width Modulator 1, channel 3 output. I/O SSEL0 — Slave Select for SSP0. P1[22]/USB_RCV1/ 74[1] U8[1] I/O P1[22] — General purpose digital input/output pin. LCDVD[8]/ I USB_RCV1 — Differential receive data for USB port 1 (OTG LCDVD[12]/ transceiver).[7] USB_PWRD1/ MAT1[0] O LCDVD[8]/LCDVD[12] — LCD data.[7] I USB_PWRD1 — Power Status for USB port 1 (host power switch). O MAT1[0] — Match output for Timer 1, channel 0. P1[23]/ 76[1] P9[1] I/O P1[23] — General purpose digital input/output pin. USB_RX_DP1/ I USB_RX_DP1 — D+ receive data for USB port 1 (OTG transceiver).[7] LCDVD[9]/ LCDVD[13]/ [7] O LCDVD[9]/LCDVD[13] — LCD data. PWM1[4]/MISO0 O PWM1[4] — Pulse Width Modulator 1, channel 4 output. I/O MISO0 — Master In Slave Out for SSP0. P1[24]/ 78[1] T9[1] I/O P1[24] — General purpose digital input/output pin. USB_RX_DM1/ I USB_RX_DM1 — D− receive data for USB port 1 (OTG transceiver).[7] LCDVD[10]/ LCDVD[14]/ O LCDVD[10]/LCDVD[14] — LCD data.[7] PWM1[5]/MOSI0 O PWM1[5] — Pulse Width Modulator 1, channel 5 output. I/O MOSI0 — Master Out Slave in for SSP0. Preliminary data sheet Rev. 01.01 — 24 September 2009 14 of 83,

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Table 4. Pin descriptionDDD…continued RA RA Symbol Pin Ball Type Description FTFDTDP1[25]/USB_LS1/ 80[1] T10[1] I/O P1[25] — General purpose digital input/output pin. RA RA LCDVD[11]/ FO USB_LS1 — Low Speed status for USB port 1 (OTG transceiver).[7] T LCDVD[15]/ D R USB_HSTEN1/ O LCDVD[11]/LCDVD[15] — LCD data.[7]

AFT

MAT1[1] O USB_HSTEN1 — Host Enabled status for USB port 1. O MAT1[1] — Match output for Timer 1, channel 1. P1[26]/ 82[1] R10[1] I/O P1[26] — General purpose digital input/output pin. USB_SSPND1/ O USB_SSPND1 — USB port 1 Bus Suspend status (OTG transceiver).[7] LCDVD[12]/ LCDVD[20]/ O LCDVD[12]/LCDVD[20] — LCD data.[7] PWM1[6]/CAP0[0] O PWM1[6] — Pulse Width Modulator 1, channel 6 output. I CAP0[0] — Capture input for Timer 0, channel 0. P1[27]/USB_INT1/ 88[1] T12[1] I/O P1[27] — General purpose digital input/output pin. LCDVD[13]/ I USB_INT1 — USB port 1 OTG transceiver interrupt (OTG transceiver).[7] LCDVD[21]/ USB_OVRCR1/ O LCDVD[13]/LCDVD[21] — LCD data.[7] CAP0[1] I USB_OVRCR1 — USB port 1 Over-Current status. I CAP0[1] — Capture input for Timer 0, channel 1. P1[28]/USB_SCL1/ 90[1] T13[1] I/O P1[28] — General purpose digital input/output pin. LCDVD[14]/ I/O USB_SCL1 — USB port 1 I2C serial clock (OTG transceiver).[7] LCDVD[22]/ PCAP1[0]/MAT0[0] O LCDVD[14]/LCDVD[22] — LCD data.[7] I PCAP1[0] — Capture input for PWM1, channel 0. O MAT0[0] — Match output for Timer 0, channel 0. P1[29]/USB_SDA1/ 92[1] U14[1] I/O P1[29] — General purpose digital input/output pin. LCDVD[15]/ I/O USB_SDA1 — USB port 1 I2C serial data (OTG transceiver).[7] LCDVD[23]/ PCAP1[1]/MAT0[1] O LCDVD[15]/LCDVD[23] — LCD data.[7] I PCAP1[1] — Capture input for PWM1, channel 1. O MAT0[1] — Match output for Timer 0, channel 0. P1[30]/ 42[3] P2[3] I/O P1[30] — General purpose digital input/output pin. USB_PWRD2/ I USB_PWRD2 — Power Status for USB port 2. VBUS/AD0[4] I VBUS — Monitors the presence of USB bus power. Note: This signal must be HIGH for USB reset to occur. I AD0[4] — A/D converter 0, input 4. P1[31]/ 40[3] P1[3] I/O P1[31] — General purpose digital input/output pin. USB_OVRCR2/ I USB_OVRCR2 — Over-Current status for USB port 2. SCK1/AD0[5] I/O SCK1 — Serial Clock for SSP1. I AD0[5] — A/D converter 0, input 5. P2[0] to P2[31] I/O Port 2: Port 2 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 2 pins depends upon the pin function selected via the pin connect block. Preliminary data sheet Rev. 01.01 — 24 September 2009 15 of 83,

DR T

Table 4. Pin descriptionDTDTD…continued RA RA Symbol Pin Ball Type Description FTFDTDP2[0]/PWM1[1]/ 154[1] B17[1] I/O P2[0] — General purpose digital input/output pin. RA RA TXD1/TRACECLK/ FO PWM1[1] — Pulse Width Modulator 1, channel 1 output. T LCDPWR DR O TXD1 — Transmitter output for UART1. AFT O TRACECLK — Trace clock.[8] O LCDPWR — LCD panel power enable.[8] P2[1]/PWM1[2]/ 152[1] E14[1] I/O P2[1] — General purpose digital input/output pin. RXD1/PIPESTAT0/ O PWM1[2] — Pulse Width Modulator 1, channel 2 output.

LCDLE

I RXD1 — Receiver input for UART1. O PIPESTAT0 — Pipeline status, bit 0.[8] O LCDLE — Line end signal.[8] P2[2]/PWM1[3]/ 150[1] D15[1] I/O P2[2] — General purpose digital input/output pin. CTS1/PIPESTAT1/ O PWM1[3] — Pulse Width Modulator 1, channel 3 output.

LCDDCLK

I CTS1 — Clear to Send input for UART1. O PIPESTAT1 — Pipeline status, bit 1.[8] O LCDDCLK — LCD panel clock.[8] P2[3]/PWM1[4]/ 144[1] E16[1] I/O P2[3] — General purpose digital input/output pin. DCD1/PIPESTAT2/ O PWM1[4] — Pulse Width Modulator 1, channel 4 output.

LCDFP

I DCD1 — Data Carrier Detect input for UART1. O PIPESTAT2 — Pipeline status, bit 2.[8] O LCDFP — Frame pulse (STN). Vertical synchronization pulse (TFT).[8] P2[4]/PWM1[5]/ 142[1] D17[1] I/O P2[4] — General purpose digital input/output pin. DSR1/ O PWM1[5] — Pulse Width Modulator 1, channel 5 output. TRACESYNC/ LCDENAB/LCDM I DSR1 — Data Set Ready input for UART1. O TRACESYNC — Trace Synchronization.[8] O LCDENAB/LCDM — STN AC bias drive or TFT data enable output.[8] P2[5]/PWM1[6]/ 140[1] F16[1] I/O P2[5] — General purpose digital input/output pin. DTR1/ O PWM1[6] — Pulse Width Modulator 1, channel 6 output. TRACEPKT0/ LCDLP O DTR1 — Data Terminal Ready output for UART1. O TRACEPKT0 — Trace Packet, bit 0.[8] O LCDLP — Line synchronization pulse (STN). Horizontal synchronization pulse (TFT).[8] P2[6]/PCAP1[0]/ 138[1] E17[1] I/O P2[6] — General purpose digital input/output pin. RI1/ I PCAP1[0] — Capture input for PWM1, channel 0. TRACEPKT1/ LCDVD[0]/ I RI1 — Ring Indicator input for UART1. LCDVD[4] O TRACEPKT1 — Trace Packet, bit 1.[8] O LCDVD[0]/LCDVD[4] — LCD data.[8] P2[7]/RD2/ 136[1] G16[1] I/O P2[7] — General purpose digital input/output pin. RTS1/ I RD2 — CAN2 receiver input. TRACEPKT2/ LCDVD[1]/ O RTS1 — Request to Send output for UART1. LCDVD[5] O TRACEPKT2 — Trace Packet, bit 2.[8] O LCDVD[1]/LCDVD[5] — LCD data.[8] Preliminary data sheet Rev. 01.01 — 24 September 2009 16 of 83,

DR

Table 4. Pin description DR DR D …continuedAASymbol Pin Ball Type Description FTFDTDP2[8]/TD2/TXD2/ 134[1] H15[1] I/O P2[8] — General purpose digital input/output pin. RA RA TRACEPKT3/ FO TD2 — CAN2 transmitter output. T LCDVD[2]/ D R LCDVD[6] O TXD2 — Transmitter output for UART2.

AFT

O TRACEPKT3 — Trace packet, bit 3.[8] O LCDVD[2]/LCDVD[6] — LCD data.[8] P2[9]/ 132[1] H16[1] I/O P2[9] — General purpose digital input/output pin. USB_CONNECT1/ O USB_CONNECT1 — USB1 SoftConnect control. Signal used to switch RXD2/EXTIN0/ an external 1.5 kΩ resistor under the software control. Used with the LCDVD[3]/ SoftConnect USB feature. LCDVD[7] I RXD2 — Receiver input for UART2. I EXTIN0 — External Trigger Input.[8] I LCDVD[3]/LCDVD[7] — LCD data.[8] P2[10]/EINT0 110[9] N15[9] I/O P2[10] — General purpose digital input/output pin. Note: LOW on this pin while RESET is LOW forces on-chip bootloader to take over control of the part after a reset. I EINT0 — External interrupt 0 input. P2[11]/EINT1/ 108[9] T17[9] I/O P2[11] — General purpose digital input/output pin. LCDCLKIN/ I EINT1 — External interrupt 1 input.[10] MCIDAT1/ I2STX_CLK O LCDCLKIN — LCD clock.[10] I/O MCIDAT1 — Data line 1 for SD/MMC interface. I/O I2STX_CLK — Transmit Clock. It is driven by the master and received by the slave. Corresponds to the signal SCK in the I2S-bus specification. P2[12]/EINT2/ 106[9] N14[9] I/O P2[12] — General purpose digital input/output pin. LCDVD[4]/ I EINT2 — External interrupt 2 input.[10] LCDVD[3]/ LCDVD[8]/ O LCDVD[4]/LCDVD[3]/LCDVD[8]/LCDVD[18] — LCD data.[10] LCDVD[18]/ I/O MCIDAT2 — Data line 2 for SD/MMC interface. MCIDAT2/ I/O I2STX_WS — Transmit Word Select. It is driven by the master and I2STX_WS received by the slave. Corresponds to the signal WS in the I2S-bus specification. P2[13]/EINT3/ 102[9] T16[9] I/O P2[13] — General purpose digital input/output pin. LCDVD[5]/ I EINT3 — External interrupt 3 input.[10] LCDVD[9]/ LCDVD[19]/ O LCDVD[5]/LCDVD[9]/LCDVD[19] — LCD data.[10] MCIDAT3/ I/O MCIDAT3 — Data line 3 for SD/MMC interface. I2STX_SDA I/O I2STX_SDA — Transmit data. It is driven by the transmitter and read by the receiver. Corresponds to the signal SD in the I2S-bus specification. P2[14]/CS2/ 91[9] R12[9] I/O P2[14] — General purpose digital input/output pin. CAP2[0]/SDA1 O CS2 — LOW active Chip Select 2 signal. I CAP2[0] — Capture input for Timer 2, channel 0. I/O SDA1 — I2C1 data input/output (this is not an open-drain pin). P2[15]/CS3/ 99[9] P13[9] I/O P2[15] — General purpose digital input/output pin. CAP2[1]/SCL1 O CS3 — LOW active Chip Select 3 signal. I CAP2[1] — Capture input for Timer 2, channel 1. I/O SCL1 — I2C1 clock input/output (this is not an open-drain pin). Preliminary data sheet Rev. 01.01 — 24 September 2009 17 of 83,

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Table 4. Pin descriptionDDD…continued RA RA Symbol Pin Ball Type Description FTFDTDP2[16]/CAS 87[1] R11[1] I/O P2[16] — General purpose digital input/output pin. RA RFAOCAS — LOW active SDRAM Column Address Strobe. T DR P2[17]/RAS 95[1] R13[1] I/O P2[17] — General purpose digital input/output pin. AFT O RAS — LOW active SDRAM Row Address Strobe. P2[18]/ 59[1] U3[1] I/O P2[18] — General purpose digital input/output pin. CLKOUT0 O CLKOUT0 — SDRAM clock 0. P2[19]/ 67[1] R7[1] I/O P2[19] — General purpose digital input/output pin. CLKOUT1 O CLKOUT1 — SDRAM clock 1. P2[20]/DYCS0 73[1] T8[1] I/O P2[20] — General purpose digital input/output pin. O DYCS0 — SDRAM chip select 0. P2[21]/DYCS1 81[1] U11[1] I/O P2[21] — General purpose digital input/output pin. O DYCS1 — SDRAM chip select 1. P2[22]/DYCS2/ 85[1] U12[1] I/O P2[22] — General purpose digital input/output pin. CAP3[0]/SCK0 O DYCS2 — SDRAM chip select 2. I CAP3[0] — Capture input for Timer 3, channel 0. I/O SCK0 — Serial clock for SSP0. P2[23]/DYCS3/ 64[1] U5[1] I/O P2[23] — General purpose digital input/output pin. CAP3[1]/SSEL0 O DYCS3 — SDRAM chip select 3. I CAP3[1] — Capture input for Timer 3, channel 1. I/O SSEL0 — Slave Select for SSP0. P2[24]/ 53[1] P5[1] I/O P2[24] — General purpose digital input/output pin. CKEOUT0 O CKEOUT0 — SDRAM clock enable 0. P2[25]/ 54[1] R4[1] I/O P2[25] — General purpose digital input/output pin. CKEOUT1 O CKEOUT1 — SDRAM clock enable 1. P2[26]/ 57[1] T4[1] I/O P2[26] — General purpose digital input/output pin. CKEOUT2/ O CKEOUT2 — SDRAM clock enable 2. MAT3[0]/MISO0 O MAT3[0] — Match output for Timer 3, channel 0. I/O MISO0 — Master In Slave Out for SSP0. P2[27]/ 47[1] P3[1] I/O P2[27] — General purpose digital input/output pin. CKEOUT3/ O CKEOUT3 — SDRAM clock enable 3. MAT3[1]/MOSI0 O MAT3[1] — Match output for Timer 3, channel 1. I/O MOSI0 — Master Out Slave In for SSP0. P2[28]/ 49[1] P4[1] I/O P2[28] — General purpose digital input/output pin. DQMOUT0 O DQMOUT0 — Data mask 0 used with SDRAM and static devices. P2[29]/ 43[1] N3[1] I/O P2[29] — General purpose digital input/output pin. DQMOUT1 O DQMOUT1 — Data mask 1 used with SDRAM and static devices. P2[30]/ 31[1] L4[1] I/O P2[30] — General purpose digital input/output pin. DQMOUT2/ O DQMOUT2 — Data mask 2 used with SDRAM and static devices. MAT3[2]/SDA2 O MAT3[2] — Match output for Timer 3, channel 2. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). Preliminary data sheet Rev. 01.01 — 24 September 2009 18 of 83,

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Table 4. Pin descriptionDDD…continued RA RA Symbol Pin Ball Type Description FTFDTDP2[31]/ 39[1] N2[1] I/O P2[31] — General purpose digital input/output pin. RA RA DQMOUT3/ FO DQMOUT3 — Data mask 3 used with SDRAM and static devices. T MAT3[3]/SCL2 DR O MAT3[3] — Match output for Timer 3, channel 3. AFT I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). P3[0] to P3[31] I/O Port 3: Port 3 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. P3[0]/D0 197[1] B4[1] I/O P3[0] — General purpose digital input/output pin. I/O D0 — External memory data line 0. P3[1]/D1 201[1] B3[1] I/O P3[1] — General purpose digital input/output pin. I/O D1 — External memory data line 1. P3[2]/D2 207[1] B1[1] I/O P3[2] — General purpose digital input/output pin. I/O D2 — External memory data line 2. P3[3]/D3 3[1] E4[1] I/O P3[3] — General purpose digital input/output pin. I/O D3 — External memory data line 3. P3[4]/D4 13[1] F2[1] I/O P3[4] — General purpose digital input/output pin. I/O D4 — External memory data line 4. P3[5]/D5 17[1] G1[1] I/O P3[5] — General purpose digital input/output pin. I/O D5 — External memory data line 5. P3[6]/D6 23[1] J1[1] I/O P3[6] — General purpose digital input/output pin. I/O D6 — External memory data line 6. P3[7]/D7 27[1] L1[1] I/O P3[7] — General purpose digital input/output pin. I/O D7 — External memory data line 7. P3[8]/D8 191[1] D8[1] I/O P3[8] — General purpose digital input/output pin. I/O D8 — External memory data line 8. P3[9]/D9 199[1] C5[1] I/O P3[9] — General purpose digital input/output pin. I/O D9 — External memory data line 9. P3[10]/D10 205[1] B2[1] I/O P3[10] — General purpose digital input/output pin. I/O D10 — External memory data line 10. P3[11]/D11 208[1] D5[1] I/O P3[11] — General purpose digital input/output pin. I/O D11 — External memory data line 11. P3[12]/D12 1[1] D4[1] I/O P3[12] — General purpose digital input/output pin. I/O D12 — External memory data line 12. P3[13]/D13 7[1] C1[1] I/O P3[13] — General purpose digital input/output pin. I/O D13 — External memory data line 13. P3[14]/D14 21[1] H2[1] I/O P3[14] — General purpose digital input/output pin. I/O D14 — External memory data line 14. On POR, this pin serves as the BOOT0 pin. Preliminary data sheet Rev. 01.01 — 24 September 2009 19 of 83,

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Table 4. Pin descriptionDDD…continued RA RA Symbol Pin Ball Type Description FTFDTDP3[15]/D15 28[1] M1[1] I/O P3[15] — General purpose digital input/output pin. RA RF A I/O D15 — External memory data line 15. On POR, this pin serves as theT D BOOT1 pin. RAF BOOT[1:0] = 00 selects 8-bit external memory on CS1. T BOOT[1:0] = 01 is reserved. Do not use. BOOT[1:0] = 10 selects 32-bit external memory on CS1. BOOT[1:0] = 11 selects 16-bit external memory on CS1. P3[16]/D16/ 137[1] F17[1] I/O P3[16] — General purpose digital input/output pin. PWM0[1]/TXD1 I/O D16 — External memory data line 16. O PWM0[1] — Pulse Width Modulator 0, output 1. O TXD1 — Transmitter output for UART1. P3[17]/D17/ 143[1] F15[1] I/O P3[17] — General purpose digital input/output pin. PWM0[2]/RXD1 I/O D17 — External memory data line 17. O PWM0[2] — Pulse Width Modulator 0, output 2. I RXD1 — Receiver input for UART1. P3[18]/D18/ 151[1] C15[1] I/O P3[18] — General purpose digital input/output pin. PWM0[3]/CTS1 I/O D18 — External memory data line 18. O PWM0[3] — Pulse Width Modulator 0, output 3. I CTS1 — Clear to Send input for UART1. P3[19]/D19/ 161[1] B14[1] I/O P3[19] — General purpose digital input/output pin. PWM0[4]/DCD1 I/O D19 — External memory data line 19. O PWM0[4] — Pulse Width Modulator 0, output 4. I DCD1 — Data Carrier Detect input for UART1. P3[20]/D20/ 167[1] A13[1] I/O P3[20] — General purpose digital input/output pin. PWM0[5]/DSR1 I/O D20 — External memory data line 20. O PWM0[5] — Pulse Width Modulator 0, output 5. I DSR1 — Data Set Ready input for UART1. P3[21]/D21/ 175[1] C10[1] I/O P3[21] — General purpose digital input/output pin. PWM0[6]/DTR1 I/O D21 — External memory data line 21. O PWM0[6] — Pulse Width Modulator 0, output 6. O DTR1 — Data Terminal Ready output for UART1. P3[22]/D22/ 195[1] C6[1] I/O P3[22] — General purpose digital input/output pin. PCAP0[0]/RI1 I/O D22 — External memory data line 22. I PCAP0[0] — Capture input for PWM0, channel 0. I RI1 — Ring Indicator input for UART1. P3[23]/D23/ 65[1] T6[1] I/O P3[23] — General purpose digital input/output pin. CAP0[0]/ I/O D23 — External memory data line 23. PCAP1[0] I CAP0[0] — Capture input for Timer 0, channel 0. I PCAP1[0] — Capture input for PWM1, channel 0. Preliminary data sheet Rev. 01.01 — 24 September 2009 20 of 83,

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Table 4. Pin descriptionDDD…continued RA RA Symbol Pin Ball Type Description FTFDTDP3[24]/D24/ 58[1] R5[1] I/O P3[24] — General purpose digital input/output pin. RA RA CAP0[1]/ FI/O D24 — External memory data line 24. T PWM1[1] DR I CAP0[1] — Capture input for Timer 0, channel 1. AFT O PWM1[1] — Pulse Width Modulator 1, output 1. P3[25]/D25/ 56[1] U2[1] I/O P3[25] — General purpose digital input/output pin. MAT0[0]/ I/O D25 — External memory data line 25. PWM1[2] O MAT0[0] — Match output for Timer 0, channel 0. O PWM1[2] — Pulse Width Modulator 1, output 2. P3[26]/D26/ 55[1] T3[1] I/O P3[26] — General purpose digital input/output pin. MAT0[1]/ I/O D26 — External memory data line 26. PWM1[3] O MAT0[1] — Match output for Timer 0, channel 1. O PWM1[3] — Pulse Width Modulator 1, output 3. P3[27]/D27/ 203[1] A1[1] I/O P3[27] — General purpose digital input/output pin. CAP1[0]/ I/O D27 — External memory data line 27. PWM1[4] I CAP1[0] — Capture input for Timer 1, channel 0. O PWM1[4] — Pulse Width Modulator 1, output 4. P3[28]/D28/ 5[1] D2[1] I/O P3[28] — General purpose digital input/output pin. CAP1[1]/ I/O D28 — External memory data line 28. PWM1[5] I CAP1[1] — Capture input for Timer 1, channel 1. O PWM1[5] — Pulse Width Modulator 1, output 5. P3[29]/D29/ 11[1] F3[1] I/O P3[29] — General purpose digital input/output pin. MAT1[0]/ I/O D29 — External memory data line 29. PWM1[6] O MAT1[0] — Match output for Timer 1, channel 0. O PWM1[6] — Pulse Width Modulator 1, output 6. P3[30]/D30/ 19[1] H3[1] I/O P3[30] — General purpose digital input/output pin. MAT1[1]/ I/O D30 — External memory data line 30. RTS1 O MAT1[1] — Match output for Timer 1, channel 1. O RTS1 — Request to Send output for UART1. P3[31]/D31/ 25[1] J3[1] I/O P3[31] — General purpose digital input/output pin. MAT1[2] I/O D31 — External memory data line 31. O MAT1[2] — Match output for Timer 1, channel 2. P4[0] to P4[31] I/O Port 4: Port 4 is a 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. P4[0]/A0 75[1] U9[1] I/O P4[0] — ]General purpose digital input/output pin. I/O A0 — External memory address line 0. P4[1]/A1 79[1] U10[1] I/O P4[1] — General purpose digital input/output pin. I/O A1 — External memory address line 1. P4[2]/A2 83[1] T11[1] I/O P4[2] — General purpose digital input/output pin. I/O A2 — External memory address line 2. Preliminary data sheet Rev. 01.01 — 24 September 2009 21 of 83,

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Table 4. Pin descriptionDDD…continued RA RA Symbol Pin Ball Type Description FTFDTDP4[3]/A3 97[1] U16[1] I/O P4[3] — General purpose digital input/output pin. RA RF A I/O A3 — External memory address line 3. T DR P4[4]/A4 103[1] R15[1] I/O P4[4] — General purpose digital input/output pin. AFT I/O A4 — External memory address line 4. P4[5]/A5 107[1] R16[1] I/O P4[5] — General purpose digital input/output pin. I/O A5 — External memory address line 5. P4[6]/A6 113[1] M14[1] I/O P4[6] — General purpose digital input/output pin. I/O A6 — External memory address line 6. P4[7]/A7 121[1] L16[1] I/O P4[7] — General purpose digital input/output pin. I/O A7 — External memory address line 7. P4[8]/A8 127[1] J17[1] I/O P4[8] — General purpose digital input/output pin. I/O A8 — External memory address line 8. P4[9]/A9 131[1] H17[1] I/O P4[9] — General purpose digital input/output pin. I/O A9 — External memory address line 9. P4[10]/A10 135[1] G17[1] I/O P4[10] — General purpose digital input/output pin. I/O A10 — External memory address line 10. P4[11]/A11 145[1] F14[1] I/O P4[11] — General purpose digital input/output pin. I/O A11 — External memory address line 11. P4[12]/A12 149[1] C16[1] I/O P4[12] — General purpose digital input/output pin. I/O A12 — External memory address line 12. P4[13]/A13 155[1] B16[1] I/O P4[13] — General purpose digital input/output pin. I/O A13 — External memory address line 13. P4[14]/A14 159[1] B15[1] I/O P4[14] — General purpose digital input/output pin. I/O A14 — External memory address line 14. P4[15]/A15 173[1] A11[1] I/O P4[15] — General purpose digital input/output pin. I/O A15 — External memory address line 15. P4[16]/A16 101[1] U17[1] I/O P4[16] — General purpose digital input/output pin. I/O A16 — External memory address line 16. P4[17]/A17 104[1] P14[1] I/O P4[17] — General purpose digital input/output pin. I/O A17 — External memory address line 17. P4[18]/A18 105[1] P15[1] I/O P4[18] — General purpose digital input/output pin. I/O A18 — External memory address line 18. P4[19]/A19 111[1] P16[1] I/O P4[19] — General purpose digital input/output pin. I/O A19 — External memory address line 19. P4[20]/A20/ 109[1] R17[1] I/O P4[20] — General purpose digital input/output pin. SDA2/SCK1 I/O A20 — External memory address line 20. I/O SDA2 — I2C2 data input/output (this is not an open-drain pin). I/O SCK1 — Serial Clock for SSP1. Preliminary data sheet Rev. 01.01 — 24 September 2009 22 of 83,

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Table 4. Pin descriptionDDD…continued RA RA Symbol Pin Ball Type Description FTFDTDP4[21]/A21/ 115[1] M15[1] I/O P4[21] — General purpose digital input/output pin. RA RA SCL2/SSEL1 FI/O A21 — External memory address line 21. T DR I/O SCL2 — I2C2 clock input/output (this is not an open-drain pin). AFT I/O SSEL1 — Slave Select for SSP1. P4[22]/A22/ 123[1] K14[1] I/O P4[22] — General purpose digital input/output pin. TXD2/MISO1 I/O A22 — External memory address line 22. O TXD2 — Transmitter output for UART2. I/O MISO1 — Master In Slave Out for SSP1. P4[23]/A23/ 129[1] J15[1] I/O P4[23] — General purpose digital input/output pin. RXD2/MOSI1 I/O A23 — External memory address line 23. I RXD2 — Receiver input for UART2. I/O MOSI1 — Master Out Slave In for SSP1. P4[24]/OE 183[1] B8[1] I/O P4[24] — General purpose digital input/output pin. O OE — LOW active Output Enable signal. P4[25]/WE 179[1] B9[1] I/O P4[25] — General purpose digital input/output pin. O WE — LOW active Write Enable signal. P4[26]/BLS0 119[1] L15[1] I/O P4[26] — General purpose digital input/output pin. O BLS0 — LOW active Byte Lane select signal 0. P4[27]/BLS1 139[1] G15[1] I/O P4[27] — General purpose digital input/output pin. O BLS1 — LOW active Byte Lane select signal 1. P4[28]/BLS2/ 170[1] C11[1] I/O P4 [28] — General purpose digital input/output pin. MAT2[0]/LCDVD[6]/ O BLS2 — LOW active Byte Lane select signal 2. LCDVD[10]/ LCDVD[2]/ O MAT2[0] — Match output for Timer 2, channel 0.[11] TXD3 O LCDVD[6]/LCDVD[10]/LCDVD[2] — LCD data.[11] O TXD3 — Transmitter output for UART3. P4[29]/BLS3/ 176[1] B10[1] I/O P4[29] — General purpose digital input/output pin. MAT2[1] O BLS3 — LOW active Byte Lane select signal 3. LCDVD[7]/ LCDVD[11]/ O MAT2[1] — Match output for Timer 2, channel 1.[11] LCDVD[3]/RXD3 O LCDVD[7]/LCDVD[11]/LCDVD[3] — LCD data.[11] I RXD3 — Receiver input for UART3. P4[30]/CS0 187[1] B7[1] I/O P4[30] — General purpose digital input/output pin. O CS0 — LOW active Chip Select 0 signal. P4[31]/CS1 193[1] A4[1] I/O P4[31] — General purpose digital input/output pin. O CS1 — LOW active Chip Select 1 signal. ALARM 37[13] N1[13] O ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC alarm is generated. USB_D−2 52 U1 I/O USB_D−2 — USB port 2 bidirectional D− line. DBGEN 9[1] F4[1] I DBGEN — JTAG interface control signal. Also used for boundary scanning. TDO 2[1] D3[1] O TDO — Test Data Out for JTAG interface. TDI 4[1] C2[1] I TDI — Test Data In for JTAG interface. Preliminary data sheet Rev. 01.01 — 24 September 2009 23 of 83,

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Table 4. Pin descriptionDDD…continued RA RA Symbol Pin Ball Type Description FTFDTDTMS 6[1] E3[1] I TMS — Test Mode Select for JTAG interface. RA RF A TRST 8[1] D1[1] I TRST — Test Reset for JTAG interface. T DR TCK 10[1] E2[1] I TCK — Test Clock for JTAG interface. This clock must be slower than 1⁄ A6 F of the CPU clock (CCLK) for the JTAG interface to operate. T RTCK 206[1] C3[1] I/O RTCK — JTAG interface control signal. Note: LOW on this pin while RESET is LOW enables ETM pins (P2[9:0]) to operate as Trace port after reset. RSTOUT 29 K3 O RSTOUT — This is a 3.3 V pin. LOW on this pin indicates LPC2470 being in Reset state. RESET 35[12] M2[12] I external reset input: A LOW on this pin resets the device, causing I/O ports and peripherals to take on their default states, and processor execution to begin at address 0. TTL with hysteresis, 5 V tolerant. XTAL1 44[13] M4[13] I Input to the oscillator circuit and internal clock generator circuits. XTAL2 46[13] N4[13] O Output from the oscillator amplifier. RTCX1 34[13] K2[13] I Input to the RTC oscillator circuit. RTCX2 36[13] L2[13] O Output from the RTC oscillator circuit. VSSIO 33, 63, L3, T5, I ground: 0 V reference for the digital IO pins. 77, 93, R9, P12, 114, N16, 133, H14, 148, E15, 169, A12, B6, 189, A2[13] 200[13] VSSCORE 32, 84, K4, P10, I ground: 0 V reference for the core. 172[13] D12[13] VSSA 22[13] J2[13] I analog ground: 0 V reference. This should nominally be the same voltage as VSSIO/VSSCORE, but should be isolated to minimize noise and error. VDD(3V3) 15, 60, G3, P6, I 3.3 V supply voltage: This is the power supply voltage for the I/O ports. 71, 89, P8, U13, 112, P17, 125, K16, 146, C17, 165, B13, C9, 181, D7[13] 198[13] n.c. 30, 117, J4, L14, I not connected pins: These pins must be left unconnected (floating). 141[13] G14[13] VDD(DCDC)(3V3) 26, 86, H4, P11, I 3.3 V DC-to-DC converter supply voltage: This is the power supply for 174[13] D11[13] the on-chip DC-to-DC converter. VDDA 20[13] G4[13] I analog 3.3 V pad supply voltage: This should be nominally the same voltage as VDD(3V3) but should be isolated to minimize noise and error. This voltage is used to power the ADC and DAC. Preliminary data sheet Rev. 01.01 — 24 September 2009 24 of 83,

DR Table 4. Pin descriptionDDD…continued RA RA Symbol Pin Ball Type Description FTFDTD VREF 24[13] K1[13] I ADC reference: This should be nominally the same voltage asVRRDDA(3V3) A

but should be isolated to minimize noise and error. The level on this pFinT is used as a reference for ADC and DAC. DRA

VBAT 38[13] M3[13] I RTC power supply: 3.3 V on this pin supplies the power to the RTC FT

peripheral. [1] 5 V tolerant pad providing digital I/O functions with TTL levels and hysteresis. [2] Either the I2S function or the LCD function is selectable, see Table 14, Table 15, and Table 16. [3] 5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input. When configured as a ADC input, digital section of the pad is disabled. [4] 5 V tolerant pad providing digital I/O with TTL levels and hysteresis and analog output function. When configured as the DAC output, digital section of the pad is disabled. [5] Open-drain5Vtolerant digital I/O pad, compatible with I2C-bus 400 kHz specification. It requires an external pull-up to provide output functionality. When power is switched off, this pin connected to the I2C-bus is floating and does not disturb the I2C lines. Open-drain configuration applies to all functions on this pin. [6] Pad provides digital I/O and USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only). [7] Either the USB OTG function or the LCD function is selectable, see Table 14, Table 15, and Table 16. [8] Either the trace function or the LCD function is selectable, see Table 14, Table 15, and Table 16. [9] 5 V tolerant pad with 5 ns glitch filter providing digital I/O functions with TTL levels and hysteresis. [10] Either one of the external interrupts EINT1 to EINT3 or the LCD function is selectable, see Table 14, Table 15, and Table 16. [11] Either one of the timer outputs MAT2[1] and MAT2[0] or the LCD function is selectable, see Table 14, Table 15, and Table 16. [12] 5 V tolerant pad with 20 ns glitch filter providing digital I/O function with TTL levels and hysteresis. [13] Pad provides special analog functionality. Preliminary data sheet Rev. 01.01 — 24 September 2009 25 of 83,

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7. Functional description DR DR DAF ATFDTRDR 7.1 Architectural overview AF AT D The LPC2470 microcontroller consists of an ARM7TDMI-S CPU with emulation support,R A the ARM7 local bus for closely coupled, high-speed access to the majority of on-chip FT memory, the AMBA AHB interfacing to high-speed on-chip peripherals and external memory, and the AMBA APB for connection to other on-chip peripheral functions. The microcontroller permanently configures the ARM7TDMI-S processor for little-endian byte order. The LPC2470 implements two AHBs in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the VIC, GPDMA controller, and EMC. The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1. In summary, bus masters with access to AHB1 are the ARM7 itself, the GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus masters with access to AHB2 are the ARM7 and the Ethernet block. AHB peripherals are allocateda2MB range of addresses at the very top of the 4 GB ARM memory space. Each AHB peripheral is allocated a 16 kB address space within the AHB address space. Lower speed peripheral functions are connected to the APB. The AHB to APB bridge interfaces the APB to the AHB. APB peripherals are also allocateda2MB range of addresses, beginning at the 3.5 GB address point. Each APB peripheral is allocated a 16 kB address space within the APB address space. The ARM7TDMI-S processor is a general purpose 32-bit microprocessor, which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. This simplicity results in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. Pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. Typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. The ARM7TDMI-S processor also employs a unique architectural strategy known as Thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the ARM7TDMI-S processor has two instruction sets: • the standard 32-bit ARM set • a 16-bit Thumb set Preliminary data sheet Rev. 01.01 — 24 September 2009 26 of 83,

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TTDTThe Thumb set’s 16-bit instruction length allows it to approach higher densityD RcAompareRdA to

D

standard ARM code while retaining most of the ARM’s performance. FTFDTRDA RA 7.2 On-chip SRAM FT DR The LPC2470 includes a SRAM memory of 64 kB reserved for the ARM processor AF exclusive use. This RAM may be used for code and/or data storage and may be accessed T as 8 bits, 16 bits, and 32 bits. A 16 kB SRAM block serving as a buffer for the Ethernet controller and a 16 kB SRAM associated with the second AHB can be used both for data and code storage, too. The 2 kB RTC SRAM can be used for data storage only. The RTC SRAM is battery powered and retains the content in the absence of the main power supply. 7.3 Memory map The LPC2470 memory map incorporates several distinct regions as shown in Table 5 and Figure 4. In addition, the CPU interrupt vectors may be remapped to allow them to reside in either boot ROM or SRAM (see Section 7.26.6). Table 5. LPC2470 memory usage and details Address range General use Address range details and description 0x0000 0000 to Fast I/O 0x3FFF C000 - 0x3FFF FFFF Fast GPIO registers 0x3FFF FFFF 0x4000 0000 to On-chip RAM 0x4000 0000 - 0x4000 FFFF RAM (64 kB) 0x7FFF FFFF 0x7FE0 0000 - 0x7FE0 3FFF Ethernet RAM (16 kB) 0x7FD0 0000 - 0x7FD0 3FFF USB RAM (16 kB) 0x8000 0000 to Off-Chip Memory Four static memory banks, 16 MB each 0xDFFF FFFF 0x8000 0000 - 0x80FF FFFF Static memory bank 0 0x8100 0000 - 0x81FF FFFF Static memory bank 1 0x8200 0000 - 0x82FF FFFF Static memory bank 2 0x8300 0000 - 0x83FF FFFF Static memory bank 3 Four dynamic memory banks, 256 MB each 0xA000 0000 - 0xAFFF FFFF Dynamic memory bank 0 0xB000 0000 - 0xBFFF FFFF Dynamic memory bank 1 0xC000 0000 - 0xCFFF FFFF Dynamic memory bank 2 0xD000 0000 - 0xDFFF FFFF Dynamic memory bank 3 0xE000 0000 to APB Peripherals 36 peripheral blocks, 16 kB each 0xEFFF FFFF 0xF000 0000 to AHB peripherals 0xFFFF FFFF Preliminary data sheet Rev. 01.01 — 24 September 2009 27 of 83,

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TDTRD

T

A R

D

F AF 4.0 GB 0xFFFF FTF FDFTDAHB PERIPHERALS RA RA 3.75 GB 0xF000 0000 FT D APB PERIPHERALS RA 3.5 GB 0xE000 0000 FT EXTERNAL STATIC AND DYNAMIC MEMORY 2.0 GB 0x8000 0000 0x7FFF FFFF BOOT ROM RESERVED ADDRESS SPACE ON-CHIP STATIC RAM 1.0 GB 0x4000 0000 0x3FFF FFFF SPECIAL REGISTERS 0x3FFF 8000 RESERVED ADDRESS SPACE 0.0 GB 0x0000 0000 002aad316 Fig 4. LPC2470 memory map 7.4 Interrupt controller The ARM processor core has two interrupt inputs called Interrupt Request (IRQ) and Fast Interrupt Request (FIQ). The VIC takes 32 interrupt request inputs which can be programmed as FIQ or vectored IRQ types. The programmable assignment scheme means that priorities of interrupts from the various peripherals can be dynamically assigned and adjusted. FIQs have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ Preliminary data sheet Rev. 01.01 — 24 September 2009 28 of 83,

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TTDTservice routine can simply start dealing with that device. But if more than onDeR requestR is DA A assigned to the FIQ class, the FIQ service routine can read a word from the VICFT that

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identifies which FIQ source(s) is (are) requesting an interrupt. DR DA RF AT Vectored IRQs, which include all interrupt requests that are not classified as FIQs, have D aR programmable interrupt priority. When more than one interrupt is assigned the same AF priority and occur simultaneously, the one connected to the lowest numbered VIC channel T will be serviced first. The VIC ORs the requests from all of the vectored IRQs to produce the IRQ signal to the ARM processor. The IRQ service routine can start by reading a register from the VIC and jumping to the address supplied by that register. 7.4.1 Interrupt sources Each peripheral device has one interrupt line connected to the VIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on port 0 and port 2 (total of 64 pins) regardless of the selected function, can be programmed to generate an interrupt on a rising edge, a falling edge, or both. Such interrupt request coming from port 0 and/or port 2 will be combined with the EINT3 interrupt requests. 7.5 Pin connect block The pin connect block allows selected pins of the microcontroller to have more than one function. Configuration registers control the multiplexers to allow connection between the pin and the on chip peripherals. Peripherals should be connected to the appropriate pins prior to being activated and prior to any related interrupt(s) being enabled. Activity of any enabled peripheral function that is not mapped to a related pin should be considered undefined. 7.6 External memory controller The LPC2470 EMC is an ARM PrimeCell MultiPort Memory Controller peripheral offering support for asynchronous static memory devices such as RAM, ROM, and flash. In addition, it can be used as an interface with off-chip memory-mapped devices and peripherals. The EMC is an Advanced Microcontroller Bus Architecture (AMBA) compliant peripheral. 7.6.1 Features • Dynamic memory interface support including single data rate SDRAM. • Asynchronous static memory device support including RAM, ROM, and flash, with or without asynchronous page mode. • Low transaction latency. • Read and write buffers to reduce latency and to improve performance. • 8/16/32 data and 24 address lines wide static memory support. • 16 bit and 32 bit wide chip select SDRAM memory support. • Static memory features include: Preliminary data sheet Rev. 01.01 — 24 September 2009 29 of 83,

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T T – D

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Asynchronous page mode read DR DA RF AF – Programmable Wait StatesTDTRDR – Bus turnaround delay AF AT – Output enable and write enable delays DRA – Extended wait FT • Four chip selects for synchronous memory and four chip selects for static memory devices. • Power-saving modes dynamically control CKE and CLKOUT to SDRAMs. • Dynamic memory self-refresh mode controlled by software. • Controller supports 2048, 4096, and 8192 row address synchronous memory parts. That is typical 512 MB, 256 MB, and 128 MB parts, with 4, 8, 16, or 32 data bits per device. • Separate reset domains allow the for auto-refresh through a chip reset if desired. Note: Synchronous static memory devices (synchronous burst mode) are not supported. 7.7 General purpose DMA controller The GPDMA is an AMBA AHB compliant peripheral allowing selected LPC2470 peripherals to have DMA support. The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. Each DMA stream provides unidirectional serial DMA transfers for a single source and destination. For example, a bidirectional port requires one stream for transmit and one for receive. The source and destination areas can each be either a memory region or a peripheral, and can be accessed through the AHB master. 7.7.1 Features • Two DMA channels. Each channel can support a unidirectional transfer. • The GPDMA can transfer data between the 16 kB SRAM, external memory, and peripherals such as the SD/MMC, two SSPs, and the I2S interface. • Single DMA and burst DMA request signals. Each peripheral connected to the GPDMA can assert either a burst DMA request or a single DMA request. The DMA burst size is set by programming the GPDMA. • Memory-to-memory, memory-to-peripheral, peripheral-to-memory, and peripheral-to-peripheral transfers. • Scatter or gather DMA is supported through the use of linked lists. This means that the source and destination areas do not have to occupy contiguous areas of memory. • Hardware DMA channel priority. Each DMA channel has a specific hardware priority. DMA channel 0 has the highest priority and channel 1 has the lowest priority. If requests from two channels become active at the same time, the channel with the highest priority is serviced first. • AHB slave DMA programming interface. The GPDMA is programmed by writing to the DMA control registers over the AHB slave interface. Preliminary data sheet Rev. 01.01 — 24 September 2009 30 of 83,

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• D One AHB master for transferring data. This interface transfers data wheDnR Aa DMA R

D A

request goes active. FTFDTD• 32-bit AHB master bus width. RA RF A • Incrementing or non-incrementing addressing for source and destination. T DR • Programmable DMA burst size. The DMA burst size can be programmed to more AFT efficiently transfer data. Usually the burst size is set to half the size of the FIFO in the peripheral. • Internal four-word FIFO per channel. • Supports 8-bit, 16-bit, and 32-bit wide transactions. • An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Interrupt masking. The DMA error and DMA terminal count interrupt requests can be masked. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 7.8 Fast general purpose parallel I/O Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC2470 use accelerated GPIO functions: • GPIO registers are relocated to the ARM local bus so that the fastest possible I/O timing can be achieved. • Mask registers allow treating sets of port bits as a group, leaving other bits unchanged. • All GPIO registers are byte and half-word addressable. • Entire port value can be written in one instruction. Additionally, any pin on port 0 and port 2 (total of 64 pins) that is not configured as an analog input/output can be programmed to generate an interrupt on a rising edge, a falling edge, or both. The edge detection is asynchronous, so it may operate when clocks are not present such as during Power-down mode. Each enabled interrupt can be used to wake the chip up from Power-down mode. 7.8.1 Features • Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. • Direction control of individual bits. • All I/O default to inputs after reset. • Backward compatibility with other earlier devices is maintained with legacy port 0 and port 1 registers appearing at the original addresses on the APB. Preliminary data sheet Rev. 01.01 — 24 September 2009 31 of 83,

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7.9 LCD controllerDTTRDDA RF AF The LCD controller provides all of the necessary control signals to interface direTc tDlyR toaTDR variety of color and monochrome LCD panels. Both STN (single and dual panel) andA FTFT A panels can be operated. The display resolution is selectable and can be up to 1024 × 7T 6D8 pixels. Several color modes are provided, up to a 24-bit true-color non-palettized mode. RAF An on-chip 512-byte color palette allows reducing bus utilization (i.e. memory size of the T displayed data) while still supporting a large number of colors. The LCD interface includes its own DMA controller to allow it to operate independently of the CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time needed to operate the display. 7.9.1 Features • AHB bus master interface to access frame buffer. • Setup and control via a separate AHB slave interface. • Dual 16-deep programmable 64-bit wide FIFOs for buffering incoming display data. • Supports single and dual-panel monochrome Super Twisted Nematic (STN) displays with 4-bit or 8-bit interfaces. • Supports single and dual-panel color STN displays. • Supports Thin Film Transistor (TFT) color displays. • Programmable display resolution including, but not limited to: 320 × 200, 320 × 240, 640 × 200, 640 × 240, 640 × 480, 800 × 600, and 1024 × 768. • Hardware cursor support for single-panel displays. • 15 gray-level monochrome, 3375 color STN, and 32 K color palettized TFT support. • 1, 2, or 4 bits-per-pixel (bpp) palettized displays for monochrome STN. • 1, 2, 4, or 8 bpp palettized color displays for color STN and TFT. • 16 bpp true-color non-palettized, for color STN and TFT. • 24 bpp true-color non-palettized, for color TFT. • Programmable timing for different display panels. • 256 entry, 16-bit palette RAM, arranged as a 128 × 32-bit RAM. • Frame, line, and pixel clock signals. • AC bias signal for STN, data enable signal for TFT panels. • Supports little and big-endian, and Windows CE data formats. • LCD panel clock may be generated from the peripheral clock, or from a clock input pin. 7.10 Ethernet The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity. Automatic frame transmission and reception with scatter-gather DMA off-loads many operations from the CPU. Preliminary data sheet Rev. 01.01 — 24 September 2009 32 of 83,

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TTDTThe Ethernet block and the CPU share a dedicated AHB subsystem that is uDsReAd to accRe

D

Ass the Ethernet SRAM for Ethernet data, control, and status information. All other AFTH B traff FiTc in the LPC2470 takes place on a different AHB subsystem, effectively separating EDtRhAernet

DRA

activity from the rest of the system. The Ethernet DMA can also access off-chip memFoTry via the EMC, as well as the SRAM located on another AHB. However, using memory DRA other than the Ethernet SRAM, especially off-chip memory, will slow Ethernet access to FT memory and increase the loading of its AHB. The Ethernet block interfaces between an off-chip Ethernet PHY using the Media Independent Interface (MII) or Reduced MII (RMII) protocol and the on-chip Media Independent Interface Management (MIIM) serial bus. 7.10.1 Features • Ethernet standards support: – Supports 10 Mbit/s or 100 Mbit/s PHY devices including 10 Base-T, 100 Base-TX, 100 Base-FX, and 100 Base-T4. – Fully compliant with IEEE standard 802.3. – Fully compliant with 802.3x Full Duplex Flow Control and Half Duplex back pressure. – Flexible transmit and receive frame options. – Virtual Local Area Network (VLAN) frame support. • Memory management: – Independent transmit and receive buffers memory mapped to shared SRAM. – DMA managers with scatter/gather DMA and arrays of frame descriptors. – Memory traffic optimized by buffering and pre-fetching. • Enhanced Ethernet features: – Receive filtering. – Multicast and broadcast frame support for both transmit and receive. – Optional automatic Frame Check Sequence (FCS) insertion with Circular Redundancy Check (CRC) for transmit. – Selectable automatic transmit frame padding. – Over-length frame support for both transmit and receive allows any length frames. – Promiscuous receive mode. – Automatic collision back-off and frame retransmission. – Includes power management by clock switching. – Wake-on-LAN power management support allows system wake-up: using the receive filters or a magic frame detection filter. • Physical interface: – Attachment of external PHY chip through standard MII or RMII interface. – PHY register access is available via the MIIM interface. Preliminary data sheet Rev. 01.01 — 24 September 2009 33 of 83,

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7.11 USB interface DR D DA RF AF The Universal Serial Bus (USB) is a 4-wire bus that supports communication beTtw DeenaTRDR host and one or more (up to 127) peripherals. The host controller allocates the USBAFAbandwidth to attached devices through a token-based protocol. The bus supports hotTDplugging and dynamic configuration of the devices. All transactions are initiated by the RAF host controller. T The LPC2470 USB interface includes a device, host, and OTG controller. Details on typical USB interfacing solutions can be found in Section 11.2 “Suggested USB interface solutions” on page 70 7.11.1 USB device controller The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers. An interrupt is also generated if enabled. When enabled, the DMA controller transfers data between the endpoint buffer and the USB RAM. 7.11.1.1 Features • Fully compliant with USB 2.0 specification (full speed). • Supports 32 physical (16 logical) endpoints witha4kB endpoint buffer RAM. • Supports Control, Bulk, Interrupt and Isochronous endpoints. • Scalable realization of endpoints at run time. • Endpoint Maximum packet size selection (up to USB maximum specification) by software at run time. • Supports SoftConnect and GoodLink features. • While USB is in the Suspend mode, LPC2470 can enter one of the reduced power modes and wake up on USB activity. • Supports DMA transfers with the DMA RAM of 16 kB on all non-control endpoints. • Allows dynamic switching between CPU-controlled and DMA modes. • Double buffer implementation for Bulk and Isochronous endpoints. 7.11.2 USB host controller The host controller enables full- and low-speed data exchange with USB devices attached to the bus. It consists of register interface, serial interface engine and DMA controller. The register interface complies with the OHCI specification. 7.11.2.1 Features • OHCI compliant • Two downstream ports • Supports per-port power switching Preliminary data sheet Rev. 01.01 — 24 September 2009 34 of 83,

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7.11.3 USB OTG controller DR DR DAF AF USB OTG is a supplement to the USB 2.0 specification that augments the capabT iDlity ofTDexisting mobile devices and USB peripherals by adding host functionality for connecRtAion to RF A USB peripherals. T DRA The OTG controller integrates the host controller, device controller, and a master-only I2C FT interface to implement OTG dual-role device functionality. The dedicated I2C interface controls an external OTG transceiver. 7.11.3.1 Features • Fully compliant with On-The-Go supplement to the USB 2.0 Specification, Revision 1.0a. • Hardware support for Host Negotiation Protocol (HNP). • Includes a programmable timer required for HNP and Session Request Protocol (SRP). • Supports any OTG transceiver compliant with the OTG Transceiver Specification (CEA-2011), Rev. 1.0. 7.12 CAN controller and acceptance filters The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. Its domain of application ranges from high-speed networks to low cost multiplex wiring. The CAN block is intended to support multiple CAN buses simultaneously, allowing the device to be used as a gateway, switch, or router between two of CAN buses in industrial or automotive applications. Each CAN controller has a register structure similar to the NXP SJA1000 and the PeliCAN Library block, but the 8-bit registers of those devices have been combined in 32-bit words to allow simultaneous access in the ARM environment. The main operational difference is that the recognition of received Identifiers, known in CAN terminology as Acceptance Filtering, has been removed from the CAN controllers and centralized in a global Acceptance Filter. 7.12.1 Features • Two CAN controllers and buses. • Data rates to 1 Mbit/s on each bus. • 32-bit register and RAM access. • Compatible with CAN specification 2.0B, ISO 11898-1. • Global Acceptance Filter recognizes 11-bit and 29-bit receive identifiers for all CAN buses. • Acceptance Filter can provide FullCAN-style automatic reception for selected Standard Identifiers. • FullCAN messages can generate interrupts. Preliminary data sheet Rev. 01.01 — 24 September 2009 35 of 83,

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7.13 10-bit ADC DR DR DAF AF The LPC2470 contains one ADC. It is a single 10-bit successive approximation AT DRC with T DR eight channels. AF AT D 7.13.1 Features RAFT • 10-bit successive approximation ADC • Input multiplexing among 8 pins • Power-down mode • Measurement range0Vto Vi(VREF) • 10-bit conversion time ≥ 2.44 μs • Burst conversion mode for single or multiple inputs • Optional conversion on transition of input pin or Timer Match signal • Individual result registers for each ADC channel to reduce interrupt overhead 7.14 10-bit DAC The DAC allows the LPC2470 to generate a variable analog output. The maximum output value of the DAC is Vi(VREF). 7.14.1 Features • 10-bit DAC • Resistor string architecture • Buffered output • Power-down mode • Selectable output drive 7.15 UARTs The LPC2470 contains four UARTs. In addition to standard transmit and receive data lines, UART1 also provides a full modem control handshake interface. The UARTs include a fractional baud rate generator. Standard baud rates such as 115 200 Bd can be achieved with any crystal frequency above 2 MHz. 7.15.1 Features • 16 B Receive and Transmit FIFOs. • Register locations conform to 16C550 industry standard. • Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B. • Built-in fractional baud rate generator covering wide range of baud rates without a need for external crystals of particular values. • Fractional divider for baud rate control, auto baud capabilities and FIFO control mechanism that enables software flow control implementation. • UART1 equipped with standard modem interface signals. This module also provides full support for hardware flow control (auto-CTS/RTS). Preliminary data sheet Rev. 01.01 — 24 September 2009 36 of 83,

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T T • D

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UART3 includes an IrDA mode to support infrared communication. DR DA RF ATFDTD7.16 SPI serial I/O controller RA RF AT The LPC2470 contains one SPI controller. SPI is a full duplex serial interface designed DtoR handle multiple masters and slaves connected to a given bus. Only a single master and a AF single slave can communicate on the interface during a given data transfer. During a data T transfer the master always sends 8 bits to 16 bits of data to the slave, and the slave always sends 8 bits to 16 bits of data to the master. 7.16.1 Features • Compliant with SPI specification • Synchronous, Serial, Full Duplex Communication • Combined SPI master and slave • Maximum data bit rate of one eighth of the input clock rate • 8 bits to 16 bits per transfer 7.17 SSP serial I/O controller The LPC2470 contains two SSP controllers. The SSP controller is capable of operation on a SPI, 4-wire SSI, or Microwire bus. It can interact with multiple masters and slaves on the bus. Only a single master and a single slave can communicate on the bus during a given data transfer. The SSP supports full duplex transfers, with frames of 4 bits to 16 bits of data flowing from the master to the slave and from the slave to the master. In practice, often only one of these data flows carries meaningful data. 7.17.1 Features • Compatible with Motorola SPI, 4-wire TI SSI, and National Semiconductor Microwire buses • Synchronous serial communication • Master or slave operation • 8-frame FIFOs for both transmit and receive • 4-bit to 16-bit frame • Maximum SPI bus data bit rate of one half (Master mode) and one twelfth (Slave mode) of the input clock rate • DMA transfers supported by GPDMA 7.18 SD/MMC card interface The Secure Digital and Multimedia Card Interface (MCI) allows access to external SD memory cards. The SD card interface conforms to the SD Multimedia Card Specification Version 2.11. 7.18.1 Features • The MCI provides all functions specific to the SD/MMC memory card. These include the clock generation unit, power management control, and command and data transfer. Preliminary data sheet Rev. 01.01 — 24 September 2009 37 of 83,

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• D Conforms to Multimedia Card Specification v2.11. DR R DA A • F FConforms to Secure Digital Memory Card Physical Layer Specification, v0.9T6 D. T R DR• Can be used as a multimedia card bus or a secure digital memory card bus hostA.F The A SD/MMC can be connected to several multimedia cards or a single secure digital T DR memory card. AFT • DMA supported through the GPDMA controller. 7.19 I2C-bus serial I/O controller The LPC2470 contains three I2C-bus controllers. The I2C-bus is bidirectional, for inter-IC control using only two wires: a serial clock line (SCL), and a serial data line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed. The I2C-bus is a multi-master bus and can be controlled by more than one bus master connected to it. The I2C-bus implemented in LPC2470 supports bit rates up to 400 kbit/s (Fast I2C-bus). 7.19.1 Features • I2C0 is a standard I2C compliant bus interface with open-drain pins. • I2C1 and I2C2 use standard I/O pins and do not support powering off of individual devices connected to the same bus lines. • Easy to configure as master, slave, or master/slave. • Programmable clocks allow versatile rate control. • Bidirectional data transfer between masters and slaves. • Multi-master bus (no central master). • Arbitration between simultaneously transmitting masters without corruption of serial data on the bus. • Serial clock synchronization allows devices with different bit rates to communicate via one serial bus. • Serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. • The I2C-bus can be used for test and diagnostic purposes. 7.20 I2S-bus serial I/O controllers The I2S-bus provides a standard communication interface for digital audio applications. The I2S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I2S connection has one master, which is always the master, and one slave. The I2S interface on the LPC2470 provides a separate transmit and receive channel, each of which can operate as either a master or a slave. Preliminary data sheet Rev. 01.01 — 24 September 2009 38 of 83,

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7.20.1 Features DR DA R

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F AT FT • The interface has separate input/output channels each of which can operate in D master R DR or slave mode. AF AT • Capable of handling 8-bit, 16-bit, and 32-bit word sizes. DRA • Mono and stereo audio data supported. FT • The sampling frequency can range from 16 kHz to 48 kHz (16, 22.05, 32, 44.1, 48) kHz. • Configurable word select period in master mode (separately for I2S input and output). • Two 8 word FIFO data buffers are provided, one for transmit and one for receive. • Generates interrupt requests when buffer levels cross a programmable boundary. • Two DMA requests, controlled by programmable buffer levels. These are connected to the GPDMA block. • Controls include reset, stop and mute options separately for I2S input and I2S output. 7.21 General purpose 32-bit timers/external event counters The LPC2470 includes four 32-bit Timer/Counters. The Timer/Counter is designed to count cycles of the system derived clock or an externally-supplied clock. It can optionally generate interrupts or perform other actions at specified timer values, based on four match registers. The Timer/Counter also includes four capture inputs to trap the timer value when an input signal transitions, optionally generating an interrupt. 7.21.1 Features • A 32-bit Timer/Counter with a programmable 32-bit prescaler. • Counter or Timer operation. • Up to four 32-bit capture channels per timer, that can take a snapshot of the timer value when an input signal transitions. A capture event may also optionally generate an interrupt. • Four 32-bit match registers that allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Up to four external outputs corresponding to match registers, with the following capabilities: – Set LOW on match. – Set HIGH on match. – Toggle on match. – Do nothing on match. Preliminary data sheet Rev. 01.01 — 24 September 2009 39 of 83,

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7.22 Pulse width modulator DR DA R

D

F AF The PWM is based on the standard Timer block and inherits all of its features, aTlt hDo T Rugh DR only the PWM function is pinned out on the LPC2470. The Timer is designed to couAnFt A cycles of the system derived clock and optionally switch pins, generate interrupts orTDperform other actions when specified timer values occur, based on seven match registersR. AF The PWM function is in addition to these features and is based on match register events. T The ability to separately control rising and falling edge locations allows the PWM to be used for more applications. For instance, multi-phase motor control typically requires three non-overlapping PWM outputs with individual control of all three pulse widths and positions. Two match registers can be used to provide a single edge controlled PWM output. A dedicated match register controls the PWM cycle rate, by resetting the count upon match. The other match register controls the PWM edge position. Additional single edge controlled PWM outputs require only one match register each, since the repetition rate is the same for all PWM outputs. Multiple single edge controlled PWM outputs will all have a rising edge at the beginning of each PWM cycle, when an PWMMR0 match occurs. Three match registers can be used to provide a PWM output with both edges controlled. Again, a dedicated match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. With double edge controlled PWM outputs, specific match registers control the rising and falling edge of the output. This allows both positive going PWM pulses (when the rising edge occurs prior to the falling edge), and negative going PWM pulses (when the falling edge occurs prior to the rising edge). 7.22.1 Features • LPC2470 has two PWMs with the same operational features. These may be operated in a synchronized fashion by setting them both up to run at the same rate, then enabling both simultaneously. PWM0 acts as the master and PWM1 as the slave for this use. • Counter or Timer operation (may use the peripheral clock or one of the capture inputs as the clock source). • Seven match registers allow up to 6 single edge controlled or 3 double edge controlled PWM outputs, or a mix of both types. The match registers also allow: – Continuous operation with optional interrupt generation on match. – Stop timer on match with optional interrupt generation. – Reset timer on match with optional interrupt generation. • Supports single edge controlled and/or double edge controlled PWM outputs. Single edge controlled PWM outputs all go HIGH at the beginning of each cycle unless the output is a constant LOW. Double edge controlled PWM outputs can have either edge occur at any position within a cycle. This allows for both positive going and negative going pulses. Preliminary data sheet Rev. 01.01 — 24 September 2009 40 of 83,

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T T • D

T

Pulse period and width can be any number of timer counts. This allows DcRompleteR DA A flexibility in the trade-off between resolution and repetition rate. All PWM ouFtTp uts wi FllT occur at the same repetition rate. DR DA RA • Double edge controlled PWM outputs can be programmed to be either positive gFoTi nDg or negative going pulses. RAF • Match register updates are synchronized with pulse outputs to prevent generation of T erroneous pulses. Software must ‘release’ new match values before they can become effective. • May be used as a standard timer if the PWM mode is not enabled. • A 32-bit Timer/Counter with a programmable 32-bit Prescaler. 7.23 Watchdog timer The purpose of the watchdog is to reset the microcontroller within a reasonable amount of time if it enters an erroneous state. When enabled, the watchdog will generate a system reset if the user program fails to ‘feed’ (or reload) the watchdog within a predetermined amount of time. 7.23.1 Features • Internally resets chip if not periodically reloaded. • Debug mode. • Enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. • Incorrect/Incomplete feed sequence causes reset/interrupt if enabled. • Flag to indicate watchdog reset. • Programmable 32-bit timer with internal prescaler. • Selectable time period from (Tcy(WDCLK) × 256 × 4) to (Tcy(WDCLK) × 232 × 4) in multiples of Tcy(WDCLK) × 4. • The Watchdog Clock (WDCLK) source can be selected from the RTC clock, the Internal RC oscillator (IRC), or the APB peripheral clock. This gives a wide range of potential timing choices of Watchdog operation under different power reduction conditions. It also provides the ability to run the WDT from an entirely internal source that is not dependent on an external crystal and its associated components and wiring, for increased reliability. 7.24 RTC and battery RAM The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. It uses little power in Power-down and Deep power-down modes. On the LPC2470, the RTC can be clocked by a separate 32.768 kHz oscillator or by a programmable prescale divider based on the APB clock. Also, the RTC is powered by its own power supply pin, VBAT, which can be connected to a battery or to the same 3.3 V supply used by the rest of the device. Preliminary data sheet Rev. 01.01 — 24 September 2009 41 of 83,

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TTDTThe VBAT pin supplies power only to the RTC and the Battery RAM. TheseD tRwAo functRioAns

D

require a minimum of power to operate, which can be supplied by an external bFaTt tery.

FT

When the CPU and the rest of chip functions are stopped and power removed, thDeR RTC DA RA can supply an alarm output that can be used by external hardware to restore chip poFwTer and resume operation. DRAFT 7.24.1 Features • Measures the passage of time to maintain a calendar and clock. • Ultra low power design to support battery powered systems. • Provides Seconds, Minutes, Hours, Day of Month, Month, Year, Day of Week, and Day of Year. • Dedicated 32 kHz oscillator or programmable prescaler from APB clock. • Dedicated power supply pin can be connected to a battery or to the main 3.3 V. • An alarm output pin is included to assist in waking up when the chip has had power removed to all functions except the RTC and Battery RAM. • Periodic interrupts can be generated from increments of any field of the time registers, and selected fractional second values. This enhancement enables the RTC to be used as a System Timer. • 2 kB data SRAM powered by VBAT. • RTC and Battery RAM power supply is isolated from the rest of the chip. 7.25 Clocking and power control 7.25.1 Crystal oscillators The LPC2470 includes three independent oscillators. These are the Main Oscillator, the Internal RC oscillator, and the RTC oscillator. Each oscillator can be used for more than one purpose as required in a particular application. Any of the three clock sources can be chosen by software to drive the PLL and ultimately the CPU. Following reset, the LPC2470 will operate from the Internal RC oscillator until switched by software. This allows systems to operate without any external crystal and the bootloader code to operate at a known frequency. 7.25.1.1 Internal RC oscillator The IRC may be used as the clock source for the WDT, and/or as the clock that drives the PLL and subsequently the CPU. The nominal IRC frequency is 4 MHz. The IRC is trimmed to 1 % accuracy. Upon power-up or any chip reset, the LPC2470 uses the IRC as the clock source. Software may later switch to one of the other available clock sources. 7.25.1.2 Main oscillator The main oscillator can be used as the clock source for the CPU, with or without using the PLL. The main oscillator operates at frequencies of 1 MHz to 24 MHz. This frequency can be boosted to a higher frequency, up to the maximum CPU operating frequency, by the PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of Preliminary data sheet Rev. 01.01 — 24 September 2009 42 of 83,

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TTDTPLLCLKIN and CCLK are the same value unless the PLL is active and connDeRcAted. ThRe

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clock frequency for each peripheral can be selected individually and is referredF tTo as

FT

PCLK. Refer to Section 7.25.2 for additional information. DR DA RF AT 7.25.1.3 RTC oscillator DRA The RTC oscillator can be used as the clock source for the RTC and/or the WDT. Also, the FT RTC oscillator can be used to drive the PLL and the CPU. 7.25.2 PLL The PLL accepts an input clock frequency in the range of 32 kHz to 24 MHz. The input frequency is multiplied up to a high frequency, then divided down to provide the actual clock used by the CPU and the USB block. The PLL input, in the range of 32 kHz to 24 MHz, may initially be divided down by a value ‘N’, which may be in the range of 1 to 256. This input division provides a wide range of output frequencies from the same input frequency. Following the PLL input divider is the PLL multiplier. This can multiply the input divider output through the use of a Current Controlled Oscillator (CCO) by a value ‘M’, in the range of 1 through 32768. The resulting frequency must be in the range of 275 MHz to 550 MHz. The multiplier works by dividing the CCO output by the value of M, then using a phase-frequency detector to compare the divided CCO output to the multiplier input. The error value is used to adjust the CCO frequency. The PLL is turned off and bypassed following a chip Reset and by entering Power-down mode. PLL is enabled by software only. The program must configure and activate the PLL, wait for the PLL to lock, then connect to the PLL as a clock source. 7.25.3 Wake-up timer The LPC2470 begins operation at power-up and when awakened from Power-down and Deep-power down modes by using the 4 MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. When the main oscillator is initially activated, the wake-up timer allows software to ensure that the main oscillator is fully functional before the processor uses it as a clock source and starts to execute instructions. This is important at power on, all types of Reset, and whenever any of the aforementioned functions are turned off for any reason. Since the oscillator and other functions are turned off during Power-down and Deep power-down modes, any wake-up of the processor from Power-down modes makes use of the Wake-up Timer. The Wake-up Timer monitors the crystal oscillator to check whether it is safe to begin code execution. When power is applied to the chip, or when some event caused the chip to exit Power-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. The amount of time depends on many factors, including the rate of VDD(3V3) ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz crystal is used), as well as any other external circuitry (e.g., capacitors), and the characteristics of the oscillator itself under the existing ambient conditions. Preliminary data sheet Rev. 01.01 — 24 September 2009 43 of 83,

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7.25.4 Power control DR DA R

D

F AF The LPC2470 supports a variety of power control features. There are four speciTa lD modesT D of processor power reduction: Idle mode, Sleep mode, Power-down mode, and DeReAp RF A power-down mode. The CPU clock rate may also be controlled as needed by changinTg D clock sources, reconfiguring PLL values, and/or altering the CPU clock divider value. ThisR AF allows a trade-off of power versus processing speed based on application requirements. T In addition, Peripheral power control allows shutting down the clocks to individual on-chip peripherals, allowing fine tuning of power consumption by eliminating all dynamic power use in any peripherals that are not required for the application. Each of the peripherals has its own clock divider which provides even better power control. The LPC2470 also implements a separate power domain in order to allow turning off power to the bulk of the device while maintaining operation of the RTC and a small SRAM, referred to as the Battery RAM. 7.25.4.1 Idle mode In Idle mode, execution of instructions is suspended until either a Reset or interrupt occurs. Peripheral functions continue operation during Idle mode and may generate interrupts to cause the processor to resume execution. Idle mode eliminates dynamic power used by the processor itself, memory systems and related controllers, and internal buses. 7.25.4.2 Sleep mode In Sleep mode, the oscillator is shut down and the chip receives no internal clocks. The processor state and registers, peripheral registers, and internal SRAM values are preserved throughout Sleep mode and the logic levels of chip pins remain static. The output of the IRC is disabled but the IRC is not powered down for a fast wake-up later. The 32 kHz RTC oscillator is not stopped because the RTC interrupts may be used as the wake-up source. The PLL is automatically turned off and disconnected. The CCLK and USB clock dividers automatically get reset to zero. The Sleep mode can be terminated and normal operation resumed by either a Reset or certain specific interrupts that are able to function without clocks. Since all dynamic operation of the chip is suspended, Sleep mode reduces chip power consumption to a very low value. On the wake-up from Sleep mode, if the IRC was used before entering Sleep mode, the code execution and peripherals activities will resume after 4 cycles expire. If the main external oscillator was used, the code execution will resume when 4096 cycles expire. The customers need to reconfigure the PLL and clock dividers accordingly. 7.25.4.3 Power-down mode Power-down mode does everything that Sleep mode does but also turns off the IRC oscillator. On the wake-up from Power-down mode, if the IRC was used before entering Power-down mode, it will take IRC 60 μs to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. The customers need to reconfigure the PLL and clock dividers accordingly after a wake-up from Power-down mode. Preliminary data sheet Rev. 01.01 — 24 September 2009 44 of 83,

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7.25.4.4 Deep power-down mode DR DA R

D

F AF Deep power-down mode is similar to the Power-down mode, but now the on-chiTpDTDregulator that supplies power to the internal logic is also shut off. This produces the RloAw RF est A possible power consumption without removing power from the entire chip. Since the DeT eDp power-down mode shuts down the on-chip logic power supply, there is no register or RA memory retention, and resumption of operation involves the same activities as a full chip FT reset. If power is supplied to the LPC2470 during Deep power-down mode, wake-up can be caused by the RTC Alarm interrupt or by external Reset. While in Deep power-down mode, external device power may be removed. In this case, the LPC2470 will start up when external power is restored. Essential data may be retained through Deep power-down mode (or through complete powering off of the chip) by storing data in the Battery RAM, as long as the external power to the VBAT pin is maintained. 7.25.4.5 Power domains The LPC2470 provides two independent power domains that allow the bulk of the device to have power removed while maintaining operation of the RTC and the Battery RAM. On the LPC2470, I/O pads are powered by the 3.3 V (VDD(3V3)) pins, while the VDD(DCDC)(3V3) pins power the on-chip DC-to-DC converter which in turn provides power to the CPU and most of the peripherals. Although both the I/O pad ring and the core require a 3.3 V supply, different powering schemes can be used depending on the actual application requirements. The first option assumes that power consumption is not a concern and the design ties the VDD(3V3) and VDD(DCDC)(3V3) pins together. This approach requires only one 3.3 V power supply for both pads, the CPU, and peripherals. While this solution is simple, it does not support powering down the I/O pad ring “on the fly” while keeping the CPU and peripherals alive. The second option uses two power supplies; a 3.3 V supply for the I/O pads (VDD(3V3)) and a dedicated 3.3 V supply for the CPU (VDD(DCDC)(3V3)). Having the on-chip DC-DC converter powered independently from the I/O pad ring enables shutting down of the I/O pad power supply “on the fly”, while the CPU and peripherals stay active. The VBAT pin supplies power only to the RTC and the Battery RAM. These two functions require a minimum of power to operate, which can be supplied by an external battery. When the CPU and the rest of chip functions are stopped and power removed, the RTC can supply an alarm output that may be used by external hardware to restore chip power and resume operation. 7.26 System control 7.26.1 Reset Reset has four sources on the LPC2470: the RESET pin, the Watchdog reset, power-on reset, and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger input pin. Assertion of chip Reset by any source, once the operating voltage attains a usable Preliminary data sheet Rev. 01.01 — 24 September 2009 45 of 83,

DR

TTDTlevel, starts the wake-up timer (see description in Section 7.25.3 “Wake-up DtiRm DAer”), RA causing reset to remain asserted until the external Reset is de-asserted, the osFcTi llator isFTrunning, and a fixed number of clocks have passed. DR DA RF AT Once the internal reset is removed, all of the processor and peripheral registers have DR been initialized to predetermined values and the LPC2470 continues with booting from an AF external static memory. T 7.26.2 Boot process The processor always boots from the off-chip static memory bank 1, executing code from address 0x8100 0000 (see Table 5 “LPC2470 memory usage and details”). During the boot process initiated by POR, the boot pins P3[15]/D15 and P3[14]/D14 are sampled, and the external memory banks 0 and 1 are configured with the same data bus width. The data bus width is determined by the setting of the two boot pins. Unused address pins are configured as GPIO. See Section 11.5 “Suggested boot memory interface solutions” for address and data bus interface details. Remark: After POR, the address ranges of chip select 1 and chip select 0 are swapped. The user code residing in the external boot memory must be linked to execute from address location 0x8000 0000. When booting from external memory, the interrupt vectors are mapped to the bottom of the external memory. Once booting is over, the application must map interrupt vectors to the proper domain. 7.26.3 Brownout detection The LPC2470 includes 2-stage monitoring of the voltage on the VDD(DCDC)(3V3) pins. If this voltage falls below 2.95 V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the VIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts a BOD Reset and generates a Reset (if this reset source is enabled in software) to inactivate the LPC2470 when the voltage on the VDD(DCDC)(3V3) pins falls below 2.65 V. The BOD circuit maintains this reset down below 1 V, at which point the power-on reset circuitry maintains the overall Reset. Both the 2.95 V and 2.65 V thresholds include some hysteresis. In normal operation, this hysteresis allows the 2.95 V detection to reliably interrupt, or a regularly-executed event loop to sense the condition. 7.26.4 AHB The LPC2470 implements two AHB in order to allow the Ethernet block to operate without interference caused by other system activity. The primary AHB, referred to as AHB1, includes the Vectored Interrupt Controller, GPDMA controller, USB interface, and 16 kB SRAM. The second AHB, referred to as AHB2, includes only the Ethernet block and an associated 16 kB SRAM. In addition, a bus bridge is provided that allows the secondary AHB to be a bus master on AHB1, allowing expansion of Ethernet buffer space into off-chip memory or unused space in memory residing on AHB1. Preliminary data sheet Rev. 01.01 — 24 September 2009 46 of 83,

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TTDTIn summary, bus masters with access to AHB1 are the ARM7 itself, the USBDR bAlock, thReA

D

GPDMA function, and the Ethernet block (via the bus bridge from AHB2). Bus mFTa sters

FT

with access to AHB2 are the ARM7 and the Ethernet block. DR DA RF AT 7.26.5 External interrupt inputs DRA The LPC2470 includes up to 68 edge sensitive interrupt inputs combined with up to four FT level sensitive external interrupt inputs as selectable pin functions. The external interrupt inputs can optionally be used to wake up the processor from Power-down mode. 7.26.6 Memory mapping control The memory mapping control alters the mapping of the interrupt vectors that appear at the beginning at address 0x0000 0000. Vectors may be mapped to the bottom of the Boot ROM, the SRAM, or external memory. This allows code running in different memory spaces to have control of the interrupts. When booting from an external memory the interrupt vectors are mapped to the bottom of the external memory. Once booting is over the application must map interrupt vectors to the proper domain. 7.27 Emulation and debugging The LPC2470 support emulation and debugging via a JTAG serial port. A trace port allows tracing program execution. Debugging and trace functions are multiplexed only with GPIOs on P2[0] to P2[9]. This means that all communication, timer, and interface peripherals residing on other pins are available during the development and debugging phase as they are when the application is run in the embedded system itself. 7.27.1 EmbeddedICE The EmbeddedICE logic provides on-chip debug support. The debugging of the target system requires a host computer running the debugger software and an EmbeddedICE protocol convertor. The EmbeddedICE protocol convertor converts the Remote Debug Protocol commands to the JTAG data needed to access the ARM7TDMI-S core present on the target system. The ARM core has a Debug Communication Channel (DCC) function built-in. The DCC allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. The DCC is accessed as a coprocessor 14 by the program running on the ARM7TDMI-S core. The DCC allows the JTAG port to be used for sending and receiving data without affecting the normal program flow. The DCC data and control registers are mapped in to addresses in the EmbeddedICE logic. The JTAG clock (TCK) must be slower than 1⁄6 of the CPU clock (CCLK) for the JTAG interface to operate. 7.27.2 Embedded trace Since the LPC2470 have significant amounts of on-chip memories, it is not possible to determine how the processor core is operating simply by observing the external pins. The ETM provides real-time trace capability for deeply embedded processor cores. It outputs Preliminary data sheet Rev. 01.01 — 24 September 2009 47 of 83,

DR

TTDTinformation about processor execution to a trace port. A software debuggerD aRlAlows R

D A

configuration of the ETM using a JTAG interface and displays the trace informaFtTio n thatFThas been captured. DR DA RF AT The ETM is connected directly to the ARM core and not to the main AMBA system bus .D IRt compresses the trace information and exports it through a narrow trace port. An external AF Trace Port Analyzer captures the trace information under software debugger control. The T trace port can broadcast the Instruction trace information. Instruction trace (or PC trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. Instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the pipeline status on a cycle by cycle basis. Trace information generation can be controlled by selecting the trigger resource. Trigger resources include address comparators, counters and sequencers. Since trace information is compressed the software debugger requires a static image of the code being executed. Self-modifying code can not be traced because of this restriction. 7.27.3 RealMonitor RealMonitor is a configurable software module, developed by ARM Inc., which enables real-time debug. It is a lightweight debug monitor that runs in the background while users debug their foreground application. It communicates with the host using the DCC, which is present in the EmbeddedICE logic. The LPC2470 contain a specific configuration of RealMonitor software programmed into the on-chip ROM memory. Preliminary data sheet Rev. 01.01 — 24 September 2009 48 of 83,

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8. Limiting values DR DR DAF ATFDTDTable 6. Limiting values RA RF A In accordance with the Absolute Maximum Rating System (IEC 60134).[1] T D Symbol Parameter Conditions Min Max Unit RAFT VDD(3V3) supply voltage (3.3 V) core and external 3.0 3.6 V rail VDD(DCDC)(3V3) DC-to-DC converter supply voltage 3.0 3.6 V (3.3 V) VDDA analog 3.3 V pad supply voltage −0.5 +4.6 V Vi(VBAT) input voltage on pin VBAT for the RTC −0.5 +4.6 V Vi(VREF) input voltage on pin VREF −0.5 +4.6 V VIA analog input voltage on ADC related −0.5 +5.1 V pins VI input voltage5Vtolerant I/O [2] −0.5 +6.0 V pins; only valid when the VDD(3V3) supply voltage is present other I/O pins [2][3] −0.5 VDD(3V3) + V 0.5 IDD supply current per supply pin [4] - 100 mA ISS ground current per ground pin [4] - 100 mA Tstg storage temperature [5] −65 +150 °C Ptot(pack) total power dissipation (per package) based on package - 1.5 W heat transfer, not device power consumption Vesd electrostatic discharge voltage human body [6] −2 500 +2 500 V model; all pins [1] The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to VSSIO/VSSCORE unless otherwise noted. [2] Including voltage on outputs in 3-state mode. [3] Not to exceed 4.6 V. [4] The peak current is limited to 25 times the corresponding maximum current. [5] Dependent on package type. [6] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 kΩ series resistor. Preliminary data sheet Rev. 01.01 — 24 September 2009 49 of 83,

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9. Static characteristics DR DR DAF ATFDTDTable 7. Static characteristics RA RF A Tamb = −40 °C to +85 °C for commercial applications, unless otherwise specified. T D Symbol Parameter Conditions Min Typ[1] Max Unit RAFT VDD(3V3) supply voltage (3.3 V) core and external rail 3.0 3.3 3.6 V VDD(DCDC)(3V3) DC-to-DC converter 3.0 3.3 3.6 V supply voltage (3.3 V) VDDA analog 3.3 V pad 3.0 3.3 3.6 V supply voltage Vi(VBAT) input voltage on pin [2] 2.0 3.3 3.6 V

VBAT

Vi(VREF) input voltage on pin 2.5 3.3 VDDA V

VREF

Standard port pins, RESET, RTCK IIL LOW-level input VI = 0 V; no pull-up - - 3 μA current IIH HIGH-level input VI = VDD(3V3); no pull-down - - 3 μA current IOZ OFF-state output VO = 0 V; VO = VDD(3V3); - - 3 μA current no pull-up/down Ilatch I/O latch-up current −(0.5VDD(3V3)) < VI < - - 100 mA (1.5VDD(3V3)); Tj < 125 °C VI input voltage pin configured to provide a [3][4][5] 0 - 5.5 V digital function [6] VO output voltage output active 0 - VDD(3V3) V VIH HIGH-level input 2.0 - - V voltage VIL LOW-level input - - 0.8 V voltage Vhys hysteresis voltage 0.4 - - V VOH HIGH-level output IOH = −4 mA [7] VDD(3V3) − - - V voltage 0.4 VOL LOW-level output IOL = −4 mA [7] - - 0.4 V voltage IOH HIGH-level output VOH = VDD(3V3) − 0.4 V [7] −4 - - mA current IOL LOW-level output VOL = 0.4 V [7] 4 - - mA current IOHS HIGH-level VOH = 0 V [8] - - −45 mA short-circuit output current IOLS LOW-level short-circuit VOL = VDDA [8] - - 50 mA output current Ipd pull-down current VI = 5 V [9] 10 50 150 μA Ipu pull-up current VI = 0 V −15 −50 −85 μA VDD(3V3) < VI < 5 V [9] 000μA Preliminary data sheet Rev. 01.01 — 24 September 2009 50 of 83,

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Table 7. Static characteristicsDDD…continued RA RA Tamb = −40 °C to +85 °C for commercial applications, unless otherwise specified. FTFTDSymbol Parameter Conditions Min Typ[1] Max DRAUnitRIF

A

DD(DCDC)act(3V3) active mode DC-to-DC VDD(DCDC)(3V3) = 3.3 V; T converter supply T Damb = 25 °C; code RA current (3.3 V) while(1){} FT executed from the on-chip SRAM; no peripherals enabled; PCLK = CCLK / 8 CCLK = 12 MHz - 17.4 - mA CCLK = 72 MHz - 66.1 - mA IDD(DCDC)pd(3V3) power-down mode VDD(DCDC)(3V3) = 3.3 V; DC-to-DC converter Tamb = 25 °C supply current (3.3 V) - 150 - μA IBATact active mode battery DC-to-DC converter on [10] - 20 - μA supply current DC-to-DC converter off [10] - 28 - μA I2C-bus pins (P0[27] and P0[28]) VIH HIGH-level input 0.7VDD(3V3) - - V voltage VIL LOW-level input - - 0.3VDD(3V3) V voltage Vhys hysteresis voltage - 0.5VDD(3V3) - V VOL LOW-level output IOLS = 3 mA [7] - - 0.4 V voltage ILI input leakage current VI = VDD(3V3) [11] - 2 4 μA VI = 5 V - 10 22 μA Oscillator pins Vi(XTAL1) input voltage on pin −0.5 1.8 1.95 V XTAL1 Vo(XTAL2) output voltage on pin −0.5 1.8 1.95 V XTAL2 Vi(RTCX1) input voltage on pin −0.5 1.8 1.95 V RTCX1 Vo(RTCX2) output voltage on pin −0.5 1.8 1.95 V RTCX2 Preliminary data sheet Rev. 01.01 — 24 September 2009 51 of 83,

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Table 7. Static characteristicsDDD…continued RA RA Tamb = −40 °C to +85 °C for commercial applications, unless otherwise specified. FTFTDSymbol Parameter Conditions Min Typ[1] Max DRAUnit RA USB pins FT D IOZ OFF-state output0V< V

R

I < 3.3 V - - ±10 μA A current FT VBUS bus supply voltage - - 5.25 V VDI differential input |(D+) − (D−)| 0.2 - - V sensitivity voltage VCM differential common includes VDI range 0.8 - 2.5 V mode voltage range Vth(rs)se single-ended receiver 0.8 - 2.0 V switching threshold voltage VOL LOW-level output RL of 1.5 kΩ to 3.6 V - - 0.18 V voltage for low-/full-speed VOH HIGH-level output RL of 15 kΩ to GND 2.8 - 3.5 V voltage (driven) for low-/full-speed Ctrans transceiver pin to GND - - 20 pF capacitance ZDRV driver output with 33 Ω series resistor; [12] 36 - 44.1 Ω impedance for driver steady state drive which is not high-speed capable Rpu pull-up resistance SoftConnect = ON 1.1 - 1.9 kΩ [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages [2] The RTC typically fails when Vi(VBAT) drops below 1.6 V. [3] Including voltage on outputs in 3-state mode. [4] VDD(3V3) supply voltages must be present. [5] 3-state outputs go into 3-state mode when VDD(3V3) is grounded. [6] Please also see the errata note in errata sheet. [7] Accounts for 100 mV voltage drop in all supply lines. [8] Allowed as long as the current limit does not exceed the maximum current allowed by the device. [9] Minimum condition for VI = 4.5 V, maximum condition for VI = 5.5 V. [10] On pin VBAT. [11] To VSSIO/VSSCORE. [12] Includes external resistors of 33 Ω ± 1 % on D+ and D−. Preliminary data sheet Rev. 01.01 — 24 September 2009 52 of 83,

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9.1 Power consumption static characteristics DR D DA RF AT FT Table 8. Power consumption static characteristicsDRDR Tamb = −40 °C to +85 °C for commercial applications, unless otherwise specified. AF AT Symbol Parameter Conditions Min Typ[1] Max Uni Dt RA Deep power-down mode FT IBAT battery supply current [2] - 19 - μA IDD(DCDC)dpd(3V3) deep power-down [2] mode DC-to-DC converter supply current (3.3 V) - 19 - μA Power-down mode IBAT battery supply current [2] - 18 - μA IDD(DCDC)pd(3V3) power-down mode [2] DC-to-DC converter supply current (3.3 V) - 113 - μA [1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages [2] VDD(DCDC)(3V3) = 3.3 V; VDD(3V3) = 3.3 V; Vi(VBAT) = 3.3 V; Tamb = 25 °C. 9.1.1 Deep power-down mode 002aae046 IDD(IO) (μA) VDD(3V3) = 3.3 V VDD(3V3) = 3.0 V −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 °C. Fig 5. I/O maximum supply current IDDdpd(3V3) versus temperature in Deep power-down mode Preliminary data sheet Rev. 01.01 — 24 September 2009 53 of 83,

DR TDTTRDA R D F AF

002aae047TDT40 R DA RAIBAT F (μA) T DR 30 AFT Vi(VBAT) = 3.3 V Vi(VBAT) = 3.0 V −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 °C

Fig 6. RTC battery maximum supply current IBAT versus temperature in Deep

power-down mode 002aae048 IDD(DCDC)dpd(3v3) (μA) VDD(DCDC)(3V3) = 3.3 V VDD(DCDC)(3V3) = 3.0 V −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = Vi(VBAT) = 3.3 V; Tamb = 25 °C.

Fig 7. Total DC-to-DC converter maximum supply current IDD(DCDC)dpd(3V3) versus

temperature in Deep power-down mode Preliminary data sheet Rev. 01.01 — 24 September 2009 54 of 83,

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9.1.2 Power-down mode DR D DA RF AFTTDRD002aae049 A

R F A4 T D

I RDD(IO) A (μA) FT VDD(3V3) = 3.3 V VDD(3V3) = 3.0 V −2 −4 −40 −15 10 35 60 85 temperature (°C) Vi(VBAT) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 °C.

Fig 8. I/O maximum supply current IDD(IO) versus temperature in Power-down mode

002aae050

IBAT

(μA) Vi(VBAT) = 3.3 V Vi(VBAT) = 3.0 V −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = VDD(DCDC)(3V3) = 3.3 V; Tamb = 25 °C.

Fig 9. RTC battery maximum supply current IBATversus temperature in Power-down

mode Preliminary data sheet Rev. 01.01 — 24 September 2009 55 of 83,

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TDTRD

T

A R

D A

002aae051FF800TDTRDR IDD(DCDC)pd(3v3) A (μA) F

A

T D 600 RAFT VDD(DCDC)(3V3) = 3.3 V 200 VDD(DCDC)(3V3) = 3.0 V −40 −15 10 35 60 85 temperature (°C) VDD(3V3) = Vi(VBAT) = 3.3 V; Tamb = 25 °C. Fig 10. Total DC-to-DC converter supply current IDD(DCDC)dpd(3V3) at different temperatures in Power-down mode Preliminary data sheet Rev. 01.01 — 24 September 2009 56 of 83,

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9.2 ADC static characteristics DR DA R

D F AT FT Table 9. ADC static characteristicsDRDR VDDA = 2.5 V to 3.6 V; Tamb = −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz. AF AT Symbol Parameter Conditions Min Typ Max Unit DRA VIA analog input voltage 0 - VDDA V FT Cia analog input capacitance - - 1 pF ED differential linearity error [1][2][3] - - ±1 LSB EL(adj) integral non-linearity [1][4] - - ±2 LSB EO offset error [1][5] - - ±3 LSB EG gain error [1][6] - - ±0.5 % ET absolute error [1][7] - - ±4 LSB Rvsi voltage source interface [8] - - 40 kΩ

resistance [1] Conditions: VSSA = 0 V, VDDA = 3.3 V. [2] The ADC is monotonic, there are no missing codes. [3] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 11. [4] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 11. [5] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal curve. See Figure 11. [6] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See Figure 11. [7] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and the ideal transfer curve. See Figure 11. [8] See Figure 12. Preliminary data sheet Rev. 01.01 — 24 September 2009 57 of 83,

DR TDTTRDR DAF AF

offset gaTinTerror erroDrRDEO EG A

R F AT D

1023 RAFT (2) code (1) out (5) (4) (3) 1 1 LSB (ideal) 12345671018 1019 1020 1021 1022 1023 1024 VIA (LSBoffset error ideal ) EO V − V 1 LSB = DDA SSA 002aac046 (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error (ED). (4) Integral non-linearity (EL(adj)). (5) Center of a step of the actual transfer curve.

Fig 11. ADC characteristics

Preliminary data sheet Rev. 01.01 — 24 September 2009 58 of 83,

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TDTDTRA R

D

F AT FT LPC2XXXDRDA RF AT 20 kΩ AD0[y] Rvsi D AD0[y] RSAMPLE AFT 3 pF 5 pF

VEXT

VSSIO, VSSCORE 002aad586 Fig 12. Suggested ADC interface - LPC2470 AD0[y] pin Preliminary data sheet Rev. 01.01 — 24 September 2009 59 of 83,

DR

10. Dynamic characteristics DR DR DAF ATFDTDTable 10. Dynamic characteristics of USB pins (full-speed) RA RF A CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD(3V3),unless otherwise specified. T D Symbol Parameter Conditions Min Typ Max Unit RAFT tr rise time 10 % to 90 % 8.5 - 13.8 ns tf fall time 10 % to 90 % 7.7 - 13.7 ns tFRFM differential rise and fall time tr / tf - - 109 % matching VCRS output signal crossover voltage 1.3 - 2.0 V tFEOPT source SE0 interval of EOP see Figure 14 160 - 175 ns tFDEOP source jitter for differential transition see Figure 14 −2 - +5 ns to SE0 transition tJR1 receiver jitter to next transition −18.5 - +18.5 ns tJR2 receiver jitter for paired transitions 10 % to 90 % −9 - +9 ns tEOPR1 EOP width at receiver must reject as [1] 40 - - ns EOP; see Figure 14 tEOPR2 EOP width at receiver must accept as [1] 82 - - ns EOP; see Figure 14 [1] Characterized but not implemented as production test. Guaranteed by design. Table 11. Dynamic characteristics Tamb = −40 °C to +85 °C for commercial applications; VDD(3V3) over specified ranges.[1] Symbol Parameter Conditions Min Typ[2] Max Unit External clock fosc oscillator frequency 1 - 24 MHz Tcy(clk) clock cycle time 42 - 1000 ns tCHCX clock HIGH time Tcy(clk) × 0.4 - - ns tCLCX clock LOW time Tcy(clk) × 0.4 - - ns tCLCH clock rise time - - 5 ns tCHCL clock fall time - - 5 ns I2C-bus pins (P0[27] and P0[28]) tf(o) output fall time VIH to VIL 20 + 0.1 × Cb[3] - - ns SSP interface tsu(SPI_MISO) SPI_MISO set-up time Tamb = 25 °C; - 11 - ns measured in SPI Master mode; see Figure 15 [1] Parameters are valid over operating temperature range unless otherwise specified. [2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. [3] Bus capacitance Cb in pF, from 10 pF to 400 pF. Preliminary data sheet Rev. 01.01 — 24 September 2009 60 of 83, DR DR DR DR DA RF AF ATTFAF AT T FT NXP SemiconductorsDLDRPC 2D 470 D RA A RFFARFlashless 16-bit/32T- F A Dbit micTr DocontrTo Dller FTR R DA A RFFARTDTFDTRDA RA RF ATFFDTRDA RF AT F TD R DAFT DRA LPC2470_1.01 Preliminary data sheet Rev. 01.01 — 24 September 2009 61 of 83 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 12. Dynamic characteristics: Static external memory interface CL = 30 pF, Tamb = −40 °C to 85 °C, VDD(DCDC)(3V3) = VDD(3V3) = 3.0 V to 3.6 V, AHB clock = 1 MHz Symbol Parameter Conditions Min Typ Max Unit .54 ns .54 ns .49 + Tcy(CCLK) × WAITOEN ns AITRD − WAITOEN + 1) × ns cy(CCLK) − 12.70 .20 ns .20 ns .44 ns .10 + (WAITRD − AITOEN + 1) × Tcy(CCLK) .54 ns .68 ns .20 + Tcy(CCLK) × (1 + ns AITWEN) .98 ns .86 ns .79 ns .10 + Tcy(CCLK) × ns AITWR − WAITWEN + 1) .59 + Tcy(CCLK) × ns AITWR − WAITWEN + 3) .74 + Tcy(CCLK) ns © NXP B.V. 2009. All rights reserved. Common to read and write cycles[1] tCSLAV CS LOW to address valid −0.29 0.20 2 time Read cycle parameters[1][2] tOELAV OE LOW to address valid −0.29 0.20 2 time tCSLOEL CS LOW to OE LOW time −0.78 + Tcy(CCLK) × WAITOEN 0 + Tcy(CCLK) × WAITOEN 0 tam memory access time [3][4] (WAITRD − WAITOEN + 1) × (WAITRD − WAITOEN + 1) × (W Tcy(CCLK) − 8.11 Tcy(CCLK) − 9.57 T th(D) data input hold time [5] 1.29 4.22 5 tCSHOEH CS HIGH to OE HIGH time −0.4900tOEHANV OE HIGH to address invalid −0.20 0.20 2 time tOELOEH OE LOW to OE HIGH time −0.59 + (WAITRD − 0 + (WAITRD − WAITOEN + 0 WAITOEN + 1) × Tcy(CCLK) 1) × Tcy(CCLK) W tBLSLAV BLS LOW to address valid −0.3902time tCSHBLSH CS HIGH to BLS HIGH time −0.88 0.49 0 Write cycle parameters[1][6] tCSLWEL CS LOW to WE LOW time −0.88 + Tcy(CCLK) × (1 + 0.10 + Tcy(CCLK) × (1 + 0 WAITWEN) WAITWEN) W tCSLBLSL CS LOW to BLS LOW time −0.88 0.49 0 tWELDV WE LOW to data valid time 0.68 2.54 5 tCSLDV CS LOW to data valid time 0 2.64 4 tWELWEH WE LOW to WE HIGH time [3] −0.78 + Tcy(CCLK) × 0 + Tcy(CCLK) × (WAITWR − 0 (WAITWR − WAITWEN + 1) WAITWEN + 1) (W tBLSLBLSH BLS LOW to BLS HIGH [3] −0.88 + Tcy(CCLK) × 0 + Tcy(CCLK) × (WAITWR − 0 time (WAITWR − WAITWEN + 3) WAITWEN + 3) (W tWEHANV WE HIGH to address invalid [3] 0 + Tcy(CCLK) 0.20 + Tcy(CCLK) 2 time, DRDDDDARRRRF AFAAAT T FT FT FT

NXP SemiconductorsDLDRPC R 2DR470DAAARA

Flashless 16-bit/3F2T -Dbit mi FcTrFFDocontrTo Dller T RA RA R

D

A RFTFDT

F T

R D DA R RF A ATFDT

F

R DA RF AT F TD R DAFT DRA LPC2470_1.01 Preliminary data sheet Rev. 01.01 — 24 September 2009 62 of 83 xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx Table 12. Dynamic characteristics: Static external memory interface …continued CL = 30 pF, Tamb = −40 °C to 85 °C, VDD(DCDC)(3V3) = VDD(3V3) = 3.0 V to 3.6 V, AHB clock = 1 MHz Symbol Parameter Conditions Min Typ Max Unit .96 ns .54 ns .37 ns © NXP B.V. 2009. All rights reserved. tWEHDNV WE HIGH to data invalid [3] 0.78 2.54 5 time tBLSHANV BLS HIGH to address [3] −0.29 0.20 2 invalid time tBLSHDNV BLS HIGH to data invalid [3] 0 2.54 5 time [1] VOH = 2.5 V, VOL = 0.2 V. [2] VIH = 2.5 V, VIL = 0.5 V. [3] Tcy(CCLK) = 1⁄CCLK. [4] Latest of address valid, CS LOW, OE LOW to data valid. [5] Earliest of CS HIGH, OE HIGH, address change to data invalid. [6] Byte lane state bit (PB) = 1.,

DR

TDTDTDTable 13. Dynamic characteristics: Dynamic external memory interface RA RA CL = 30 pF, T F Famb = −40 °C to 85 °C, VDD(DCDC)(3V3) = VDD(3V3) = 3.0 V to 3.6 V, AHB clock = 1 MHzTDTDSymbol Parameter Conditions Min Typ Max RAUnit RF A Common T DR td(SV) chip select valid delay time - 1.05 1.76 ns AFT th(S) chip select hold time 0.1 1.02 - ns td(RASV) row address strobe valid delay time - 1.51 1.95 ns th(RAS) row address strobe hold time 0.5 1.51 - ns td(CASV) column address strobe valid delay time - 0.98 1.27 ns th(CAS) column address strobe hold time 0.1 0.97 - ns td(WV) write valid delay time - 0.84 1.95 ns th(W) write hold time 0.1 0.84 - ns td(GV) output enable valid delay time - 0.95 1.86 ns th(G) output enable hold time 0.1 1 - ns td(AV) address valid delay time - 0.87 1.95 ns th(A) address hold time 0.1 0.81 - ns Read cycle parameters tsu(D) data input set-up time 0.51 2.24 - ns th(D) data input hold time 0.57 2.41 - ns Write cycle parameters td(QV) data output valid delay time - 2.65 4.36 ns th(Q) data output hold time 0.49 2.61 - ns Preliminary data sheet Rev. 01.01 — 24 September 2009 63 of 83,

DR

10.1 Timing DR D DA RF ATFDTRDA RF AT DR t ACHCX F tCHCL tCLCX tCLCH T Tcy(clk) 002aaa907 Fig 13. External clock timing (with an amplitude of at least Vi(RMS) = 200 mV) TPERIOD crossover point extended crossover point differential data lines source EOP width: tFEOPT differential data to SE0/EOP skew n × TPERIOD + tFDEOP receiver EOP width: tEOPR1, tEOPR2 002aab561 Fig 14. Differential data-to-EOP transition skew and EOP width shifting edges

SCK

sampling edges

MOSI MISO

tsu(SPI_MISO) 002aad326 Fig 15. MISO line set-up time in SSP Master mode Preliminary data sheet Rev. 01.01 — 24 September 2009 64 of 83,

DR TTDT

DR DA RF AF tCSLAV tCSHOEHTDTRDA RA CS FT DRAFT addr tam th(D) data tCSLOEL tOELAV tOEHANV tOELOEH

OE

tBLSLAV tCSHBLSH

BLS

002aad955

Fig 16. External memory read access CS

tAVCSL tWELWEH tCSLWEL tBLSLBLSH BLS/WE tWEHANV tCSLBLSL tWELDV tBLSHANV addr tWEHDNV tCSLDV tBLSHDNV data

OE

002aad956

Fig 17. External memory write access

Preliminary data sheet Rev. 01.01 — 24 September 2009 65 of 83,

DR TDTRD T D A RF AF

referenceTTclock DR DA RF Atd(XXX) th(XXX) T DRAFT output signal (O) tsu(D) th(D) input signal (I) 002aad636

Fig 18. Signal timing

Preliminary data sheet Rev. 01.01 — 24 September 2009 66 of 83,

DR

11. Application information DR DA R

D

F ATFDTRDR 11.1 LCD panel signal usage AF AT D

R

Table 14. LCD panel connections for STN single panel mode AFT External pin 4-bit mono STN single panel 8-bit mono STN single panel Color STN single panel LPC2470 pin LCD function LPC2470 pin LCD function LPC2470 pin LCD function used used used LCDVD[23] - - - - - - LCDVD[22] - - - - - - LCDVD[21] - - - - - - LCDVD[20] - - - - - - LCDVD[19] - - - - - - LCDVD[18] - - - - - - LCDVD[17] - - - - - - LCDVD[16] - - - - - - LCDVD[15] - - - - - - LCDVD[14] - - - - - - LCDVD[13] - - - - - - LCDVD[12] - - - - - - LCDVD[11] - - - - - - LCDVD[10] - - - - - - LCDVD[9] - - - - - - LCDVD[8] - - - - - - LCDVD[7] - - P4[29][3] UD[7] P4[29][3] UD[7] LCDVD[6] - - P4[28][3] UD[6] P4[28][3] UD[6] LCDVD[5] - - P2[13][2] UD[5] P2[13][2] UD[5] LCDVD[4] - - P2[12][2] UD[4] P2[12][2] UD[4] LCDVD[3] P2[9][1] UD[3] P2[9][1] UD[3] P2[9][1] UD[3] LCDVD[2] P2[8][1] UD[2] P2[8][1] UD[2] P2[8][1] UD[2] LCDVD[1] P2[7][1] UD[1] P2[7][1] UD[1] P2[7][1] UD[1] LCDVD[0] P2[6][1] UD[0] P2[6][1] UD[0] P2[6][1] UD[0] LCDLP P2[5][1] LCDLP P2[5][1] LCDLP P2[5][1] LCDLP LCDENAB/ P2[4][1] LCDENAB/ P2[4][1] LCDENAB/ P2[4][1] LCDENAB/ LCDM LCDM LCDM LCDM LCDFP P2[3][1] LCDFP P2[3][1] LCDFP P2[3][1] LCDFP LCDDCLK P2[2][1] LCDDCLK P2[2][1] LCDDCLK P2[2][1] LCDDCLK LCDLE P2[1][1] LCDLE P2[1][1] LCDLE P2[1][1] LCDLE LCDPWR P2[0][1] CDPWR P2[0][1] LCDPWR P2[0][1] LCDPWR LCDCLKIN P2[11][2] LCDCLKIN P2[11][2] LCDCLKIN P2[0][2] LCDPWR [1] ETM replaced with LCD pins. [2] External interrupt pins EINT1, EINT2, EINT3 replaced with LCD pins. [3] Timer pins MAT2[0] and MAT2[1] replaced with LCD pins. Preliminary data sheet Rev. 01.01 — 24 September 2009 67 of 83,

DR T D

TDTDTable 15. LCD panel connections for STN dual panel mode RA RF AF External pin 4-bit mono STN dual panel 8-bit mono STN dual panel Color STN dual panelTDTRDR LPC2470 pin LCD function LPC2470 pin LCD function LPC2470 pin LCD funcAtiFon A used used used T DR LCDVD[23] - - - - - - AFT LCDVD[22] - - - - - - LCDVD[21] - - - - - - LCDVD[20] - - - - - - LCDVD[19] - - - - - - LCDVD[18] - - - - - - LCDVD[17] - - - - - - LCDVD[16] - - - - - - LCDVD[15] - - P1[29][4] LD[7] P1[29][4] LD[7] LCDVD[14] - - P1[28][4] LD[6] P1[28][4] LD[6] LCDVD[13] - - P1[27][4] LD[5] P1[27][4] LD[5] LCDVD[12] - P1[26][4] LD[4] P1[26][4] LD[4] LCDVD[11] P4[29][3] LD[3] P1[25][4] LD[3] P1[25][4] LD[3] LCDVD[10] P4[28][3] LD[2] P1[24][4] LD[2] P1[24][4] LD[2] LCDVD[9] P2[13][2] LD[1] P1[23][4] LD[1] P1[23][4] LD[1] LCDVD[8] P2[12][2] LD[0] P1[22][4] LD[0] P1[22][4] LD[0] LCDVD[7] - - P1[21][4] UD[7] P1[21][4] UD[7] LCDVD[6] - - P1[20][4] UD[6] P1[20][4] UD[6] LCDVD[5] - - P2[13][2] UD[5] P2[13][2] UD[5] LCDVD[4] - - P2[12][2] UD[4] P2[12][2] UD[4] LCDVD[3] P2[9][1] UD[3] P2[9][1] UD[3] P2[9][1] UD[3] LCDVD[2] P2[8][1] UD[2] P2[8][1] UD[2] P2[8][1] UD[2] LCDVD[1] P2[7][1] UD[1] P2[7][1] UD[1] P2[7][1] UD[1] LCDVD[0] P2[6][1] UD[0] P2[6][1] UD[0] P2[6][1] UD[0] LCDLP P2[5][1] LCDLP P2[5][1] LCDLP P2[5][1] LCDLP LCDENAB/ P2[4][1] LCDENAB/ P2[4][1] LCDENAB/ P2[4][1] LCDENAB/ LCDM LCDM LCDM LCDM LCDFP P2[3][1] LCDFP P2[3][1] LCDFP P2[3][1] LCDFP LCDDCLK P2[2][1] LCDDCLK P2[2][1] LCDDCLK P2[2][1] LCDDCLK LCDLE P2[1][1] LCDLE P2[1][1] LCDLE P2[1][1] LCDLE LCDPWR P2[0][1] LCDPWR P2[0][1] LCDPWR P2[0][1] LCDPWR LCDCLKIN P2[11][2] LCDCLKIN P2[11][2] LCDCLKIN P2[11][2] LCDCLKIN [1] ETM replaced with LCD pins. [2] External interrupt pins EINT1, EINT2, EINT3 replaced with LCD pins. [3] Timer pins MAT2[0] and MAT2[1] replaced with LCD pins. [4] USB OTG pins replaced by LCD pins. Preliminary data sheet Rev. 01.01 — 24 September 2009 68 of 83,

DR

TDTDTDTable 16. LCD panel connections for TFT panels RA RF AF External TFT 12 bit (4:4:4 mode) TFT 16 bit (5:6:5 mode) TFT 16 bit (1:5:5:5 mode) TFT 24 bitTDTDpin RA RF A LPC2470 LCD LPC2470 LCD LPC2470 pin LCD LPC2470 LCDTDpin used function pin used function used function pin used function RAF LCDVD[23] P1[29][4] BLUE3 P1[29][4] BLUE4 P1[29][4] BLUE4 P1[29][4] BLUE7 T LCDVD[22] P1[28][4] BLUE2 P1[28][4] BLUE3 P1[28][4] BLUE3 P1[28][4] BLUE6 LCDVD[21] P1[27][4] BLUE1 P1[27][4] BLUE2 P1[27][4] BLUE2 P1[27][4] BLUE5 LCDVD[20] P1[26][4] BLUE0 P1[26][4] BLUE1 P1[26][4] BLUE1 P1[26][4] BLUE4 LCDVD[19] - - P2[13][2] BLUE0 P2[13][2] BLUE0 P2[13][2] BLUE3 LCDVD[18] - - - - P2[12][2] intensity P2[12][2] BLUE2 LCDVD[17] - - - - - - P0[9][5] BLUE1 LCDVD[16] - - - - - - P0[8][5] BLUE0 LCDVD[15] P1[25][4] GREEN3 P1[25][4] GREEN5 P1[25][4] GREEN4 P1[25][4] GREEN7 LCDVD[14] P1[24][4] GREEN2 P1[24][4] GREEN4 P1[24][4] GREEN3 P1[24][4] GREEN6 LCDVD[13] P1[23][4] GREEN1 P1[23][4] GREEN3 P1[23][4] GREEN2 P1[23][4] GREEN5 LCDVD[12] P1[22][4] GREEN0 P1[22][4] GREEN2 P1[22][4] GREEN1 P1[22][4] GREEN4 LCDVD[11] - - P1[21][4] GREEN1 P1[21][4] GREEN0 P1[21][4] GREEN3 LCDVD[10] - - P1[20][4] GREEN0 P1[20][4] intensity P1[20][4] GREEN2 LCDVD[9] - - - - - - P0[7][5] GREEN1 LCDVD[8] - - - - - - P0[6][5] GREEN0 LCDVD[7] P2[9][1] RED3 P2[9][1] RED4 P2[9][1] RED4 P2[9][1] RED7 LCDVD[6] P2[8][1] RED2 P2[8][1] RED3 P2[8][1] RED3 P2[8][1] RED6 LCDVD[5] P2[7][1] RED1 P2[7][1] RED2 P2[7][1] RED2 P2[7][1] RED5 LCDVD[4] P2[6][1] RED0 P2[6][1] RED1 P2[6][1] RED1 P2[6][1] RED4 LCDVD[3] - - P2[12][2] RED0 P4[29][3] RED0 P4[29][3] RED3 LCDVD[2] - - - - P4[28][3] intensity P4[28][3] RED2 LCDVD[1] - - - - - - P0[5][5] RED1 LCDVD[0] - - - - - - P0[4][5] RED0 LCDLP P2[5][1] LCDLP P2[5][1] LCDLP P2[5][1] LCDLP P2[5][1] LCDLP LCDENAB/ P2[4][1] LCDENAB/ P2[4][1] LCDENAB/ P2[4][1] LCDENAB/ P2[4][1] LCDENAB/L LCDM LCDM LCDM LCDM CDM LCDFP P2[3][1] LCDFP P2[3][1] LCDFP P2[3][1] LCDFP P2[3][1] LCDFP LCDDCLK P2[2][1] LCDDCLK P2[2][1] LCDDCLK P2[2][1] LCDDCLK P2[2][1] LCDDCLK LCDLE P2[1][1] LCDLE P2[1][1] LCDLE P2[1][1] LCDLE P2[1][1] LCDLE LCDPWR P2[0][1] LCDPWR P2[0][1] LCDPWR P2[0][1] LCDPWR P2[0][1] LCDPWR LCDCLKIN P2[11][2] LCDCLKIN P2[11][2] LCDCLKIN P2[11][2] LCDCLKIN P2[11][2] LCDCLKIN [1] ETM replaced with LCD pins. [2] External interrupt pins EINT1, EINT2, EINT3 replaced with LCD pins. [3] Timer pins MAT2[0] and MAT2[1] replaced with LCD pins. [4] USB OTG pins replaced with LCD pins. [5] I2S pins replaced with LCD pins. Preliminary data sheet Rev. 01.01 — 24 September 2009 69 of 83,

DR

11.2 Suggested USB interface solutions DR DA R

D

F ATFDTRDA RF AVDD(3V3) T DRAFT USB_UP_LED USB_CONNECT LPC24XX soft-connect switch R1 1.5 kΩ

VBUS

USB_D+ RS = 33 Ω USB-B connector USB_D− RS = 33 Ω VSSIO, VSSCORE 002aad587 Fig 19. LPC2470 USB interface on a self-powered device VDD(3V3) R2 LPC24XX R1 USB_UP_LED 1.5 kΩ

VBUS

USB_D+ RS = 33 Ω USB-B connector USB_D− RS = 33 Ω VSSIO, VSSCORE 002aad588 Fig 20. LPC2470 USB interface on a bus-powered device Preliminary data sheet Rev. 01.01 — 24 September 2009 70 of 83,

DR T D T D TR R DAF A

VDD T

F DTRDA RF A

R1 R2 R3 R4 T DRA RSTOUT RESET_N VBUS FT ADR/PSW ID V OE_N/INT_N DP 33 ΩDD Mini-AB

SPEED

DM 33 Ω connector SUSPEND ISP1302 R4 R5 R6 VSSIO, USB_SCL1 SCL VSSCORE USB_SDA1 SDA USB_INT1 INT_N USB_D+1 USB_D−1

VDD

USB_UP_LED1 R7 LPC24XX5VVDD

IN OUTA

USB_PPWR2 LM3526-LENA FLAGA USB_OVRCR2 USB_PWRD2 VBUS USB_D+2 33 Ω D+ USB-A USB_D−2 33 Ω D− connector

V

15 kΩ 15 kΩ SSIO,

VSSCORE VDD

USB_UP_LED2 R8 002aad589

Fig 21. LPC2470 USB OTG port configuration: USB port 1 OTG dual-role device, USB port 2 host

Preliminary data sheet Rev. 01.01 — 24 September 2009 71 of 83,

DR T D T T R D DA RF A

VDD T

F DTRDA RF A

RSTOUT RESET_N T DR USB_TX_E1 OE_N/INT_N AFT USB_TX_DP1 DAT_VP USB_TX_DM1 SE0_VM USB_RCV1 RCV USB_RX_DP1 VP VBUS USB_RX_DM1 VM ID VDD DP 33 Ω USB MINI-AB ISP1302 connector DM 33 Ω LPC24XX ADR/PSW VSSIO, SPEED VSSCORE

SUSPEND

USB_SCL1 SCL USB_SDA1 SDA USB_INT1 INT_N

VDD

USB_UP_LED1 002aad590

Fig 22. LPC2470 USB OTG port configuration: VP_VM mode

Preliminary data sheet Rev. 01.01 — 24 September 2009 72 of 83,

DR TDTTRDA R D F AT FVDDDTD

USB_UP_LED1RRVAASSIO, F VSSCORETDUSB_D+1 33 Ω D+

RAFT

USB_D−1 33 Ω D− USB-A 15 kΩ 15 kΩ connector

VDD

USB_PWRD1 VBUS USB_OVRCR1 USB_PPWR1 ENA FLAGA5VOUTALM3526-L

IN

LPC24XX

VDD

USB_UP_LED2

VDD

USB_CONNECT2 VSSIO,

VSSCORE

USB_D+2 33 Ω D+ 33 Ω USB-BUSB_D−2 D− connector VBUS VBUS 002aad595

Fig 23. LPC2470 USB OTG port configuration: USB port 2 device, USB port 1 host

Preliminary data sheet Rev. 01.01 — 24 September 2009 73 of 83,

DR

TDTTRDA R

D

F AF VDDTDTDUSB_UP_LED1 RA RF AVSSIO, T VSSCORE DR USB_D+1 33 Ω D+ AFT USB_D−1 33 Ω D− USB-A 15 kΩ 15 kΩ connector

VDD

USB_PWRD1 VBUS USB_OVRCR1 USB_PPWR1 ENA FLAGA5VOUTA VDD

IN

LM3526-L OUTB LPC24XX USB_PPWR2 ENB FLAGB USB_OVRCR2 USB_PWRD2 VBUS USB_D+2 33 Ω D+ USB-A connector USB_D−2 33 Ω D− 15 kΩ 15 kΩ VSSIO,

VSSCORE VDD

USB_UP_LED2 002aad596 Fig 24. LPC2470 USB OTG port configuration: USB port 1 host, USB port 2 host 11.3 XTAL1 input The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a clock in slave mode, it is recommended that the input be coupled through a capacitor with Ci = 100 pF. To limit the input voltage to the specified range, choose an additional capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave mode, a minimum of 200 mVrms is needed. For more details see the LPC24xx User manual UM10237. Preliminary data sheet Rev. 01.01 — 24 September 2009 74 of 83,

DR

TTDTDR DA RF ATFDTRDA RA LPC2xxx FT DRAF XTAL1 T Ci Cg 100 pF 002aae718 Fig 25. Slave mode operation of the on-chip oscillator 11.4 XTAL and RTC Printed Circuit Board (PCB) layout guidelines The crystal should be connected on the PCB as close as possible to the oscillator input and output pins of the chip. Take care that the load capacitors Cx1 and Cx2, and Cx3 in case of third overtone crystal usage, have a common ground plane. The external components must also be connected to the ground plain. Loops must be made as small as possible, in order to keep the noise coupled in via the PCB as small as possible. Also parasitics should stay as small as possible. Values of Cx1 and Cx2 should be chosen smaller accordingly to the increase in parasitics of the PCB layout. 11.5 Suggested boot memory interface solutions ‘a_m’ and ‘a_b’ in the following figures refer to the highest order address line of the memory chip and the highest order microcontroller’s address line used respectively. CS1

OE

CE CE OE OE WE WE BLS1 8-bit BLS0 8-bit MEMORY MEMORY IO[7:0] IO[7:0] D[15:8] D[7:0] A[a_m:0] A[a_m:0] A[a_b:1] 002aad322 Fig 26. Booting from two 8-bit memory chips Preliminary data sheet Rev. 01.01 — 24 September 2009 75 of 83,

DR

TDTDTRA R

D A

CS1 FTFDTRDOE A RA WE CE OE RA WE FT

UB

BLS1 16-bit LB MEMORY BLS0 IO[15:0] D[15:0] A[a_m:0] A[a_b:1] 002aad323 Fig 27. Booting from a single 16-bit memory chip Preliminary data sheet Rev. 01.01 — 24 September 2009 76 of 83,

DR T

12. Package outline D

T R D T R DAF ATFDT

R DA RF A

LQFP208; plastic low profile quad flat package; 208 leads; body 28 x 28 x 1.4 mm SOT459T- 1DRAFT

c y

X A

157 104

ZE

e E HE A A2 A (A 3 )1wMθbp Lp

L

pin 1 index detail X 208 53 1 52wMZvMAeb

D

pDBHDvMB0510 mm scale DIMENSIONS (mm are the original dimensions)

A

UNIT A1 A2AbcD(1)3 p E(1) e HD HE L LpvwyZD Z θmax. E mm 0.15 1.45 0.27 0.20 28.1 28.1 30.15 30.15 0.75 1.43 1.43 o 1.6 0.25 1 0.12 0.08 0.08 7 0.05 1.35 0.17 0.09 27.9 27.9 0.5 29.85 29.85 0.45 1.08 1.08 0o Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION ISSUE DATE IEC JEDEC JEITA PROJECTION SOT459-1 136E30 MS-026 00-02-06 03-02-20

Fig 28. Package outline SOT459-1 (LQFP208)

Preliminary data sheet Rev. 01.01 — 24 September 2009 77 of 83,

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TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 15 x 15 x 0.7 mm SOT950T- 1DRAFTDBAball A1 index area

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ball A11357911 13 15 17 index area246810 12 14 16X0510 mm scale DIMENSIONS (mm are the original dimensions) UNIT Amax A1 A2bDEee1 e2vwyy1 mm 1.2 0.4 0.8 0.5 15.1 15.10.3 0.6 14.9 14.9 0.8 12.8 12.8 0.15 0.08 0.12 0.10.4 OUTLINE REFERENCES EUROPEAN ISSUE DATE VERSION IEC JEDEC JEITA PROJECTION 06-06-01 SOT950-1 - - - 06-06-14

Fig 29. Package outline SOT950-1 (TFBGA208)

Preliminary data sheet Rev. 01.01 — 24 September 2009 78 of 83,

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13. Abbreviations D

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F ATFDTDTable 17. Acronym list RA RF A Acronym Description T DR ADC Analog-to-Digital Converter AFT AHB Advanced High-performance Bus AMBA Advanced Microcontroller Bus Architecture APB Advanced Peripheral Bus BLS Byte Lane Select BOD BrownOut Detection CAN Controller Area Network DAC Digital-to-Analog Converter DCC Debug Communication Channel DMA Direct Memory Access EOP End Of Packet ETM Embedded Trace Macrocell GPIO General Purpose Input/Output IrDA Infrared Data Association JTAG Joint Test Action Group LCD Liquid Crystal Display MII Media Independent Interface MIIM Media Independent Interface Management OHCI Open Host Controller Interface OTG On-The-Go PHY Physical Layer PLL Phase-Locked Loop POR Power-On Reset PWM Pulse Width Modulator RMII Reduced Media Independent Interface SD/MMC Secure Digital/MultiMediaCard SE0 Single Ended Zero SPI Serial Peripheral Interface SSI Synchronous Serial Interface SSP Synchronous Serial Port TTL Transistor-Transistor Logic UART Universal Asynchronous Receiver/Transmitter USB Universal Serial Bus Preliminary data sheet Rev. 01.01 — 24 September 2009 79 of 83,

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14. Revision history DR DR DAF ATFDTDTable 18. Revision history RA RF A Document ID Release date Data sheet status Change notice Supersedes T DR LPC2470_1.01 Preliminary data sheet - LPC2470_1 AFT Modifications: • Table 6: Changed ESD min/max to −2500/+2500. • Table 7: Updated conditions and typical values for IDD(DCDC)act(3V3). • Table 7: Updated Table note 12. • Table 7: Updated min, typical and max values for oscillator pins. • Added deep power-down mode information. • Added Section 11.3 “XTAL1 input”. • Figure 21: Changed ISP1301 to ISP1302. • Figure 22: Changed ISP1301 to ISP1302. • Section 7.26.3 “Brownout detection”: Changed VDD(3V3) to VDD(DCDC)(3V3). LPC2470_1 20081027 Preliminary data sheet - - Preliminary data sheet Rev. 01.01 — 24 September 2009 80 of 83,

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15. Legal information DR D DA RF ATFDTRDR 15.1 Data sheet status AF AT D

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Document status[1][2] Product status[3] Definition AFT Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. 15.2 Definitions to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and Draft — The document is a draft version only. The content is still under therefore such inclusion and/or use is at the customer’s own risk. internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any Applications — Applications that are described herein for any of these representations or warranties as to the accuracy or completeness of products are for illustrative purposes only. NXP Semiconductors makes no information included herein and shall have no liability for the consequences of representation or warranty that such applications will be suitable for the use of such information. specified use without further testing or modification. Short data sheet — A short data sheet is an extract from a full data sheet Limiting values — Stress above one or more limiting values (as defined in with the same product type number(s) and title. A short data sheet is intended the Absolute Maximum Ratings System of IEC 60134) may cause permanent for quick reference only and should not be relied upon to contain detailed and damage to the device. Limiting values are stress ratings only and operation of full information. For detailed and full information see the relevant full data the device at these or any other conditions above those given in the sheet, which is available on request via the local NXP Semiconductors sales Characteristics sections of this document is not implied. Exposure to limiting office. In case of any inconsistency or conflict with the short data sheet, the values for extended periods may affect device reliability. full data sheet shall prevail. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published 15.3 Disclaimers at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of General — Information in this document is believed to be accurate and any inconsistency or conflict between information in this document and such reliable. However, NXP Semiconductors does not give any representations or terms and conditions, the latter will prevail. warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such No offer to sell or license — Nothing in this document may be interpreted or information. construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or Right to make changes — NXP Semiconductors reserves the right to make other industrial or intellectual property rights. changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior 15.4 Trademarks to the publication hereof. Notice: All referenced brands, product names, service names and trademarks Suitability for use — NXP Semiconductors products are not designed, are the property of their respective owners. authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or I2C-bus — logo is a trademark of NXP B.V. malfunction of an NXP Semiconductors product can reasonably be expected 16. Contact information

For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: email is hidden

Preliminary data sheet Rev. 01.01 — 24 September 2009 81 of 83,

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17. Contents DR DA R

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F ATFDTD1General description .1 7.22 Pulse width modulator ..R .A .40 RA 2 Features .1 7.22.1 Features.F.T D40 3 Applications .3 7.23 Watchdog timer .4R1AF 4 Ordering information.3 7.23.1 Features.41 T7.24 RTC and battery RAM .41 4.1 Ordering options .3 7.24.1 Features.42 5 Block diagram .4 7.25 Clocking and power control .42 6 Pinning information.5 7.25.1 Crystal oscillators.42 6.1 Pinning .5 7.25.1.1 Internal RC oscillator .42 6.2 Pin description .9 7.25.1.2 Main oscillator .42 7 Functional description .25 7.25.1.3 RTC oscillator .43 7.1 Architectural overview .25 7.25.2 PLL.43 7.2 On-chip SRAM .26 7.25.3 Wake-up timer .43 7.3 Memory map.26 7.25.4 Power control .44 7.4 Interrupt controller .28 7.25.4.1 Idle mode .44 7.4.1 Interrupt sources.29 7.25.4.2 Sleep mode .44 7.5 Pin connect block .29 7.25.4.3 Power-down mode .44 7.6 External memory controller.29 7.25.4.4 Deep power-down mode .45 7.6.1 Features .29 7.25.4.5 Power domains .45 7.7 General purpose DMA controller .30 7.26 System control .45 7.7.1 Features .30 7.26.1 Reset .45 7.8 Fast general purpose parallel I/O .31 7.26.2 Boot process .46 7.8.1 Features .31 7.26.3 Brownout detection .46 7.9 LCD controller.32 7.26.4 AHB .46 7.9.1 Features .32 7.26.5 External interrupt inputs .47 7.10 Ethernet .32 7.26.6 Memory mapping control .47 7.10.1 Features .33 7.27 Emulation and debugging .47 7.11 USB interface .34 7.27.1 EmbeddedICE .47 7.11.1 USB device controller .34 7.27.2 Embedded trace.47 7.11.1.1 Features .34 7.27.3 RealMonitor .48 7.11.2 USB host controller.34 8 Limiting values .49 7.11.2.1 Features .34 9 Static characteristics .50 7.11.3 USB OTG controller .35 9.1 Power consumption static characteristics .53 7.11.3.1 Features .35 9.1.1 Deep power-down mode .53 7.12 CAN controller and acceptance filters .35 9.1.2 Power-down mode .55 7.12.1 Features .35 9.2 ADC static characteristics .57 7.13 10-bit ADC .36 10 Dynamic characteristics.60 7.13.1 Features .36 10.1 Timing .64 7.14 10-bit DAC .36 7.14.1 Features .36 11 Application information .67 7.15 UARTs.36 11.1 LCD panel signal usage.67 7.15.1 Features .36 11.2 Suggested USB interface solutions .70 7.16 SPI serial I/O controller.37 11.3 XTAL1 input .74 7.16.1 Features .37 11.4 XTAL and RTC Printed Circuit Board (PCB) layout 7.17 SSP serial I/O controller .37 guidelines.75 7.17.1 Features .37 11.5 Suggested boot memory interface solutions . 75 7.18 SD/MMC card interface .37 12 Package outline.77 7.18.1 Features .37 13 Abbreviations .79 7.19 I2C-bus serial I/O controller .38 14 Revision history .80 7.19.1 Features .38 7.20 I2S-bus serial I/O controllers.38 7.20.1 Features .39 7.21 General purpose 32-bit timers/external event counters .39 7.21.1 Features .39 Preliminary data sheet Rev. 01.01 — 24 September 2009 82 of 83,

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15 Legal information.81 DR DR DA A 15.1 Data sheet status .81 FT FT 15.2 Definitions.81DRDR 15.3 Disclaimers .81 AF A 15.4 Trademarks.81 T DR 16 Contact information.81 AF 17 Contents .82 T Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: email is hidden Date of release: 24 September 2009 Document identifier: LPC2470_1.01]

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