Download: INTEGRATED CIRCUITS DATA SHEET TDA8501 PAL/NTSC encoder Preliminary specification April 1993 File under Integrated Circuits, IC02

INTEGRATED CIRCUITS

DATA SHEET TDA8501 PAL/NTSC encoder

Preliminary specification April 1993 File under Integrated Circuits, IC02, FEATURES GENERAL DESCRIPTION • Two input stages: R, G, B and −(R−Y), −(B−Y), Y with The TDA8501 is a highly integrated PAL/NTSC encoder IC multiplexing which is designed for use in all applications where R, G • Chrominance processing, highly integrated, includes and B or Y, U and V signals require transformation to PAL low frequency filters for the colour difference signals, or NTSC values.The specification of the input signals are and after the modulator a bandpass filter fully compatible with the specification of those of the TDA8505 SECAM-encoder. • Fully controlled modulator produces a signal according to the PAL or NTSC standard without adjustments • A free running oscillator. Can be tuned by crystal or by an external frequency source • Output stages with separated Y + SYNC and chrominance (Y + C, SVHS), and a CVBS output. Signal amplitudes are correct for 75 Ω driving via an external emitter follower. Internal generation of NTSC setup • Sync separator circuit and pulse shaper, to generate the required pulses for the processing, clamping, blanking, FH/2, and burst pulse • H/2 control pin. In PAL mode the internally generated H/2 is connected to this pin and the phase of this signal can be reset • Internal bandgap reference. ORDERING INFORMATION EXTENDED TYPE PACKAGE NUMBER PINS PIN POSITION MATERIAL CODE TDA8501 24 DIL plastic SOT234AH2(1) TDA8501T 24 SO plastic SOT137AH1(2) Note 1. SOT234-1; 1996 December 2. 2. SOT137-1; 1996 December 2. April 1993 2, April 1993 3 Fig.1 Block diagram., Fig.2 Pin configuration.

PINNING

U and V respectively, are the terms used to describe the colour difference signals at the output of the matrix. SYMBOL PIN DESCRIPTION −(R−Y) 1 colour difference input signal, for EBU bar (75%) 1.05 V (p-p) MCONTROL 2 multiplexer switch control input; HIGH = RGB, LOW = −(R−Y), −(B−Y), Y −(B−Y) 3 colour difference input signal, for EBU bar (75%) 1.33 V (p-p) H/2 4 line pulse input/output divided-by-2 for synchronizing the internal H/2, if not used, this pin dependent on mode selected, is either left open-circuit, or connected to VCC or to ground (note 1) Y 5 luminance input signal1Vnominal without sync U OFFSET6Umodulator offset control capacitorR7RED input signal for EBU bar of 75% 0.7 V (p-p) VCC 8 supply voltage; 5 V nominalG9GREEN input signal for EBU bar of 75% 0.7 V (p-p) VSS 10 ground (0 V) B 11 BLUE input signal for EBU bar of 75% 0.7 V (p-p) V OFFSET 12 V modulator offset control capacitor VREF 13 2.5 V internal reference voltage output CHROMA 14 chrominance output FLT 15 filter tuning loop capacitor CVBS 16 composite PAL or NTSC output, 2 V (p-p) nominal April 1993 4, SYMBOL PIN DESCRIPTION PAL/NTSC and 17 four level control pin (note 2) Y/Y + SYNC NOTCH 18 Y +SYNC output via an internal resistor of 2 kΩ; a notch filter can be connected to this pin Y +SYNC OUT 192V(p-p) nominal Y +SYNC output Y +SYNC IN 20 Y +SYNC input; (from pin 22) connected to the output of the external delay line BURST ADJ 21 burst current adjustment via external resistor Y +SYNC OUT 22 Y +SYNC output1V(p-p) nominal, connected to the input of the external delay line OSC 23 oscillator tuning: connected to either a crystal in series with capacitor to ground, or to an external frequency source via a resistor in series with a capacitor CS 24 composite sync input, 0.3 V (p-p) nominal Notes 1. Pin 4: in PAL mode, if not connected to external H2 pulse, this pin is the output for the internally generated H/2 signal. Pin 4: in NTSC mode, for internal set-up this pin is connected to ground; when internal set-up is switched off, this pin is connected to VCC. 2. The listed voltages connected to pin 17 (if VCC = + 5 V) enable the following Y (via pin 5) input signal states: 0 V = PAL mode; at pin 5, Y without sync and input blanking on5V= NTSC mode; at pin 5, Y without sync and input blanking on 1.8 V = PAL mode; at pin 5, Y with sync and input blanking off 3.2 V = NTSC mode; at pin 5, Y with sync and input blanking off April 1993 5, FUNCTIONAL DESCRIPTION The Y input signal (via pin 5) differs from other signal inputs, in that the timing of the internal clamp is after the The TDA8501 device comprises: sync period. • encoder circuit The amplitude and polarity of these colour difference and • oscillator and filter control luminance input signals are processed to provide suitable • sync separator and pulse shaper. switch inputs of U, V and Y signal values. Within this functional description, the term Y is used to The condition for 75% colour bar is: describe the luminance signal and the terms U and V respectively, are used to describe the colour difference signals. pin 1 −(R−Y) = 1.05 V (peak-to-peak) Encoder circuit pin 3 −(B−Y) = 1.33 V (peak-to-peak) pin5Y= 1 V (peak-to-peak) without sync INPUT STAGE The input stage of the device uses two signal paths (see When selected (via MCONTROL), the U and V signals (via Fig.1). Fast switching between the two signal paths is the switch) are routed to the low pass filters. The Y signal achieved by means of the signal path selection switch (via the switch) is routed via the adder and buffer to pin 22 MCONTROL (pin 2). (Y +SYNC OUT to delay line). Dependent on pin 17 conditioning, the Y signal may have external or internal R, B AND G INPUT SIGNALS PATH sync added (see section Four level control pin). One signal path provides the connection for R, G and B signal inputs (via pins 7, 9 and 11) which are connected to FOUR LEVEL CONTROL PIN a matrix via clamping and line blanking circuits. The signal The Y input signal (via pin 5) is conditioned by use of the outputs from the matrix are U, V and Y. 4-level control pin (pin 17) to emulate either the PAL or For an EBU colour bar of 75% the amplitude of the signal NTSC modes, with sync and input blanking off or without must be 0.7 V (peak-to-peak): sync and input blanking on. Pin 17 may be hard wire connected to either ground (LOW for PAL mode) or VCC (HIGH for NTSC mode). External U = 0.493 (B−Y) resistors can further modify the voltage level input at pin 17 V = 0.877 (R−Y) to condition (pin 5) Y with sync and input blanking off or Y without sync and input blanking on. (see section Y = 0.299 R +0.587 G +0.114 B PAL/NTSC and Y/Y +SYNC). When selected (via MCONTROL), the U, V signals from U AND V SIGNALS the matrix are routed through the selection switch to the In PAL and NTSC modes the U and V (colour difference) low pass filters. The Y signal from the matrix is routed signals at the output of the switch are configured differently through the selection switch to the adder and combined as follows: with the sync pulse from the sync separator and then connected via a buffer internally to pin 22 (Y + SYNC OUT PAL mode: to delay line). • after the adding of the burst pulse to U and V, these signals are connected to the input of the low pass filters. −(R−Y), −(B−Y) AND Y INPUT SIGNALS PATH During the vertical sync period the burst pulse is A second signal path provides the connection for negative suppressed. colour difference signal inputs −(R−Y), −(B−Y) i.e. V, U (via NTSC mode: pins 1, 3) and luminance Y (via pin 5), which are routed directly to the switch inputs via clamping and line blanking • the burst pulse is only added to U and the gain of the U circuits. and V signals is 0.95 of the gain in PAL mode. During the vertical sync period the burst pulse is suppressed. April 1993 6, Low pass filters The −3dB nominal frequency response level of the low pass filters are different in PAL and NTSC modes. PAL mode: bandwidth = 1.35 MHz nominal (see Fig.3). NTSC mode: bandwidth = 1.1 MHz nominal (see Fig.4). The signal outputs of the low pass filters are connected to the signal inputs of the U and V modulators. U AND V MODULATORS Two four-quadrant multipliers are used for quadrature amplitude modulation of the U and V signals. The level of harmonics produced by the modulated signals are minimal, because of real multiplication with sinewave carriers. The unbalance of the modulators is minimized by means (1) frequency response. of a control loop and two external capacitors, pin 6 for the (2) group delay. U modulator and pin 12 for the V modulator. The timing of the control loop is triggered by the H/2 pulse, so that during one sync period the U control is active and during the next Fig.3 Low pass filter response for colour sync period the V control is active. In this way, when U and difference signals (PAL mode). V are both zero, the suppressed carrier is guaranteed to be at a low level. The internal oscillator circuit generates two sinewave carriers (0 degree and 90 degree). The '0 degree' (0) carrier is connected to the U modulator and the '90 degree' (1) carrier is connected to the V modulator. PAL mode: • switched sequentially by the H/2 pulse, the V signal is modulated alternately with the direct and inverse carrier. • the internal H/2 pulse can be forced into a specific phase by means of an external pulse connected to pin 4 (H/2). Forcing is active at HIGH level. If not used pin 4 can be left open-circuit or connected to ground. If pin 4 is left open, the internally generated H/2 pulse (output) is connected to this pin. NTSC mode: • alternation of the V modulation is not allowed. If pin 4 is not used for set-up control (see Y +SYNC, CVBS and Chrominance outputs), it can be left open-circuit or connected to ground. (1) frequency response. (2) group delay. Fig.4 Low pass filter response for colour difference signals (NTSC mode). April 1993 7, CHROMINANCE BLANKING BANDPASS FILTER The signal outputs from the modulators are connected to A wide symmetrical bandpass filter is used so that a the signal input of the chrominance blanking circuit. To maximum performance of the chrominance for Y +C avoid signal distortion that may be caused by the control (SVHS) is guaranteed. This wide curve is possible loop, the signal outputs of the modulators are blanked because of the minimal signal level of the harmonics within during the sync period. This prevents signal distortion the modulators see Figs (PAL mode: 5 and 6); during the adding of the sync pulse at the CVBS output (NTSC mode: 7 and 8) which illustrate the nominal circuit. response for PAL and NTSC modes. (1) frequency response. (2) group delay. Fig.5 Band pass filter nominal frequency Fig.6 Band pass filter nominal frequency/group response (PAL mode). delay response (PAL mode). April 1993 8, Y +SYNC, CVBS AND CHROMINANCE OUTPUTS The Y signal from the matrix, or the Y signal from pin 5, (selected via the switch) is added with the composite sync signal of the sync separator (dependent on pin 17 conditioning). The output of the adder, nominal1V(peak-to-peak), is connected to pin 22 (see Fig.1). Pin 22 is connected to an external delay line. The delay line is necessary for correct timing of the Y + SYNC signal with the chrominance signal. The output resistor of the delay line is connected to VREF (pin 13). The output of the external delay line is connected to (input) pin 20. The Y +SYNC (delayed) input signal at pin 20 is amplified via a buffer to a level of2V(peak-to-peak) nominal and connected to pin 19 (Y + SYNC output). The Y + SYNC (delayed) input signal at pin 20 is also connected via an internal resistor of 2 kΩ to the input of the CVBS adder stage. After the internal resistor of 2 kΩ, and before the input of the CVBS adder, an external notch filter can be connected via pin 18. Fig.7 Band pass filter nominal frequency response (NTSC mode). The chrominance output of the bandpass filter is added with Y +SYNC signal via the CVBS adder. The CVBS (combined video and blanking signal) output of the adder is connected to pin 16 with a nominal amplitude of2V(peak-to-peak). The chrominance output of the bandpass filter is amplified via a buffer and connected to pin 14. The chrominance amplitude corresponds with the value of Y + SYNC signal output at pin 19. Together both outputs give the Y +C (SVHS) signals. BLACK AND BLANKING LEVELS IN PAL AND NTSC MODES PAL mode: Fig.9 illustrates the nominal Y + SYNC signal at pin 22, the difference between black and blanking level is 0 mV. NTSC mode: Fig.10 illustrates the nominal Y + SYNC signal at pin 22, the difference between black and blanking level is 53 mV. Because of the difference between the black and blanking level in the NTSC mode, there are two options for NTSC. (1) frequency response. (2) group delay. Fig.8 Band pass filter nominal frequency/group delay response (NTSC mode). April 1993 9, NTSC option with internal set-up generation Pin 4 connected to ground or left open-circuit. The set-up is generated internally and the input signals have the values already specified in section Input stage. The set-up is not suppressed during vertical sync. NTSC option without internal set-up generation Pin 4 connected to VCC. This option places some restrictions on the input signals as follows: • if the output signal must be according to the NTSC standard, the input signals must be generated with a specific set-up level • for R, G and B inputs a set-up level of 53 mV is required, therefore the specified amplitude must be 753 mV (peak-to-peak) instead of 700 mV (peak-to-peak) • for U, V and Y inputs a set-up level for Y of 76 mV is required, therefore the specified amplitude must be 1076 mV (peak-to-peak) (without sync) instead of1V(peak-to-peak). This option, combined with U, V and Y inputs, is not possible if V is < 4.75 V. Fig.9 Nominal Y + SYNC signal level at pin 22 CC (PAL mode). Fig.10 Nominal Y +SYNC signal level at pin 22 (NTSC mode). April 1993 10, Oscillator and Filter Control Sync separator and Pulse shaper The internal crystal oscillator is connected to pin 23 which The composite sync (CS) input at pin 24 (via the sync provides for the external connection of a crystal in series separator) together with a sawtooth generator provide the with a trimmer to ground. It is possible to connect an source for all pulses necessary for the processing. external signal source to pin 23, via a capacitor in series Pulses are used for: with a resistor. The signal shape is not important. Figure 11 shows the external components connected to • clamping pin 23 and the required conditions. The minimum AC • video blanking current of 50 µA must be determined by the resistors • H/2 (Rint and Rext) and the voltage of the signal source. For example, in this way an external sub-carrier, locked to the • chrominance blanking sync, can be used. • burst pulse generation for adding to U, V • pulses for the modulator offset control. The value of the sawtooth generator output (current) is PAL mode: frequency of the oscillator is determined by the value of a fixed resistor to ground which 4.433618 MHz. is connected externally at pin 21 (BURST ADJ). When NTSC mode: frequency of the oscillator is finer tolerance of the burst position is required, the fixed 3.579545 MHz. resistor is connected in series with a variable potentiometer to ground. By use of the potentiometer the The −3 dB of the low pass filters and the centre frequency burst position at the outputs can be finely adjusted, after of the bandpass filter are controlled by the filter control which the pulse width of the burst and the position and loop and directly coupled to the value of the frequency of pulse width of all other internal pulses are then the oscillator. The external capacitor of the control loop is determined. When using a fixed resistor with a tolerance of connected to pin 15. 2%, a tolerance of 10% of the burst position can be expected. Timing diagrams of the pulses are provided by Figs 12 and 13. H/2 at pin 4 is only necessary in the PAL mode when the internal H/2 pulse requires locking with an external H/2 phase (two or more encoders locked in same phase). The forcing of the internal H/2 to a desired phase is possible by means of an external pulse. Forcing is active at HIGH level. For the functioning of Pin 4 in the NTSC mode see also section Black and Blanking levels in PAL and NTSC modes. Fig.11 Tuning circuit for external signal source. April 1993 11, April 1993 12 Fig.12 Sync separator and pulse shaper pulses., April 1993 13 Fig.13 Sync separator and pulse shaper pulse timing levels., PAL/NTSC and Y/Y + SYNC Pin 17 is used as a four level control pin to condition the Y/Y + SYNC input signal (via pin 5). Pin 17 is normally connected to ground for PAL mode, or to VCC for the NTSC mode. By use of external resistors (potential divider connected to pin 17), the input blanking at pin 5 can be switched on and off. (see Table 1 and Fig 14). Table 1 PAL/NTSC Y/Y +SYNC pin 5 options (pin 17 connection configurations). MODE PIN 5 STATUS PIN 17 CONNECTION REQUIREMENT PAL Y without sync and input blanking on pin 17 LOW, connected to VSS NTSC Y without sync and input blanking on pin 17 HIGH, connected to VCC PAL Y with sync and input blanking off pin 17 with 39 kΩ connected to VCC and 22 kΩ connected to VSS NTSC Y with sync and input blanking off pin 17 with 22 kΩ connected to VCC and 39 kΩ connected to VSS LIMITING VALUES In accordance with the Absolute Maximum System (IEC134); all voltages referenced to VSS (pin 10). SYMBOL PARAMETER MIN. MAX. UNIT VCC positive supply voltage 0 5.5 V Tstg storage temperature −65 +150 °C Tamb operating ambient temperature −25 +70 °C THERMAL RESISTANCE SYMBOL PARAMETER THERMAL RESISTANCE Rth j-a from junction to ambient in free air SOT234 66 K/W SOT137 75 K/W DC CHARACTERISTICS VCC = 5 V; Tamb = 25 °C; all voltages referenced to ground (pin 10); unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply (pin 8) VCC supply voltage 4.5 5.0 5.5 V ICC supply current − 40 − mA Ptot total power dissipation − 200 − mW VREF reference voltage output (pin 13) 2.425 2.5 2.575 V April 1993 14, AC CHARACTERISTICS VCC = 5 V; Tamb = 25 °C; composite sync signal connected to pin 24; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Encoder circuit Input stage (pins 1, 3, 5, 7, 9 and 11); black level = clamping level maximum signal Vn(max) from black level positive − 1.2 − V Vn(min) from black level negative only pins 1, 3 and 5 − 0.9 − V Ibias input bias current VI = V13 − − < 1 µA VI input voltage clamped input capacitor tbf V13 tbf V connected to ground ZI input clamping impedance II = 1 mA − 80 − Ω IO = 1 mA − 80 − Ω matrix and gain tolerance of R, G − − < 5 % and B signals G gain tolerance of Y, −(R−Y) and − − < 5 % −(B−Y) MCONTROL (pin 2; note 1) VIL LOW level input voltage 0 − 0.4 V Y, −(R−Y) and −(B−Y) VIH HIGH level input voltage 1 − 5 V R, G and B II input current − − −3 µA tsw switching time − 50 − ns U modulator offset control (pin 6) V6 DC voltage control level − 2.5 − V ILI input leakage current − − 100 nA VLL limited level voltage LOW − 1.8 − V VHL limited level voltage HIGH − 3.2 − V V modulator offset control (pin 12) V12 DC voltage control level − 2.5 − V ILI input leakage current − − 100 nA VLL limited level voltage LOW − 1.8 − V VHL limited level voltage HIGH − 3.2 − V Y + SYNC (pin 22 out to delay circuit) RO output resistance − − < 25 Ω Isink maximum sink current 350 − − µA Isource maximum source current 1000 − − µA VBL black level output voltage − 2.5 − V April 1993 15, SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT PAL mode; pin 17 = 0 V VSYNC sync voltage amplitude 285 300 315 mV VY Y voltage amplitude 665 700 735 mV VDIF difference between black and − 0 − mV blanking level NTSC mode; pin 17 = 5 V and pin 4 open-circuit or ground VSYNC sync voltage amplitude 270 286 300 mV VY Y voltage amplitude 628 661 694 mV VDIF difference between black and − 53 − mV blanking level BW frequency response pin 22 with external 10 − − MHz load of R = 10 kΩ and C = 10 pF group delay tolerance − − 20 ns td sync delay from pin 24 to pin 22 220 290 360 ns td Y delay from pin 5 to pin 22 − 10 − ns α Chrominance cross talk 0 dB = 1330 mV − − −60 dB (peak-to-peak) = 75% RED Y + SYNC IN (pin 20 from delay circuit; note 2) Ibias input bias current − − 1 µA VI maximum voltage amplitude − − 1VY+ SYNC OUT (pin 19 output Y (SVHS); note 2) RO output resistance − 120 − Ω Isink maximum sink current 650 − − µA Isource maximum source current 1000 − − µA VBL black level output voltage − 1.65 − VGY+ SYNC gain; − 12 − dB from pin 20 to pin 19 BW frequency response pin 19 with external 10 − − MHz load of R = 10 kΩ and C = 10 pF group delay tolerance − − 20 ns α Chrominance cross talk 0 dB = 1330 mV − − −54 dB (peak-to-peak) = 75% RED April 1993 16, SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT NOTCH (pin 18) RO output resistance 1750 2000 2500 Ω VCC DC voltage level − 2.5 − V Isink maximum sink current 350 − − µA Chrominance output (pin 14) Isink maximum sink current 700 − − µA Isource maximum source current 1000 − − µA RO output resistance − 120 − Ω ∆VDC variation of DC voltage level − − 5 mV when chrominance signal is blanked and chrominance signal is not blanked PAL mode; pin 17 = 0 V VO chrominance output voltage 480 600 720 mV (peak-to-peak) amplitude burst ratio: chrominance 2.1 2.2 2.3 (75% RED)/burst NTSC mode; pin 17 = 5 V VO chrominance output voltage 460 570 680 mV (peak-to-peak) amplitude burst ratio: chrominance 2.1 2.2 2.3 (75% RED)/burst carrier suppression when 0 dB = 1330 mV − 37 − dB input-signals are0V(peak-to-peak) phase accuracy (difference − − 2 degrees between 0 and 90 degree carriers) LPF Low-pass filters see Figs 3 and 4 BPF Band-pass filters see Figs 5 and 6 Vn noise level (RMS value) − − 4 mV BP burst phase; 0 degrees = phase U carrier PAL mode − ±135 − degrees NTSC mode − 180 − degreesαY+ SYNC cross talk 0 dB = 1400 mV − − −60 dB (0 to 6 MHz) (peak-to-peak) April 1993 17, SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT CVBS output (pin 16) Isink maximum sink current 650 − − µA Isource maximum source current 1000 − − µA VO DC voltage level Y +SYNC = 0 − 1.6 − VGY+SYNC gain; − 12 − dB from pin 20 to pin 16 G chrominance difference; − 0 − dB from pin 14 to pin 16 Gø differential phase note 3 − − 3 degrees GV differential gain note 4 − − 3 dB RO output resistance − 120 − Ω Oscillator output (pin 23) OSC series-resonance the resonance resistance of the crystal should be < 60 Ω and the parallel capacitance of the crystal should be < 10 pF. Filter tuning loop (pin 15) VDC DC control voltage level NTSC − 0.83 − V VDC DC control voltage level PAL − 0.88 − V VDCL limited DC-level LOW IO = 200 µA − 0.27 − V VDCH limited DC-level HIGH II = 200 µA − 1.8 − V H2 (pin 4) VIL LOW level input voltage inactive 0 − 1 V VIH HIGH level input voltage active 4 − 5 V II current for forcing HIGH 220 − − µA IO current for forcing LOW 260 − − µA VO voltage out LOW − − < 0.5 V VO voltage out HIGH 4 − − V Isink maximum sink current 50 − − µA Isource maximum source current 50 − − µA Composite sync input (pin 24) VSYNC SYNC pulse amplitude 75 300 600 mV (p-p) slicing level − 50 − % II input current − 4 − µA IO maximum output current during − 100 − µA

SYNC

BURST ADJ (pin 21; note 5) BP DC voltage level − VREF − V (V13) April 1993 18, SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Control pin PAL/NTSC and Y/Y + SYNC (pin 17; note 6) VI PAL mode and blanking pin50− 1 V active internal sync added to Y VI PAL mode and blanking pin 5 1.6 − 2.0 V inactive internal sync not added to Y VI NTSC mode and blanking pin54− 5 V active internal sync added to Y VI NTSC mode and blanking pin53− 3.4 V inactive internal sync not added to Y Ibias input bias current − − −10 µA Notes 1. The threshold level of this pin is 700 mV ±20 mV. The specification of the HIGH and LOW levels is according to the SCART fast blanking. 2. Pin 20 condition: black level of input signal must be 2.5 V; amplitude 0.5 V (peak-to-peak) nominal. 3. Definition: maximum phase − minimum phase = difference phase maximum gain – minimum gain 4. Definition: - × 100 = difference gain % maximum gain 5. The output impedance of this pin is low (< 100 Ω). The nominal value of the external resistor is 196 kΩ (see also section Sync separator and Pulse shaper). 6. The threshold levels are: 0.25 times VCC, 0.5 times VCC and 0.75 times VCC. April 1993 19, Table 2 Internal circuitry. PIN NAME CIRCUIT DESCRIPTION 1 −(R−Y) −(R−Y) input; connected via 47 nF capacitor 1.05 V (p-p) for EBU bar of 75% see also pins 3, 5, 7, 9 and 11 2 MCONTROL multiplexer switch control input < 0.4 V Y, U and V >1 V R, G andB3−(B−Y) see pin 1 −(B−Y) input; connected via 47 nF capacitor 1.33 (p-p) for EBU bar of 75% 4 H/2 H/2 input IN/OUT PAL MODE: pin open, output of internal H/2 Forcing possibility NTSC mode: 0 V set-up5Vno set-up April 1993 20, PIN NAME CIRCUIT DESCRIPTION5Ysee pin1Yinput; connected via 47 nF capacitor1V(p-p) for EBU bar of 75% 6 U OFFSET 220 nF (low-leakage) connected to ground see also pin 127Rsee pin 1 RED input; connected via 47 nF capacitor 0.7 V (p-p) for EBU bar of 75% 8 VCC supply voltage5Vnominal9Gsee pin 1 GREEN input; connected via 47 nF capacitor 0.7 V (p-p) for EBU bar of 75% 10 VSS ground 11 B see pin 1 BLUE input; connected via 47 nF capacitor 0.7 V (p-p) for EBU bar of 75% April 1993 21, PIN NAME CIRCUIT DESCRIPTION 12 V OFFSET see pin 6 220 nF (low-leakage) connected to ground 13 VREF 2.5 V reference voltage decoupling with 47 µF and 22 nF capacitors 14 CHROMA chrominance output; together with pin 19 the Y + C (SVHS) output 15 FLT filter control pin 220 nF capacitor to ground April 1993 22, PIN NAME CIRCUIT DESCRIPTION 16 CBVS CVBS output 17 PAL/NTSC 4-level control pin Y/Y+SYNC Pin 5: 0 V PAL, Y 1.8 V PAL Y+SYNC 3.2 V NTSC Y +SYNC5VNTSC Y 18 NOTCH pin for external notch filter April 1993 23, PIN NAME CIRCUIT DESCRIPTION 19 Y+SYNC OUT output of the Y +SYNC signal; together with pin 14 the Y +C (SVHS) output 20 Y+SYNC IN input of the delayed Y+SYNC signal of the delay line black level must be 2.5 V 21 BURST ADJ external resistor to ground for adjusting the position of the burst April 1993 24, PIN NAME CIRCUIT DESCRIPTION 22 Y+SYNC OUT output of the Y+SYNC signal, connected to the delay line via a resistor 23 OSC subcarrier-crystal in series with a trimmer, or an external subcarrier signal, via 1 nF in series with a resistor 24 CS composite SYNC signal input amplitude < 600 mV (p-p) April 1993 25, April 1993 26 Fig.14 Application diagram.,

PACKAGE OUTLINES SDIP24: plastic shrink dual in-line package; 24 leads (400 mil) SOT234-1

D ME A2ALA1cZewM(e 1 ) b1

MH

b 24 13 pin 1 index

E

1 120510 mm scale DIMENSIONS (mm are the original dimensions) AA1A2(1)UNIT max. min. max. bbcD(1) E (1) Z1 e e1 L ME MH w max. mm 4.7 0.51 3.8 1.3 0.53 0.32 22.3 9.1 3.2 10.7 12.2 0.8 0.40 0.23 21.4 8.7 1.778 10.16 2.8 10.2 10.5 0.18 1.6 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION ISSUE DATE IEC JEDEC EIAJ PROJECTION 92-11-17 SOT234-1 95-02-04

April 1993 27

seating plane,

SO24: plastic small outline package; 24 leads; body width 7.5 mm SOT137-1

DEA

X

c y HEvMA

Z

24 13

Q

A2 A (A 3 )

A

pin 1 index θ Lp

L

1 12 detailXewMbp0510 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions)

A

UNIT (1) (1)max. A1 A2 A3 bpcDEeH(1) E L LpQvwyZθmm 2.65 0.30 2.45 0.49 0.32 15.6 7.6 10.65 1.1 1.1 0.9 0.10 2.25 0.25 0.36 0.23 15.2 7.4 1.27 10.00 1.4 0.4 1.0 0.25 0.25 0.1 0.4 8o 0o inches 0.10 0.012 0.096 0.019 0.013 0.61 0.30 0.419 0.043 0.043 0.035 0.004 0.089 0.01 0.014 0.009 0.60 0.29 0.050 0.394 0.055 0.016 0.039 0.01 0.01 0.004 0.016 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION ISSUE DATE IEC JEDEC EIAJ PROJECTION 95-01-24 SOT137-1 075E05 MS-013AD 97-05-22

April 1993 28

, SOLDERING Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary Introduction between 50 and 300 seconds depending on heating There is no soldering method that is ideal for all IC method. Typical reflow temperatures range from packages. Wave soldering is often preferred when 215 to 250 °C. through-hole and surface mounted components are mixed Preheating is necessary to dry the paste and evaporate on one printed-circuit board. However, wave soldering is the binding agent. Preheating duration: 45 minutes at not always suitable for surface mounted ICs, or for 45 °C. printed-circuits with high population densities. In these situations reflow soldering is often used. WAVE SOLDERING This text gives a very brief insight to a complex technology. Wave soldering techniques can be used for all SO A more in-depth account of soldering ICs can be found in packages if the following conditions are observed: our “IC Package Databook” (order code 9398 652 90011). • A double-wave (a turbulent wave with high upward SDIP pressure followed by a smooth laminar wave) soldering technique should be used. SOLDERING BY DIPPING OR BY WAVE • The longitudinal axis of the package footprint must be The maximum permissible temperature of the solder is parallel to the solder flow. 260 °C; solder at this temperature must not be in contact • The package footprint must incorporate solder thieves at with the joint for more than 5 seconds. The total contact the downstream end. time of successive solder waves must not exceed 5 seconds. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be The device may be mounted up to the seating plane, but applied by screen printing, pin transfer or syringe the temperature of the plastic body must not exceed the dispensing. The package can be soldered after the specified maximum storage temperature (Tstg max). If the adhesive is cured. printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the Maximum permissible solder temperature is 260 °C, and temperature within the permissible limit. maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 °C within REPAIRING SOLDERED JOINTS 6 seconds. Typical dwell time is 4 seconds at 250 °C. Apply a low voltage soldering iron (less than 24 V) to the A mildly-activated flux will eliminate the need for removal lead(s) of the package, below the seating plane or not of corrosive residues in most applications. more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 °C it may remain in REPAIRING SOLDERED JOINTS contact for up to 10 seconds. If the bit temperature is Fix the component by first soldering two diagonally- between 300 and 400 °C, contact may be up to 5 seconds. opposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact SO time must be limited to 10 seconds at up to 300 °C. When REFLOW SOLDERING using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between Reflow soldering techniques are suitable for all SO 270 and 320 °C. packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. April 1993 29,

DEFINITIONS

Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. April 1993 30]

15