Download: INTEGRATED CIRCUITS DATA SHEET TDA8505 SECAM encoder Preliminary specification July 1994 Supersedes data of May 1993 File under Integrated Circuits, IC02

INTEGRATED CIRCUITS DATA SHEET TDA8505 SECAM encoder Preliminary specification July 1994 Supersedes data of May 1993 File under Integrated Circuits, IC02 Philips Semiconductors FEATURES GENERAL DESCRIPTION • Two input stages, R, G, B and Y, −(R−Y), −(B−Y) with The TDA8505 is a highly integrated SECAM encoding IC multiplexing. that is designed for use in all applications that require • transformation of R, G and B signals or Y, U and V signalsChrominance processing, highly integrated, includes to a standard SECAM signal. vertical identification, low frequency pre-emphasis and high frequency pre...
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INTEGRATED CIRCUITS

DATA SHEET TDA8505 SECAM encoder

Preliminary specification July 1994 Supersedes data of May 1993 File under Integrated Circuits, IC02 Philips Semiconductors, FEATURES GENERAL DESCRIPTION • Two input stages, R, G, B and Y, −(R−Y), −(B−Y) with The TDA8505 is a highly integrated SECAM encoding IC multiplexing. that is designed for use in all applications that require • transformation of R, G and B signals or Y, U and V signalsChrominance processing, highly integrated, includes to a standard SECAM signal. vertical identification, low frequency pre-emphasis and high frequency pre-emphasis (anti-Cloche) and The specification of the input signals is fully compatible bandpass filter. with those of the TDA8501 PAL/NTSC encoder. • Fully controlled FM modulator which produces a signal in accordance with the SECAM standard without adjustments. • Two reference oscillators, one for D'R f0 (4.40625 MHz) and one for D'B f0 (4.250 MHz). These oscillators are tuned by PLL loop with the frequency of the line sync as reference. Crystal tuning, or tuning by external reference source, of the reference oscillators is possible. • Output stages, CVBS and separated Y + SYNC and CHROMA. For CVBS output, signal amplitude2V(p−p) nominal, thus only an external emitter follower is required for 75 Ω driving. • Sync separator circuit and pulse shaper, to generate the required pulses for the processing, line, frame, FH/2 and chrominance blanking. • A 3-level sandcastle pulse is generated for PAL/NTSC to SECAM transcoding. • FH/2 input for locking with another decoder. • Colour killing on the internal colour difference signals. • Internal bandgap reference. ORDERING INFORMATION

PACKAGE

TYPE NUMBER PINS PIN POSITION MATERIAL CODE TDA8505 32 SDIP32 plastic SOT232-1 July 1994 2,

BLOCK DIAGRAM July 1994 3

4.7 µF 2.2 kΩ 4.7 µF 1.2 kΩ LPF4.25 LPF 4.4 output 22 nF output 100 nF 31 24 V 8DDA 47 µF PHASE 282 4.406 MHz nF 10 SWITCH V DETECTOR DIVIDER VCOSSA VDDD 26 XTAL/PLL

VIDENT

100 nF 30 input

VSSD

composite 22 nF 29 SYNC PHASE 272 sync SEPARATOR DETECTOR DIVIDER 4.25 MHz 27 input VCO 270 pF VCO4.25 output colour killing 28 input 13 FH/2 input PULSE GENERATOR 1 nF 3.9 kΩ

PHASE

external power 19 DETECTOR 1 µF supply (Vext)

SANDCASTLE

sandcastle 20 output LPFDR output

TDA8505

6.8 100 Ω ADDER PHASE nF DETECTOR 470 nF control input 12 (Y/Y SYNC) FRAME LPFDB output IDENTI- multiplexer 2 FICATION Y+SYNC output control input 252V(p-p) RED 7 input CL/BL 47 650 DELAY nF LOW-PASSMATRIX FM ns LINE GREEN 9 FILTER

ADDER

MODULATOR 23SWITCH CLAMP GAIN BUFFER input CL/BL LF PRE- 47 SEQUENCE PHASE Y+SYNC EMPHASIS LIMITER Y+SYNC nF SWITCH 11 2 kΩ input BLUE1V(p p) input CL/BL 47 22 notch nF output CLOCHE BANDPASS V CHROMINANCE CL/BL CL/BL CL/BL ref FILTER ADDER

BLANKING

135617 14 16 18 21

V

47 47 47 ref

FADJ

4.7 220 nF nF nF TEST 1.8 kΩ kΩ nF chrominance CVBS2V(p p) nF FLT output output output (R Y) (B Y) luminance 47 input MLA951 - 3 colour difference µF reference 22 nF 22 kΩ inputs voltage output

Fig.1 Block diagram.

handbook, full pagewidth,

PINNING

D'R and D'B are the colour difference signals at the output of the multiplexer circuit; D'R = −1.9(R−Y) and D'B = +1.5(B−Y), for an EBU bar of 75% the amplitudes are equal. SYMBOL PIN DESCRIPTION −(R−Y) 1 colour difference input signal, for EBU bar of 75% 1.05 V (peak-to-peak value) MCONTR 2 multiplexer control; input HIGH = RGB, input LOW = −(R−Y), −(B−Y) and Y −(B−Y) 3 colour difference input signal, for EBU bar of 75% 1.33 V (peak-to-peak value) FH/2 4 line pulse input divided-by-2 for synchronizing two or more encoders; when not used this pin is connected to groundY5luminance input signal1Vnominal without sync TEST 6 test pin; must be connected to VCC (pin 8), or left open-circuitR7RED input signal for EBU bar of 75% 0.7 V (peak-to-peak value) VDDA 8 analog supply voltage for encoder part; 5 V nominalG9GREEN input signal for EBU bar of 75% 0.7 V (peak-to-peak value) VSSA 10 analog ground B 11 BLUE input signal for EBU bar of 75% 0.7 V (peak-to-peak value) Y/Y+SYNC 12 when this control input is LOW, Y without sync is connected to pin 5, input blanking at pin 5 is active; when input is HIGH, Y+SYNC is connected to pin 5, input blanking at pin 5 is not active LPFDR 13 modulator control loop filter output; black level of D'R = 4.40625 MHz FADJ 14 adjustment pin for 4.286 MHz of HF pre-emphasis filter LPFDB 15 modulator control loop filter output; black level of D'B = 4.250 MHz FLT 16 filter tuning loop capacitor output Vref 17 2.5 V internal reference voltage output CHROMA 18 chrominance output, amplitude corresponds with Y+SYNC at the output of the delay line Vext 19 external power supply for sandcastle generation; when not used this pin is connected to ground SAND 20 3-level sandcastle output pulse CVBS 21 composite SECAM output2V(peak-to-peak value) nominal NOTCH 22 Y+SYNC output after an internal resistor of 2 kΩ; a notch filter can be connected Y+SYNC IN 23 Y+SYNC input, connected to the output of the delay line LPF4.4 24 loop filter output for 4.40625 MHz reference oscillator Y+SYNC OUT 25 Y+SYNC output, 2 V (peak-to-peak value) nominal, connected to the input of the delay line XTAL/PLL 26 control pin; input HIGH = crystal tuning, input LOW = PLL tuning, both without vertical VIDENT identification, 2.5 V = PLL tuning with vertical identification VCO4.25 27 when used for PLL tuning a capacitor is connected; when used for crystal tuning a crystal has to be connected (in series with a capacitor) COLKIL 28 colour killing; input HIGH = active, internal colour difference signals are blanked CS 29 composite sync input, 0.3 V (peak-to-peak value) nominal July 1994 4, SYMBOL PIN DESCRIPTION VSSD 30 digital ground LPF4.25 31 loop filter output for 4.25 MHz reference oscillator; connected to pin 17 (Vref) when external tuning by crystal or signal source VDDD 32 supply voltage for the digital part handbook, halfpage (R Y) 1 32 VDDD MCONTR 2 31 LPF4.25 (B Y) 3 30 VSSD FH/2 4 29 CSY528 COLKIL TEST 6 27 VCO4.25 XTAL/PLLR726 VIDENT VDDA 8 25 Y+SYNC OUT TDA8505G924 LPF4.4 VSSA 10 23 Y+SYNC IN B 11 22 NOTCH Y/Y SYNC 12 21 CVBS LPFDR 13 20 SAND FADJ 14 19 Vext LPFDB 15 18 CHROMA FLT 16 17 V ref MLA952 - 3 Fig.2 Pin configuration. July 1994 5, FUNCTIONAL DESCRIPTION The Y output signal of the multiplexer is added to the sync pulse of the sync separator. The following three important circuits are integrated: • Encoder circuit The Y input (pin 5) is different to the other 5 inputs. The timing of the internal clamping is after the sync period and • Modulator control circuit there is no vertical blanking. • Sync separator and pulse shaper. The input blanking of Y can be switched off by a HIGH at pin 12, and the internal sync separator signal is not added Encoder circuit to the Y signal. In this way the Y+SYNC is allowed at pin 5 INPUT STAGE and after clamping internally connected directly to pin 25. R, G and B inputs are connected to the matrix via a The colour difference signals are switched sequentially by clamping and a blanking circuit. H/2 and fed to the low frequency pre-emphasis circuit. For an EBU colour bar of 75% the amplitude of the signal The colour-killing input signal at pin 28 can be used for must be 0.7 V (peak-to-peak value). The outputs of the completely blanking the internal colour difference signals matrix are Y, D'R and D'B. at the input of the low frequency pre-emphasis filter. The second part of the input stage contains inputs for LOW FREQUENCY PRE-EMPHASIS colour difference signals and a luminance signal. The condition for 75% colour bar is This filter is fully integrated, Fig.3 illustrates the nominal −(R−Y) = 1.05 V (peak-to-peak value) at pin 1, response. −(B−Y) = 1.33 V (peak-to-peak value) at pin 3 and The transfer is guaranteed within the illustrated area for Y = 1 V (peak-to-peak value) without sync at pin 5. After the whole ambient temperature range by a compensation clamping and blanking the amplitude and polarity are circuit. corrected such that the signals are equal to the signals of the matrix output. Signals are connected to a switch. Fast switching between the two input parts is possible by the multiplexer control pin (pin 2). MLA953 - 1 handbook, full pagewidth

H

(dB) 104 105 10 6 7f (Hz) 10 Fig.3 Nominal response for the low frequency pre-emphasis filter. July 1994 6, VERTICAL IDENTIFICATION level of D'R. The modulator control also sets the DC level at pin 15 to adjust the FM frequency to 4.250 MHz at the After the low frequency pre-emphasis the signal is black level of D'B. clamped and, if desired the vertical identification sawtooth waveform can be added. The generation of the vertical At the start of every line the FM modulator is stopped and identification is switched on/off by the logic level input at is started again by a short duration pulse of the pulse pin 26. shaper. These stop/start pulses are operating such that after two lines starting in the same phase, the start phase Figure 4 shows the sawtooth waveform at the input of the of the third line is shifted 180 degrees. This sequence is FM modulator with the corresponding frequency values inverted during each vertical blanking. after modulation. The FM signal is fed to the internal HF pre-emphasis filter. Vertical identification is only possible if PLL tuning is selected. HF PRE-EMPHASIS AND BANDPASS FILTER GAIN + LIMITER An HF pre-emphasis filter combined with a bandpass filter is integrated. The gain of this amplifier is sequentially switched, so that the amplitude of D'R is 280/230 times the amplitude of D'B Figures 5 and 6 illustrate the frequency response. Two (based on an EBU colour bar). The signal is limited at a resistors in series with a potentiometer at pin 14 adjusts lower and upper level to ensure that the FM modulator the frequency to 4.286 MHz with a tolerance of ±20 kHz. frequencies are always between 3.9 MHz and 4.756 MHz. A tuning circuit integrated with an external capacitor A DC offset between D'R and D'B is added which connected to pin 16 guarantees a stable frequency corresponds with the limiter levels. response for the whole temperature range. FM MODULATOR The output of the bandpass filter is connected directly to the chrominance blanking circuit. The signal of the gain + limiter stage is fed to the FM modulator. The modulator control adjusts the DC level at pin 13 to set the frequency of the FM signal to 4.406 MHz at the black frequency after 64 µs 64 µs modulation handbook, full pagewidth 15µs5µs4.756 MHz 35 kHz D'R 4.406 MHz 4.250 MHz D'B 3.90 MHz 18µsMLA954 35 kHz6µsFig.4 Vertical identification sawtooth waveform input. July 1994 7, MLA955 - 1 handbook, full pagewidth

H

(dB) 105 106 107f(Hz) 10 Fig.5 Frequency response of the HF pre-emphasis and bandpass filter; H as a function of frequency (1). MLA956 - 1 handboHok, full pagewidth (dB) 8 upper limit nominal 6 lower limit 3.7 3.9 4.1 4.3 4.5 4.7 4.9 f (MHz) Fig.6 Frequency response of the HF pre-emphasis and bandpass filter; H as a function of frequency (2). July 1994 8, CHROMINANCE BLANKING The outputs of the 272 divider are also used for pulse shaping. The chrominance signal is blanked by the internally generated chrominance blanking pulse. The output of this Within the vertical blanking period, another two Phase blanking stage is connected to the chrominance and Locked Loops (PLLs) synchronizes the FM modulator CVBS output circuits. during two lines with the 4.406 MHz reference VCO and during the following 2 lines with the 4.250 MHz reference Y+SYNC, CVBS, AND CHROMA OUTPUTS VCO. The loop filters are connected to pins 13 and 15 respectively. The Y output signal of the matrix is added to the composite sync signal of the sync separator. The output of this adder It is necessary to use low-leakage capacitors for these at pin 25 is connected to the input of an external delay line loop filters. which is necessary for correct timing of the Y+SYNC signal corresponding with the chrominance signal. The signal TUNING BY CRYSTAL OR EXTERNAL SIGNAL SOURCE amplitude at pin 25 is2V(peak-to-peak value) nominal, When the frequency of the sync pulse at pin 29 is not so at the output of the delay line Y+SYNC is stable or is incorrect it is possible to tune the FM modulator1V(peak-to-peak value). using an external 4.250 MHz crystal connected to pin 27. The delay line has to be DC-coupled between The 4.25 MHz loop at pin 31 has to be connected to pin 17 pins 25 and 23 to ensure the required DC level at (Vref). A stable line frequency reference is generated by pin 23. The output resistor of the delay line has to be the 272 divider circuit which is used for the 4.406 MHz connected to pin 17 where (Vref = 2.5 V). reference loop. The output of the delay line is connected to pin 23 which is An external signal source, instead of a crystal, can be the input of a buffer operational amplifier. The output of the connected at pin 27 via a capacitor in series with a resistor. buffer operational amplifier is connected to pin 22 and to The minimum AC current of 50 µA is determined by the the CVBS adder stage via an internal resistor of 2 kΩ. An resistor values (R + R ) and the output voltage of the external notch filter can be connected to pin 22. The CVBS int extsignal source (see Fig.7). signal amplitude output at pin 21 is2V(peak-to-peak value) nominal. An external emitter follower is used to When crystal tuning is used no vertical identification provide a 75 Ω output load. is possible. The amplitude of the chrominance output signal which is Crystal tuning is recommended for VTR signals. connected to pin 18 corresponds with the Y+SYNC signal at the output of the delay line. Modulator control circuit The modulator control circuit has two tuning modes which are controlled by the input at pin 26: handbook, halfpage • Tuning by line frequency TDA8505 • Tuning by crystal or external signal source. I 50µARint R27 ext signal TUNING BY LINE FREQUENCY OSCILLATOR source 800Ω1nF V (p-p) Two reference voltage controlled oscillators (VCOs) are integrated, the 4.4 MHz VCO with an internal capacitor and the 4.25 MHz VCO with an external capacitor at MSA732 - 1 pin 27. A PLL loop with divider circuits directly couples the frequencies of the two VCOs with the line frequency of the sync separator sync signal. The loop filter for the 4.40625 MHz reference is at pin 24 Fig.7 Tuning circuit for external signal source. and the loop filter for the 4.250 MHz reference is at pin 31. July 1994 9, Sync separator and pulse shaper Figures 9 and 10 show the generated pulses during vertical blanking for PLL tuning or crystal tuning The composite sync input at pin 29 together with the respectively. Figure 11 shows the pulses during line outputs of the 272 divider of the 4.250 MHz reference loop blanking. are the sources for all pulses necessary for the processing. The pulses are used for: Transcoding application • Clamping A sandcastle pulse is necessary for the PAL/NTSC • Video blanking demodulator (i.e. TDA4510) for transcoding PAL or NTSC • FH/2 to SECAM. • Chrominance blanking Most of the demodulator ICs use a sandcastle pulse with • an amplitude of 12 V or 8 V. A 12 V or8Vsandcastle isStop/start of modulator not possible with the TDA8505 because of the5Vpower • Vertical identification supply. • Timing for the modulator control To generate a 3-level sandcastle pulse at pin 20 • Sandcastle pulse shaping at pin 20. (see Fig.8) an external supply voltage must be connected External FH/2 at pin 4 is only necessary when two or more to pin 19. SECAM encoders have to be locked in the same phase. The PAL or NTSC CVBS signal is connected to the The phase of the internal FH/2 can be locked with an composite sync input (pin 29) for PLL tuning and pulse external FH/2 connected at pin 4. A reset of the internal shaping. As previously mentioned the Y input at pin 5 can FH/2 is possible by forcing pin 4 to a HIGH level. This be used as the Y+SYNC input for the filtered Y+SYNC PAL HIGH level corresponds with D'R. Pin 4 is connected to or NTSC signal, when pin 12 is at a HIGH level. ground when not used. V ext handbook, full pagewidth 4.5 V 0.2 V 2.5 V 0.2 V 0.5 V MSA733 - 1 Fig.8 3-level sandcastle pulse. July 1994 10,

July 1994 11 FIELD 2 FIELD 1

622 623 624 62512345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337

Fig.9 PLL tuning.

,

July 1994 12 FIELD 2 FIELD 1

622 623 624 62512345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337

Fig.10 Crystal tuning.

, Fig.11 Pulses during line blanking. July 1994 13, LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134); all voltages referenced to VSSA pin 10. SYMBOL PARAMETER MIN. MAX. UNIT VDDA analog supply voltage for encoder part 0 5.5 V VDDD digital supply voltage 0 5.5 V Vext external supply voltage for sandcastle generation 0 13.2 V Tstg storage temperature −65 +150 °C Tamb operating ambient temperature −25 +70 °C THERMAL CHARACTERISTICS SYMBOL PARAMETER VALUE UNIT Rth j-a thermal resistance from junction to ambient in free air 60 K/W DC CHARACTERISTICS VCC and VDD = 5 V; Tamb = 25 °C; all voltages referenced to pins 10 and 30; unless otherwise specified. SYMBOL PARAMETER MIN. TYP. MAX. UNIT VDDA analog supply voltage for encoder part (pin 8) 4.5 5.0 5.5 V VDDD digital supply voltage (pin 32) 4.5 5.0 5.5 V IDDA analog supply current − 39 − mA IDDD digital supply current − 4 − mA Vext external supply voltage for sandcastle generation08to 12 13.2 V Ptot total power dissipation − 215 − mW Vref reference voltage output (pin 17) 2.425 2.5 2.575 V AC CHARACTERISTICS VCC and VDD = 5 V; Tamb = 25 °C; composite sync signal connected to pin 29; unless otherwise specified. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Encoder circuit: input stage (pins 1, 3, 5, 7, 9 and 11; black level = clamping level Vn(max) voltage from black level positive 1.2 − − V Vn(min) voltage from black level negative only pins 1, 3 and 5 0.9 − − V Ibias(max) maximum input bias current VI = V17 − − 1 µA VI input voltage clamped input capacitor − V17 − V connected to ground ZI input clamping impedance II = 1 mA − 80 − Ω IO = 1 mA − 80 − Ω July 1994 14, SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Multiplexer control (pin 2; note 1) VIL LOW level input voltage Y, −(R−Y) 0 − 0.4 V and −(B−Y) VIH HIGH level input voltage R, G 1 − 5 V and B II input current − − −3 µA tsw switching time − 50 − ns Control input Y/Y+SYNC (pin 12) VIL LOW level input voltage blanking pin 5 active; 0 − 1 V internal sync added to Y VIH HIGH level input voltage blanking pin 5 inactive; 4 − 5 V internal sync not added to Y II(max) maximum input current − − 1 µA XTAL/PLL and VIDENT input (pin 26) VIL LOW level input voltage PLL mode; vertical 0 − 1 V identification off VIH HIGH level input voltage crystal tuning; vertical 4 − 5 V identification off VI input voltage pin 26 connected to − V17 − V pin 17; PLL tuning; vertical identification on; see Fig.4 II input current − − −6 µA COLKIL input (pin 28) VIL LOW level input voltage inactive 0 − 1 V VIH HIGH level input voltage active 4 − 5 V II(max) maximum input current − − 1 µA FH/2 input (pin 4) VIL LOW level input voltage inactive 0 − 1 V VIH HIGH level input voltage active 4 − 5 V II(max) maximum input current − − 1 µA LF pre-emphasis (see Fig.3) HF pre-emphasis and bandpass (see Figs 5 and 6) FADJ input (pin 14) resistor value for correct adjustment; see Fig.1 input sensitivity − 1.75 − kHz/mV II(max) maximum input current − − 100 nA July 1994 15, SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT FLT output (pin 16) VDCL limited DC LOW level output IO = 200 µA − 0.27 − V voltage VDCH limited DC HIGH level output II = 200 µA − 1.8 − V voltage VDC DC level output voltage tbf 0.86 tbf V Y+SYNC output (pin 25) RO output resistance − − 40 Ω Isink(max) maximum sink current 200 − − µA Isource(max) maximum source current 1 − − mA VBL black level output voltage − 1.6 − V VSYNC sync voltage amplitude 570 600 630 mV VY Y voltage amplitude 1330 1400 1470 mV B bandwidth frequency response RL = 10 kΩ; CL = 10 pF 10 − − MHz td group delay time tolerance RL = 10 kΩ; CL = 10 pF − − 20 ns td sync delay time from 220 290 360 ns pin 29 to pin 25 td Y delay time from pin 5 to pin 25 − 10 − ns Y+SYNC input (pin 23; note 2) Ibias input bias current − − 1 µA VI(max) maximum Y voltage amplitude − − 1 V NOTCH output (pin 22) RO output resistance 1750 2000 2250 Ω VDC DC output voltage level − V23 − V Isink(max) maximum sink current 300 − − µA CHROMA output (pin 18) Isink(max) maximum sink current 200 − − µA Isource(max) maximum source current 1 − − mA VDC DC voltage level − 2.5 − V ∆VDC variation of DC voltage level chrominance signal − 5 − mV blanked chrominance signal not − 5 − mV blanked RO output resistance − 120 − Ω VO(p-p) chrominance output voltage f = 4.25 MHz − 165 − mV amplitude (peak-to-peak value) f = 4.406 MHz − 205 − mV July 1994 16, SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT FREQUENCY OF CHROMINANCE SIGNAL (NOTE 3) fOR black level of D'R − 4406 − kHz fOB black level of D'B − 4250 − kHz fmax maximum frequency 4721 4756 4791 kHz fmin minimum frequency 3865 3900 3935 kHz ∆D'R deviation of D'R EBU bar of 75% 252 280 308 kHz ∆D'B deviation of D'B EBU bar of 75% 207 230 253 kHz CVBS output (pin 21) Isink(max) maximum sink current 250 − − µA Isource(max) maximum source current 1 − − mA Vblack black level voltage − 1.6 − V GY gain Y+SYNC (pin 23 to pin 21) − 6 − dB GCHR gain CHROMA (pin 18 to pin 21) − 6 − dB RO output resistance − 120 − Ω LPFDR output (pin 13) VO DC control voltage level tbf 2.4 tbf V control sensitivity − 0.2 − kHz/mV ILO output leakage current − − 50 nA LPFDB output (pin 15) VO DC control voltage level tbf 2.1 tbf V control sensitivity − 1.5 − kHz/mV ILO output leakage current − − 50 nA LPF4.4 output (pin 24) VO DC control voltage level tbf 2.3 tbf V control sensitivity − 1.5 − kHz/mV ILO output leakage current − − 100 nA LPF4.25 output (pin 31; Cext = 270 pF) VO DC control voltage level tbf 2.3 tbf V control sensitivity − 5.3 − kHz/mV ILO output leakage current − − 100 nA VCO4.25 (pin 27; note 4) CS input (pin 29) VI(p-p) sync pulse input amplitude 75 300 600 mV (peak-to-peak value) slicing level − 50 − % II input current − 4 − µA IO(max) maximum output current during sync − 100 − µA July 1994 17, SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Vext (pin 19) Iext external supply current − − 1.5 mA SAND output (pin 20; Vext = 13.2 V); see Fig.8 Isink(max) maximum sink current 100 − − µA Isource(max) maximum source current 100 − − µA VTL top voltage level Vext < 10 V Vext − 0. − − V Vext > 10 V 10 − − V Notes 1. The threshold level of pin 2 is 700 ± 20 mV. The specification of the HIGH and LOW levels is in accordance with the scart fast blanking. 2. The black level of input signal must be 2 V; amplitude1V(peak-to-peak value) nominal (Y = 700 mV, SYNC = 300 mV). 3. The tolerances of fOR and fOB are with the printed-circuit board <±5 kHz. This value can be influenced by the print layout. 4. The oscillator operates in series-resonance. The resonance resistance of the crystal must be <60 Ω and parallel capacitance of the crystal <10 pF. INTERNAL CIRCUITRY PIN NAME CIRCUIT DESCRIPTION 1 −(R−Y) −(R−Y) input; connected via 47 nF capacitor; 1.05 V (peak-to-peak value) for EBU bar of 75%; see also pins 3, 5, 7, 9 and 11 July 1994 18, PIN NAME CIRCUIT DESCRIPTION 2 MCONTR multiplexer control input: <0.4 V Y, U and V >1 V R, G and B

B

3 −(B−Y) see pin 1 −(B−Y) input; connected via 47 nF capacitor; 1.33 V (peak-to-peak value) for EBU bar of 75% 4 FH/2 FH/2 input; forcing possibility; when not used this pin is connected to ground5Ysee pin1Yinput; connected via 47 nF capacitor; 1 V (peak-to-peak value) for EBU bar of 75% 6 TEST test pin; connected to VCC or left open-circuit July 1994 19, PIN NAME CIRCUIT DESCRIPTION7Rsee pin 1 RED input; connected via 47 nF capacitor; 0.7 V (peak-to-peak value) for EBU bar of 75% 8 VDDA analog supply voltage for encoder part; 5 V nominal9Gsee pin 1 GREEN input; connected via 47 nF capacitor; 0.7 V (peak-to-peak value) for EBU bar of 75% 10 VSSA analog ground 11 B see pin 1 BLUE input; connected via 47 nF capacitor; 0.7 V (peak-to-peak value) for EBU bar of 75% 12 Y/Y+SYNC control pin: 0VYwithout sync supplied to pin55VYwith sync supplied to pin 5 July 1994 20, PIN NAME CIRCUIT DESCRIPTION 13 LPFDR modulator control loop filter with low leakage capacitors 14 FADJ adjustment pin for 4.286 MHz: potentiometer in series with two resistors between ground and pin 17 15 LPFDB see pin 13 modulator control loop filter with low leakage capacitors 16 FLT filter control pin; 220 nF capacitor to ground

B B

July 1994 21, PIN NAME CIRCUIT DESCRIPTION 17 Vref 2.5 V reference voltage decoupling with 47 µF and 22 nF capacitors 18 CHROMA chrominance output 19 Vext pin for external power supply, for sandcastle pulse; Vext > 8 V; if not used, the pin should be connected to ground 20 SAND sandcastle pulse July 1994 22, PIN NAME CIRCUIT DESCRIPTION 21 CVBS composite SECAM output 22 NOTCH pin for external notch filter 23 Y+SYNC IN input of the delayed Y+SYNC signal of the delay line; black level must be2V24 LPF4.4 see pin 13 loop filter for 4.40625 MHz reference oscillator July 1994 23, PIN NAME CIRCUIT DESCRIPTION 25 Y+SYNC OUT output of the delayed Y+SYNC signal, connected to the delay line via a resistor 26 XTAL/PLL control pin: VIDENT without vertical identification: 0 V PLL tuning

BB5Vcrystal tuning

with vertical identification: 2.5 V PLL tuning

B B B B

27 VCO4.25 tuning of 4.25 MHz oscillator: PLL tuning: C = 270 pF to ground crystal tuning: crystal in series with a

B capacitor to ground B external tuning:

signal via 1 nF capacitor in series with a resistor July 1994 24, PIN NAME CIRCUIT DESCRIPTION 28 COLKIL colour killing input: 0 V not active5Vactive, internal D'R and D'B are blanked 29 CS composite sync signal input; amplitude <600 mV (peak-to-peak value) 30 VSSD digital ground

B B B B

July 1994 25, PIN NAME CIRCUIT DESCRIPTION 31 LPF4.25 loop filter for 4.25 MHz reference oscillator; connected to pin 17 if crystal or external tuning 32 VDDD supply voltage digital part; 5 V nominal July 1994 26, PACKAGE OUTLINE 29.4 10.7 28.5 10.2 3.8 max 4.7 max 3.2 0.51 2.8 min 0.18 M 1.6 0.53 0.32 max1.778 max (15x) max 1.3 max 10.16 12.2 10.5 MSA270 32 17 9.1 8.7 1 16 Dimensions in mm. Fig.12 Plastic shrink dual in-line package; 32 leads (400 mil) (SDIP32; SOT232-1). July 1994 27 seating plane, SOLDERING specified storage maximum. If the printed-circuit board has been pre-heated, forced cooling may be necessary Plastic dual in-line packages immediately after soldering to keep the temperature within BY DIP OR WAVE the permissible limit. The maximum permissible temperature of the solder is REPAIRING SOLDERED JOINTS 260 °C; this temperature must not be in contact with the joint for more than 5 s. The total contact time of successive Apply a low voltage soldering iron below the seating plane solder waves must not exceed 5 s. (or not more than 2 mm above it). If its temperature is below 300 °C, it must not be in contact for more than 10 s; The device may be mounted up to the seating plane, but if between 300 and 400 °C, for not more than 5 s. the temperature of the plastic body must not exceed the

DEFINITIONS

Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. July 1994 28,

NOTES

July 1994 29,

NOTES

July 1994 30,

NOTES

July 1994 31,

Philips Semiconductors – a worldwide company

Argentina: IEROD, Av. Juramento 1992 - 14.b, (1428) Norway: Box 1, Manglerud 0612, OSLO, BUENOS AIRES, Tel. (541)786 7633, Fax. (541)786 9367 Tel. (022)74 8000, Fax. (022)74 8341 Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Pakistan: Philips Electrical Industries of Pakistan Ltd., Tel. (02)805 4455, Fax. (02)805 4466 Exchange Bldg. ST-2/A, Block 9, KDA Scheme 5, Clifton, Austria: Triester Str. 64, A-1101 WIEN, P.O. Box 213, KARACHI 75600, Tel. (021)587 4641-49, Tel. (01)60 101-1236, Fax. (01)60 101-1211 Fax. (021)577035/5874546. Belgium: Postbus 90050, 5600 PB EINDHOVEN, The Netherlands, Philippines: PHILIPS SEMICONDUCTORS PHILIPPINES Inc, Tel. (31)40 783 749, Fax. (31)40 788 399 106 Valero St. Salcedo Village, P.O. Box 2108 MCC, MAKATI, Brazil: Rua do Rocio 220 - 5th floor, Suite 51, Metro MANILA, Tel. (02)810 0161, Fax. (02)817 3474 CEP: 04552-903-SÃO PAULO-SP, Brazil. Portugal: PHILIPS PORTUGUESA, S.A., P.O. Box 7383 (01064-970). Rua dr. António Loureiro Borges 5, Arquiparque - Miraflores, Tel. (011)821-2333, Fax. (011)829-1849 Apartado 300, 2795 LINDA-A-VELHA, Canada: INTEGRATED CIRCUITS: Tel. (01)14163160/4163333, Fax. (01)14163174/4163366. Tel. (800)234-7381, Fax. (708)296-8556 Singapore: Lorong 1, Toa Payoh, SINGAPORE 1231, DISCRETE SEMICONDUCTORS: 601 Milner Ave, Tel. (65)350 2000, Fax. (65)251 6500 SCARBOROUGH, ONTARIO, M1B 1M8, South Africa: S.A. PHILIPS Pty Ltd., Components Division, Tel. (0416)292 5161 ext. 2336, Fax. (0416)292 4477 195-215 Main Road Martindale, 2092 JOHANNESBURG, Chile: Av. Santa Maria 0760, SANTIAGO, P.O. Box 7430 Johannesburg 2000, Tel. (02)773 816, Fax. (02)777 6730 Tel. (011)470-5911, Fax. (011)470-5494. Colombia: IPRELENSO LTDA, Carrera 21 No. 56-17, Spain: Balmes 22, 08007 BARCELONA, 77621 BOGOTA, Tel. (571)249 7624/(571)217 4609, Tel. (03)301 6312, Fax. (03)301 42 43 Fax. (571)217 4549 Sweden: Kottbygatan 7, Akalla. S-164 85 STOCKHOLM, Denmark: Prags Boulevard 80, PB 1919, DK-2300 COPENHAGEN S, Tel. (0)8-632 2000, Fax. (0)8-632 2745 Tel. (032)88 2636, Fax. (031)57 1949 Switzerland: Allmendstrasse 140, CH-8027 ZÜRICH, Finland: Sinikalliontie 3, FIN-02630 ESPOO, Tel. (01)488 2211, Fax. (01)481 77 30 Tel. (9)0-50261, Fax. (9)0-520971 Taiwan: PHILIPS TAIWAN Ltd., 23-30F, 66, Chung Hsiao West France: 4 Rue du Port-aux-Vins, BP317, Road, Sec. 1. Taipeh, Taiwan ROC, P.O. Box 22978, 92156 SURESNES Cedex, TAIPEI 100, Tel. (02)388 7666, Fax. (02)382 4382. Tel. (01)4099 6161, Fax. (01)4099 6427 Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd., Germany: PHILIPS COMPONENTS UB der Philips G.m.b.H., 209/2 Sanpavuth-Bangna Road Prakanong, P.O. Box 10 63 23, 20043 HAMBURG, Bangkok 10260, THAILAND, Tel. (040)3296-0, Fax. (040)3296 213. Tel. (662)398-0141, Fax. (662)398-3319. Greece: No. 15, 25th March Street, GR 17778 TAVROS, Turkey: Talatpasa Cad. No. 5, 80640 GÜLTEPE/ISTANBUL, Tel. (01)4894 339/4894 911, Fax. (01)4814 240 Tel. (0212)279 2770, Fax. (0212)269 3094 Hong Kong: PHILIPS HONG KONG Ltd., Components Div., United Kingdom: Philips Semiconductors Limited, P.O. Box 65, 6/F Philips Ind. Bldg., 24-28 Kung Yip St., KWAI CHUNG, N.T., Philips House, Torrington Place, LONDON, WC1E 7HD, Tel. (852)424 5121, Fax. (852)428 6729 Tel. (071)436 41 44, Fax. (071)323 03 42 India: Philips INDIA Ltd, Components Dept, United States: INTEGRATED CIRCUITS: Shivsagar Estate, A Block , 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Dr. Annie Besant Rd. Worli, Bombay 400 018 Tel. (800)234-7381, Fax. (708)296-8556 Tel. (022)4938 541, Fax. (022)4938 722 DISCRETE SEMICONDUCTORS: 2001 West Blue Heron Blvd., Indonesia: Philips House, Jalan H.R. Rasuna Said Kav. 3-4, P.O. Box 10330, RIVIERA BEACH, FLORIDA 33404, P.O. Box 4252, JAKARTA 12950, Tel. (800)447-3762 and (407)881-3200, Fax. (407)881-3300 Tel. (021)5201 122, Fax. (021)5205 189 Uruguay: Coronel Mora 433, MONTEVIDEO, Ireland: Newstead, Clonskeagh, DUBLIN 14, Tel. (02)70-4044, Fax. (02)92 0601 Tel. (01)640 000, Fax. (01)640 200 For all other countries apply to: Philips Semiconductors, Italy: PHILIPS COMPONENTS S.r.l., International Marketing and Sales, Building BAF-1, Viale F. Testi, 327, 20162 MILANO, P.O. Box 218, 5600 MD, EINDHOVEN, The Netherlands, Tel. (02)6752.3302, Fax. (02)6752 3300. Telex 35000 phtcnl, Fax. +31-40-724825 Japan: Philips Bldg 13-37, Kohnan 2 -chome, Minato-ku, TOKYO 108, SCD32 © Philips Electronics N.V. 1994 Tel. (03)3740 5028, Fax. (03)3740 0580 All rights are reserved. Reproduction in whole or in part is prohibited without the Korea: (Republic of) Philips House, 260-199 Itaewon-dong, prior written consent of the copyright owner. Yongsan-ku, SEOUL, Tel. (02)794-5011, Fax. (02)798-8022 The information presented in this document does not form part of any quotation Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, or contract, is believed to be accurate and reliable and may be changed without SELANGOR, Tel. (03)750 5214, Fax. (03)757 4880 notice. No liability will be accepted by the publisher for any consequence of its Mexico: Philips Components, 5900 Gateway East, Suite 200, use. Publication thereof does not convey nor imply any license under patent- or EL PASO, TX 79905, Tel. 9-5(800)234-7381, Fax. (708)296-8556 other industrial or intellectual property rights. Netherlands: Postbus 90050, 5600 PB EINDHOVEN, Bldg. VB Printed in The Netherlands Tel. (040)783749, Fax. (040)788399 New Zealand: 2 Wagener Place, C.P.O. Box 1041, AUCKLAND, 533061/1500/03/pp32 Date of release: July 1994 Tel. (09)849-4160, Fax. (09)849-7811 Document order number: 9397 736 70011

Philips Semiconductors

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