Download: SYNCHRONOUS 64K x 32 SRAM BURST SRAM +3.3V SUPPLY, PIPELINED, SINGLE PIPELINED OUTPUT CYCLE DESELECT, BURST COUNTER

SYNCHRONOUS 64K x 32 SRAM BURST SRAM +3.3V SUPPLY, PIPELINED, SINGLE PIPELINED OUTPUT CYCLE DESELECT, BURST COUNTER

FEATURES GENERAL DESCRIPTIO N • Fast access times: 5, 6, 7, and 8ns The Galvantech Synchronous Burst SRAM family • Fast clock speed: 100, 83, and 66 MHz employs high-speed, low power CMOS designs using • Provide high performance 3-1-1-1 access rate advanced triple-layer polysilicon, double-layer metal • Fast OE# access times: 5, 6, and 7ns technology. Each memory cell consists of four transistors and • Optimal for depth expansion (one cycle chip deselect to two high valued resistors. eliminate bus contention) The GVT7164D32 SRAM integrates 65,536x32 SRAM • Single +3.3V -5% and +10%power supply cells with advanced synchronous peripheral circuitry and a 2- • Support +2.5V I/O bit counter for internal burst operation. All synchronous • 5V tolerant inputs except I/O’s inputs are gated by registers controlled by a positive-edge- • Clamp diodes to VSSQ at all outputs triggered clock input (CLK). The synchronous inputs include • Common data inputs and data outputs all addresses, all data inputs, address-pipelining chip enable • BYTE WRITE ENABLE and GLOBAL WRITE control (CE#), depth-expansion chip enables (CE2# and CE2), burst • Three chip enables for depth expansion and address control inputs (ADSC#, ADSP#, and ADV#), write enables pipeline (BW1#, BW2#, BW3#, BW4#,and BWE#), and global write • Address, control, input, and output pipeline registers (GW#). • Internally self-timed WRITE CYCLE Asynchronous inputs include the output enable (OE#) • Burst control pins (interleaved or linear burst sequence) and burst mode control (MODE). The data outputs (Q), • Automatic power-down for portable applications enabled by OE#, are also asynchronous. • High density, high speed packages Addresses and chip enables are registered with either • Low capacitive bus loading address status processor (ADSP#) or address status controller • High 30pF output drive capability at rated access time (ADSC#) input pins. Subsequent burst addresses can be OPTIONS MARKING internally generated as controlled by the burst advance pin(ADV#). • Timing Address, data inputs, and write controls are registered on- 5ns access/10ns cycle -5 chip to initiate self-timed WRITE cycle. WRITE cycles can 6ns access/12ns cycle -6 be one to four bytes wide as controlled by the write control 7ns access/15ns cycle -7 inputs. Individual byte write allows individual byte to be 8ns access/15ns cycle -8 written. BW1# controls DQ1-DQ8. BW2# controls DQ9- • Packages DQ16. BW3# controls DQ17-DQ24. BW4# controls DQ25- 100-pin PQFP Q DQ32. BW1#, BW2# BW3#, and BW4# can be active only 100-pin TQFP T with BWE# being LOW. GW# being LOW causes all bytes to be written. This device also incorporates pipelined enable circuit for easy depth expansion without penalizing system performance. The GVT7164D32 operates from a +3.3V power supply. All inputs and outputs are TTL-compatible. The device is ideally suited for 486, PentiumTM, 680x0, and PowerPCTM systems and for systems that are benefited from a wide synchronous data bus. Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, CA 95051 Pentium is a trademark of Intel Corporatio.n Tel (408) 566-0688 Fax (408) 566-0699 PowerPC is a trademark of IBM Corporatio.n Galvantech, Inc. reserves the right to change Rev. 3/99 products or specifications without notic.e,

FUNCTIONAL BLOCK DIAGRAM

BYTE 1 WRITE BW1# D Q BWE#

CLK

BYTE 2 WRITE BW2# D Q GW# BYTE 3 WRITE BW3# D Q BYTE 4 WRITE BW4# D Q CE# ENABLE CE2DQDQCE2# OE# ZZ Power Down Logic Input ADSP# Register A15-A2 Address Register OUTPUT ADSC# REGISTER CLRDQDQ1-DQ32 ADV# Binary A1-A0 Counter & Logic

MODE NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing

diagrams for detailed information. March 25, 19992Galvantech, Inc. reserves the right to change products or specifications without not.ice 64Kx8x4SRAM Array byte 4 write Output Buffers byte 3 write byte 2 write byte 1 write,

PIN ASSIGNMENT (Top View)

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC 1 80 NC DQ17 2 79 DQ16 DQ18 3 78 DQ15 VCCQ 4 77 VCCQ VSSQ 5 76 VSSQ DQ19 6 75 DQ14 DQ20 7 74 DQ13 DQ21 8 73 DQ12 DQ22 9 72 DQ11 VSSQ 10 71 VSSQ VCCQ 11 70 VCCQ DQ23 12 69 DQ10 DQ24 13 68 DQ9 NC 14 67 VSS VCC 15 100-pin PQFP 66 NC NC 16 or 65 VCC VSS 17 100-pin TQFP 64 ZZ DQ25 18 63 DQ8 DQ26 19 62 DQ7 VCCQ 20 61 VCCQ VSSQ 21 60 VSSQ DQ27 22 59 DQ6 DQ28 23 58 DQ5 DQ29 24 57 DQ4 DQ30 25 56 DQ3 VSSQ 26 55 VSSQ VCCQ 27 54 VCCQ DQ31 28 53 DQ2 DQ32 29 52 DQ1 NC 30 51 NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

PIN DESCRIPTIONS QFP PINS SYMBOL TYPE DESCRIPTIO N

37, 36, 35, 34, 33, A0-A15 Input- Addresses: These inputs are registered and must meet the setup and hold times around 32, 100, 99, 82, 81, Synchronous the rising edge of CLK. The burst counter generates internal addresses associated with A0 44, 45, 46, 47, 48, 4 9 and A1, during burst cycle and wait cycle . 93,94,95,96 BW1#, Input- Byte Write: A byte write is LOW for a WRITE cycle and HIGH for a READ cycle. BW1# BW2#, Synchronous controls DQ1-DQ8. BW2# controls DQ9-DQ16. BW3# controls DQ17-DQ24. BW4# BW3#, controls DQ25-DQ32. Data I/O are high impedance if either of these inputs are LOW, BW4# conditioned by BWE# being LOW . 87 BWE# Input- Write Enable: This active LOW input gates byte write operations and must meet the setup Synchronous and hold times around the rising edge of CLK . 88 GW# Input- Global Write: This active LOW input allows a full 32-bit WRITE to occur independent of the Synchronous BWE# and BWn# lines and must meet the setup and hold times around the rising edge of CLK. 89 CLK Input- Clock: This signal registers the addresses, data, chip enables, write control and burst Synchronous control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock’s rising edge . 98 CE# Input- Chip Enable: This active LOW input is used to enable the device and to gate ADSP# . Synchronous 92 CE2# Input- Chip Enable: This active LOW input is used to enable the device . Synchronous March 25, 19993Galvantech, Inc. reserves the right to change products or specifications without not.ice MODE A6 A5 A7 A4 CE# A3 CE2 A2 BW4# A1 BW3# A0 BW2# NC BW1# NC CE2# VSS VCC VCC VSS NC CLK NC GW# A10 BWE# A11 OE# A12 ADSC# A13 ADSP# A14 ADV# A15 A8 NC A9,

PIN DESCRIPTIONS (continued)

QFP PINS SYMBOL TYPE DESCRIPTIO N 97 CE2 input- Chip enable: This active HIGH input is used to enable the device . Synchronous 86 OE# Input Output Enable: This active LOW asynchronous input enables the data output drivers . 83 ADV# Input- Address Advance: This active LOW input is used to control the internal burst counter. Synchronous A HIGH on this pin generates wait cycle (no address advance). 84 ADSP# Input- Address Status Processor: This active LOW input, along with CE# being LOW, Synchronous causes a new external address to be registered and a READ cycle is initiated using the new address . 85 ADSC# Input- Address Status Controller: This active LOW input causes device to be de-selected or Synchronous selected along with new external address to be registered. A READ or WRITE cycle is initiated depending upon write control inputs . 31 MODE Input- Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR Static BURST. A NC or HIGH on this pin selects INTERLEAVED BURST . 64 ZZ Input- Snooze: This active HIGH input puts the device in low power consumption standby Asynchro-nou s mode. For normal operation, this input has to be either LOW or NC (No Connect) . 52, 53, 56, 57, 58, 59, DQ1-DQ32 Input/ Data Inputs/Outputs: First Byte is DQ1-DQ8. Second Byte is DQ9-DQ16. Third Byte 62, 63, 68, 69, 72-75, Output is DQ17-DQ24. Fourth Byte is DQ25-DQ32. Input data must meet setup and hold 78, 79, 2, 3, 6-9, 12, 13, times around the rising edge of CLK . 18, 19, 22-25, 28, 2 9 15, 41, 65, 91 VCC Supply Power Supply: +3.3V -5% to +10%. Pin 14 does not have to be connected directly to VCCas long as it is greater than VIH . 17, 40, 67, 90 VSS Ground Ground: GND 4, 11, 20, 27, 54, 61, 70, VCCQ I/O Supply Output Buffer Supply: +3.3V -5% to +10%. For 2.5V I/O: 2.375V to VCC . 5, 10, 21, 26, 55, 60, 71, VSSQ I/O Ground Output Buffer Ground: GN D 1, 14, 16, 30, 38, 39, 42, NC - No Connect: These signals are not internally connected . 43, 50, 51, 66, 8 0

BURST ADDRESS TABLE (MODE = NC/VCC )

First Address Second Address Third Address Fourth Address (external ) (internal ) (internal ) (internal ) A...A00 A...A01 A...A10 A...A11 A...A01 A...A00 A...A11 A...A10 A...A10 A...A11 A...A00 A...A01 A...A11 A...A10 A...A01 A...A00

BURST ADDRESS TABLE (MODE = GND )

First Address Second Address Third Address Fourth Address (external ) (internal ) (internal ) (internal ) A...A00 A...A01 A...A10 A...A11 A...A01 A...A10 A...A11 A...A00 A...A10 A...A11 A...A00 A...A01 A...A11 A...A00 A...A01 A...A10

PARTIAL TRUTH TABLE FOR READ/WRIT E

FUNCTION GW# BWE# BW1# BW2# BW3# BW4# READHHXXXXREADHLHHHHWRITE one byteHLLHHHWRITE all bytesHLLLLLWRITE all bytesLXXXXXMarch 25, 19994Galvantech, Inc. reserves the right to change products or specifications without not.ice,

TRUTH TABLE

OPERATION ADDRESSUSED CE# CE2# CE2 ADSP# ADSC# ADV# WRITE# OE# CLK DQ Deselected Cycle, Power Dow n NoneHXXXLXXXL-H High-Z Deselected Cycle, Power Dow n NoneLXLLXXXXL-H High-Z Deselected Cycle, Power Dow n NoneLHXLXXXXL-H High-Z Deselected Cycle, Power Dow n NoneLXLHLXXXL-H High-Z Deselected Cycle, Power Dow n NoneLHXHLXXXL-H High-Z READ Cycle, Begin Burs t ExternalLLHLXXXLL-H Q READ Cycle, Begin Burs t ExternalLLHLXXXHL-H High-Z WRITE Cycle, Begin Burs t ExternalLLHHLXLXL-H D READ Cycle, Begin Burs t ExternalLLHHLXHLL-H Q READ Cycle, Begin Burs t ExternalLLHHLXHHL-H High-Z READ Cycle, Continue Burs t NextXXXHHLHLL-H Q READ Cycle, Continue Burs t NextXXXHHLHHL-H High-Z READ Cycle, Continue Burs t NextHXXXHLHLL-H Q READ Cycle, Continue Burs t NextHXXXHLHHL-H High-Z WRITE Cycle, Continue Burs t NextXXXHHLLXL-H D WRITE Cycle, Continue Burs t NextHXXXHLLXL-H D READ Cycle, Suspend Burs t CurrentXXXHHHHLL-H Q READ Cycle, Suspend Burs t CurrentXXXHHHHHL-H High-Z READ Cycle, Suspend Burs t CurrentHXXXHHHLL-H Q READ Cycle, Suspend Burs t CurrentHXXXHHHHL-H High-Z WRITE Cycle, Suspend Burs t CurrentXXXHHHLXL-H D WRITE Cycle, Suspend Burs t CurrentHXXXHHLXL-H D Note: 1. X means “don’t care.” H means logic HIGH. L means logic LOW. WRITE# = L means [BWE# + BW1#*BW2#*BW3#*BW4#]*GW# equals LOW. WRITE# = H means [BWE# + BW1#*BW2#*BW3#*BW4#]*GW# equals HIGH. 2. BW1# enables write to DQ1-DQ8. BW2# enables write to DQ9-DQ16. BW3# enables write to DQ17-DQ24. BW4# enables write to DQ25-DQ32. 3. All inputs except OE# must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 4. Suspending burst generates wait cycle. 5. For a write operation following a read operation, OE# must be HIGH before the input data required setup time plus High-Z time for OE# and staying HIGH throughout the input data hold time. 6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 7. ADSP# LOW along with chip being selected always initiates an READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE# LOW for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification. March 25, 19995Galvantech, Inc. reserves the right to change products or specifications without not.ice,

ABSOLUTE MAXIMUM RATINGS * *Stresses greater than those listed uunder “Absolute Maximum Voltage on VCC Supply Relative to VSS...-0.5V to +4.6V Ratings” may cause permanent damage to the device.This is a stress V ...-0.5V to VCC+0.5V rating only and functional operation of the device at these or anyIN Storage Temperature (plastic) ...-55oC to +150o other conditions above those indicated in the operational sections of

Junction Temperature ...+150o this specification is not implied. Exposure to absolute maximumrating conditions for extended periods may affect reliability.

Power Dissipation ...1.0W Short Circuit Output Current ...50mA DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITION S

(0oC ≤ Ta ≤ 70°C; VCC = 3.3V -5 to +10% unless otherwise noted) DESCRIPTIO N CONDITION S SYMBOL MIN MAX UNITS NOTES Input High (Logic 1) Voltag e Data Inputs (DQxx ) VIHD 2.0 VCCQ+0.3 V 1,2 All Other Input s VIH 2.0 4.6 V 1,2 Input Low (Logic 0) Voltag e VIl -0.3 0.8 V 1, 2 Input Leakage Curren t 0V < VIN < VCC ILI -2 2 uA 14 Output Leakage Curren t Output(s) disabled, ILO -2 2 uA 0V < VOUT < VCC Output High Voltag e IOH = -4.0mA VOH 2.4 V 1, 11 Output Low Voltag e IOL = 8.0mA VOL 0.4 V 1, 11 Supply Voltag e VCC 3.1 3.6V1I/O Supply Voltage (3.3V I/O ) VCCQ 3.1 3.6V1I/O Supply Voltage (2.5V I/O ) VCCQ 2.375 VCCV1DESCRIPTIO N CONDITION S SYM TYP -5 -6 -7 -8 UNITS NOTES Power Supply Device selected; all inputs < VILor > Icc 80 225 185 120 115 mA 3, 12, Current: Operatin g VIH;cycle time > tKC MIN; VCC =MAX; 13 outputs open CMOS Standb y Device deselected; VCC = MAX ; ISB2 0.22222mA 12,13 all inputs < VSS +0.2 or >VCC -0.2; all inputs static; CLK frequency = 0 TTL Standby Device deselected; all inputs < VIL ISB3 8 18 18 18 18 mA 12,13 or > VIH; all inputs static ; VCC = MAX; CLK frequency = 0 Clock Runnin g Device deselected ; ISB4 12 30 25 20 15 mA 12,13 all inputs < VIL or > VIH; VCC = MAX ; CLK cycle time > tKC MIN

CAPACITANCE

DESCRIPTIO N CONDITION S SYMBOL TYP MAX UNITS NOTES Input Capacitanc e TA = 25 oC; f = 1 MHz CI34pF 4 Input/Output Capacitance (DQ ) VCC = 3.3V CO67pF 4

THERMAL CONSIDERATIO N

DESCRIPTIO N CONDITION S SYMBOL TQFP TYP UNITS NOTES Thermal Resistance - Junction to Ambien t Still air, soldered on 4.25xΘoJA 20 C/W Thermal Resistance - Junction to Cas e 1.125 inch 4-layer PC B ΘJC 1 oC/W March 25, 19996Galvantech, Inc. reserves the right to change products or specifications without not.ice,

AC ELECTRICAL CHARACTERISTICS

(Note 5) (0oC ≤ TA ≤ 70oC; VCC = 3.3V -5 to +10%) -5 -6 -7 -8 DESCRIPTIO N SYM MIN MAX MIN MAX MIN MAN MIN MAN UNITS NOTES Clock Clock cycle tim e tKC 10 12 15 15 ns Clock HIGH tim e tKH4455ns Clock LOW tim e tKL4455ns Output Times Clock to output vali d tKQ5678ns Clock to output invali d tKQX2222ns Clock to output in Low- Z tKQLZ3333ns 6,7 Clock to output in High- Z tKQHZ5566ns 6,7 OE to output vali d tOEQ5677ns 9 OE to output in Low- Z tOELZ0000ns 6,7 OE to output in High- Z tOEHZ4566ns 6,7 Setup Times Address, Controls and DataIntS 2.0 2.5 2.5 3 ns 10 Hold Times Address, Controls and DataIntH 0.5 0.5 0.5 0.5 ns 10

CAPACITANCE DERATIN G

DESCRIPTIO N SYMBOL TYP MAX UNITS NOTES Clock to output vali d ∆ tKQ 0.016 ns / pF 15 March 25, 19997Galvantech, Inc. reserves the right to change products or specifications without not.ice, AC TEST CONDITIONS FOR 3.3V I/O OUTPUT LOADS FOR 3.3V I/O Input pulse levels 0V to 3.0V DQ Z0 = 50Ω 50Ω 30 pFInput rise and fall times 1.5ns Input timing reference levels 1.5V Vt = 1.5V Output reference levels 1.5V Fig. 1 OUTPUT LOAD EQUIVALENT Output load See Figures 1 and 2 3.3v 317Ω AC TEST CONDITIONS FOR 2.5V I/O

DQ

Input pulse levels 0V to 2.5V 351Ω 5 pF Input slew rate 1.0V/ns Output rise and fall times(max) 1.8ns Fig. 2 OUTPUT LOAD EQUIVALENT Input timing reference levels 1.25V OUTPUT LOADS FOR 2.5V I/O Output reference levels 1.25V Output load See Figures 3 DQ

Z0 = 50Ω 50Ω Vt = 1.25V

Fig. 3 OUTPUT LOAD EQUIVALENT NOTES 10. This is a synchronous device. All synchronous inputs must meet specified setup and hold time, except for “don’t care” as defined 1. All voltages referenced to VSS (GND). in the truth table. 2. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2. t 11. AC I/O curves are available upon request.Undershoot: VIL ≤ -2.0V for t ≤ KC /2 12. “Device Deselected” means the device is in POWER -DOWN 3. Icc is given with no output current. Icc increases with greater mode as defined in the truth table. “Device Selected” means the output loading and faster cycle times. device is active. 4. This parameter is sampled. 13. Typical values are measured at 3.3V, 25oC and 20ns cycle time. 5. Test conditions as specified with the output loading as shown in 14. MODE pin has an internal pull-up and ZZ pin has an internal Fig. 1 unless otherwise noted. pull-down. These two pins exhibit an input leakage current of 6. Output loading is specified with CL=5pF as in Fig. 2. +30 µA. 7. At any given temperature and voltage condition, tKQHZ is less 15. Capacitance derating applies to capacitance different from the than tKQLZ and tOEHZ is less than tOELZ. load capacitance shown in Fig. 1 or Fig. 3, for 3.3V or 2.5V I/O 8. A READ cycle is defined by byte write enables all HIGH or respectively ADSP# LOW along with chip enables being active for the required setup and hold times. A WRITE cycle is defined by at one byte or all byte WRITE per READ/WRITE TRUTH TABLE. 9. OE# is a “don’t care” when a byte write enable is sampled LOW. March 25, 19998Galvantech, Inc. reserves the right to change products or specifications without not.ice,

READ TIMIN G

tKC tKL

CLK

tS tKH

ADSP#

tH

ADSC#

tS

ADDRESS A1 A2

tH

BW1#, BW2#, BW3#, BW4#, BWE#, GW# CE#

(See Note) tS

ADV#

tH

OE#

t t tKQ OEQ KQ tKQLZ tOELZ

DQ Q(A1) Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) Q(A2) Q(A2+1)

SINGLE READ BURST READ Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active . March 25, 19999Galvantech, Inc. reserves the right to change products or specifications without not.ice,

WRITE TIMIN G CLK

tS

ADSP#

tH

ADSC#

tS

ADDRESS A1 A2 A3

tH

BW1#, BW2#, BW3#, BW4#, BWE# GW# CE#

(See Note) tS

ADV#

tH

OE#

tOEHZ tKQX

DQ Q D(A1) D(A2) D(A2+1) D(A2+1) D(A2+2) D(A2+3) D(A3) D(A3+1) D(A3+2)

SINGLE WRITE BURST WRITE BURST WRITE Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active . March 25, 199 9 10 Galvantech, Inc. reserves the right to change products or specifications without not.ice,

READ/WRITE TIMIN G CLK

tS

ADSP#

tH

ADSC#

tS

ADDRESS A1 A2 A3 A4 A5

tH

BW1#, BW2#, BW3#, BW4#, BWE#, GW# CE#

(See Note)

ADV# OE# DQ Q(A1) Q(A2) D(A3) Q(A3) Q(A4) Q(A4+1) Q(A4+2) D(A5) D(A5+1)

Single Pass Through Reads Single Write Burst Read Burst Write

Note: CE# active in this timing diagram means that all chip enables CE#, CE2, and CE2# are active .

March 25, 199 9 11 Galvantech, Inc. reserves the right to change products or specifications without not.ice, 100 Pin PQFP Package Dimension s 17.20 + 0.30 14.00 + 0.10 # 1 2.80 + 0.25 0.65 Basic 0.30 + 0.10 Note: All dimensions in Millimeters March 25, 199 9 12 Galvantech, Inc. reserves the right to change products or specifications without not.ice 23.20 + 0.30 20.00 + 0.10, 100 Pin TQFP Package Dimension s 16.00 + 0.10 14.00 + 0.10 # 1 1.40 + 0.05 0.65 Basic 0.30 + 0.08 Note: All dimensions in Millimeters March 25, 199 9 13 Galvantech, Inc. reserves the right to change products or specifications without not.ice 22.00 + 0.10 20.00 + 0.10,

Ordering Information GVT 7164D32 X - X

Galvantech Prefix Part Number Speed (5 =5ns, 6 = 6ns, 7 = 7ns , 8 = 8ns) Package (Q = PQFP, T = TQFP) March 25, 199 9 14 Galvantech, Inc. reserves the right to change products or specifications without not.ice]

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