Download: OUTLINE OF CIRCUIT DESCRIPTION 1-1. CA1 and A PART OF CA2 CIRCUIT DESCRIPTIONS Around CCD block 10987654321

OUTLINE OF CIRCUIT DESCRIPTION 1-1. CA1 and A PART OF CA2 CIRCUIT DESCRIPTIONS Around CCD block 109876543211. IC Configuration CA1 board Ye Cy Ye Cy IC901 (ICX411AQ) CCD imager G Mg G CA2 board MgYe Cy Ye IC931 H driver, CDS, AGC and A/D converter CyG Mg G Mg IC934 (CXD3400N) V driver Ye Cy Ye Cy G Mg G 2. IC901 (CCD imager) Mg (Note) Horizontal register [Structure] Interline type CCD image sensor Image size Diagonal 8.293 mm (1/1.8 type) 11 12 13 14 15 16 17 18 19 20 Pixels in total 2384 (H) x 1734 (V) Recording pixels 2288 (H) x 1712 (V) (Note) : Photo sensor Fig. 1-2. CCD Block Diagram Pi...
Author: Folver Shared: 8/19/19
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OUTLINE OF CIRCUIT DESCRIPTION 1-1. CA1 and A PART OF CA2 CIRCUIT

DESCRIPTIONS Around CCD block 10987654321

1. IC Configuration CA1 board Ye Cy Ye Cy IC901 (ICX411AQ) CCD imager G Mg G CA2 board MgYe Cy Ye IC931 H driver, CDS, AGC and A/D converter CyG Mg G Mg IC934 (CXD3400N) V driver Ye Cy Ye Cy G Mg G 2. IC901 (CCD imager) Mg (Note) Horizontal register [Structure] Interline type CCD image sensor Image size Diagonal 8.293 mm (1/1.8 type) 11 12 13 14 15 16 17 18 19 20 Pixels in total 2384 (H) x 1734 (V) Recording pixels 2288 (H) x 1712 (V) (Note) : Photo sensor Fig. 1-2. CCD Block Diagram Pin No. Symbol Pin Description Waveform Voltage 1 Vø4 Vertical register transfer clock -7.5 V, 0 V 2, 3 Vø3A, Vø3B Vertical register transfer clock -7.5 V, 0 V, 15V4Vø2 Vertical register transfer clock -7.5 V, 0 V 5, 6 Vø1A, Vø1B Vertical register transfer clock -7.5 V, 0 V, 15 V 9, 15 GND GND GND0V10 VOUT Signal output Aprox. 10 V 11 VDD Circuit power DC 15 V 12 øRG Reset gate clock 12.5 V, 16 V 13, 20 Hø2 Horizontal register transfer clock 0 V, 5 V 14, 19 Hø1 Horizontal register transfer clock 0 V, 5 V 16 øSUB Substrate clock DC Approx. 8 V Approx. 8 V 17 CSUB Substrate bias DC (Different from every CCD) 18 VL Protection transistor bias DC Table 1-1. CCD Pin Description When sensor read-out – 2 – VDD VOUT ØRG GNDHØ2TESTHØ1TEST Vertical register GNDVØ1B ØSUBVØ1A CSUBVØ2VLVØ3BHØ1VØ3AHØ2VØ 4, 3. IC934 (V Driver) and IC931 (H Driver) An H driver and V driver are necessary in order to generate the clocks (vertical transfer clock, horizontal transfer clock and electronic shutter clock) which driver the CCD. IC934 is V driver. In addition the XV1-XV4 signals which are output from IC102 are the vertical transfer clocks, and the XSG sig- nal which is output from IC102 is superimposed onto XV1 and XV3 at IC934 in order to generate a ternary pulse. In addition, the XSUB signal which is output from IC102 is used as the sweep pulse for the electronic shutter. A H driver is inside IC931, and H1, H2 and RG clock are generated at IC931. 4. IC931 (CDS, AGC Circuit and A/D Converter) The video signal which is output from the CCD is input to Pin (29) of IC931. There are inside the sampling hold block, AGC block and A/D converter block. The setting of sampling phase and AGC amplifier is carried out by serial data at Pin (37) of IC911. The video signal is carried out A/D converter, and is output by 12-bit. VRT VRB

VREF

2~36 dB CCDIN CDS PxGA VGA ADC DOUT CLAMP CLAMP

INTERNAL

CLOCKS CLPOB

CLPDM PBLK

RG HORIZONTAL PRECISION4 H1-H4 DRIVERS TIMING CLI

CORE

SYNC INTERNAL GENERATOR REGISTERS HD VD SL SCK SDATA Fig. 1-2. IC931 Block Diagram – 3 –, 1-2. CA2 CIRCUIT DESCRIPTION 1. Circuit Description 2. Outline of Operation 1-1. Digital clamp When the shutter opens, the reset signals (ASIC and CPU) The optical black section of the CCD extracts averaged val- and the serial signals (“take a picture” commands) from the ues from the subsequent data to make the black level of the 8-bit microprocessor are input and operation starts. CCD output data uniform for each line. The optical black sec- When the TG/SG drives the CCD, picture data passes through tion of the CCD averaged value for each line is taken as the the A/D and CDS, and is then input to the ASIC as 12-bit sum of the value for the previous line multiplied by the coeffi- data. The AF, AE, AWB, shutter, and AGC value are com- cient k and the value for the current line multiplied by the puted from this data, and three exposures are made to obtain coefficient 1-k. the optimum picture. The data which has already been stored in the SDRAM is read by the CPU and color generation is 1-2. Signal processor carried out. Each pixel is interpolated from the surrounding 1. γ correction circuit data as being either Ye, Cy, Mg or B primary color data to This circuit performs (gamma) correction in order to maintain produce R, G and B data. At this time, correction of the lens a linear relationship between the light input to the camera distortion which is a characteristic of wide-angle lenses is and the light output from the picture screen. carried out. After AWB and γ processing are carried out, a matrix is generated and aperture correction is carried out for 2. Color generation circuit the Y signal, and the data is then compressed by JPEG and This circuit converts the CCD data into RGB signals. is then written to card memory (smart media). When the data is to be output to an external device, it is taken 3. Matrix circuit data from the memory and output via the USART. When played This circuit generates the Y signals, R-Y signals and B-Y sig- back on the LCD and monitor, data is transferred from memery nals from the RGB signals. to the SDRAM, and the image is then elongated so that it is displayed over the SDRAM display area. 4. Horizontal and vertical aperture circuit This circuit is used gemerate the aperture signal. 3. LCD Block During monitoring, YUV conversion is carried out for the 12- 1-3. AE/AWB and AF computing circuit bit CCD data which is input from the A/D conversion block to The AE/AWB carries out computation based on a 64-segment the ASIC and is then transferred to the DRAM so that the screen, and the AF carries out computations based on a 6- CCD data can be displayed on the LCD. segment screen. The data which has accumulated in the DRAM is passed through the NTSC encoder , and after D/A conversion is car- 1-4. SDRAM controller ried out to change the data into a Y/U/V signal, the data is This circuit outputs address, RAS, CAS and AS data for con- sent to the LCD panel and displayed. trolling the SDRAM. It also refreshes the SDRAM. If the shutter button is pressed in this condition, the 12-bit data which is output from the A/D conversion block of the 1-5. Communication control CCD is sent to the DRAM (DMA transfer), and after proces- 1. SIO sor, it is displayed on the LCD as a freeze-frame image. This is the interface for the 8-bit microprocessor. During playback, the JPEG image data which has accumu- lated in the flash memory is converted to YUV signals, and 2. PIO/PWM/SIO for LCD then in the same way as during monitoring, it is passed through 8-bit parallel input and output makes it possible to switch be- the NTSC endoder, and after D/A conversion is carried out to tween individual input/output and PWM input/output. change the data into a Y/U/V signal, the data is sent to the LCD panel and displayed. 1-6. TG/SG The three analog signals (Y/U/V signals) from the ASIC are Timing generated for 4 million pixel CCD control. converted into RGB signals by the LCD driver, and these RGB signals and the control signal which is output by the LCD driver 1-7. Digital encorder are used to drive the LCD panel. The RGB signals are 1H It generates chroma signal from color difference signal. transposed so that no DC component is present in the LCD element, and the two horizontal shift register clocks drive the horizontal shift registers inside the LCD panel so that the 1H transposed RGB signals are applied to the LCD panel. Be- cause the LCD closes more as the difference in potential be- tween the COM (common polar voltage: fixed at DC) and the R, G and B signals becomes greater, the display becomes darker; if the difference in potential is smaller, the element opens and the LCD become brighter. – 4 –, 1-3. PW1 POWER CIRCUIT and LENS DRIVE

BLOCK DESCRIPTION

7. LED Backlight Power Output 1. Outline A constant current flows to the backlight LEDs. Feedback for This is the main power circuit, and is comprised of the follow- the voltage of R5098 is provided to the power controller (Pin ing blocks. (2) of IC501) so that PWM control can be carried out. Switching power controller (IC501) Analog system power output (Q5001, T5001) 8. 5 V and LCD System Power Output Digital 1.8 V power output (Q5009, L5008) 5 V is output. Feedback for the5Vis provided to the swiching Digital 3.3 V power output (Q5010, L5009) controller (Pin (4) of IC501) so that PWM control can be car- Digital 3.3 V step-up power output (Q5011, L5010) ried out. And also this CH6 pulse is carried out voltage dou- LED backlight power output (Q5012, L5011) bler so that 9.9 V (L) for LCD is output. 5 V and LCD system power output (Q5015, L5012) 9. Lens drive block 2. Switching Controller 9-1. Iris drive This is the basic circuit which is necessary for controlling the When the drive signals (IRIS_A, IRIS_/A, IRIS_B and IRIS_/ power supply for a PWM-type switching regulator, and is pro- B) which are output from the ASIC expansion port (IC105), the vided with six built-in channels, only CH1 (analog system stepping motor is driven by the driver (IC951), and are then power output), CH2 (digital 1.85 V system power output), CH3 used to drive the iris steps. (digital 3.35 V system power output), CH4 (digital 3.35 V step- up power output), CH5 (LED back light power output) and 9-2. Focus drive CH6 (5 V and LCD system power output) are used. Feedback When the drive signals (FIN_A, FIN_-A, FIN_B and FIN_-B) from 15.0 V (A) (CH1), 1.8 V (D) (CH2), 3.3 V (D) (CH3), 4.7 which are output from the ASIC expansion port (IC106), the V (L) (CH4), LED backlight output (CH5) and5V(CH6) power focus stepping motor is driven by the driver (IC951). Detection supply outputs are received, and the PWM duty is varied so of the standard focusing positions is carried out by means of that each one is maintained at the correct voltage setting level. the photointerruptor (FOCUS PI) inside the lens block. 2-1. Short-circuit Protection 9-3. Iris drive If output is short-circuited for the length of time determined The zoom DC motor drive signals (ZIN_A and ZIN_-A) which by the condenser which is connected to Pin (37) of IC501, all are output from the ASIC are used to drive by the motor driver output is turned off. The control signal (P ON) are recontrolled (IC951). Detection of the zoom positions is carried out by means to restore output. of photointerruptor (ZOOM PI) inside the lens block. 3. Analog System Power Output 9-4. Shutter drive 15.0 V (A) and -7.5 V (A) are output. Feedback for the 15.0 V It is driven regular current with the motor driver IC (IC951) by (A) is provided to the switching controller (Pin (40) of IC501) the shutter drive signals (SHUT_A and SHUT_/A) which are so that PWM control can be carried out. output from the ASIC expansion port (IC106). 4. Digital 1.8 V Power Output 1.8 V (D) is output. Feedback for the 1.8 V (D) is provided to the switching controller (Pins (43) of IC501) so that PWM control can be carried out. 5. Digital 3.3 V Power Output 3.3 V (D) is output. Feedback for the 3.3 V (D) is provided to the swiching controller (Pin (45) of IC501) so that PWM con- trol can be carried out. 6. Digital 3.3 V Step-up Power Output 4.7 V is output. Feedback for the 4.7 V is provided to the swiching controller (Pin (47) of IC501) so that PWM control can be carried out. – 5 –]
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