Download: Features • Compatible with MCS-51 Products • 2 Kbytes of Reprogrammable Flash Memory • 2.7 V to6VOperating Range • Fully Static Operation: 0 Hz to 24 MHz

Features

• Compatible with MCS-51 Products • 2 Kbytes of Reprogrammable Flash Memory Endurance: 1,000 Write/Erase Cycles • 2.7 V to6VOperating Range • Fully Static Operation: 0 Hz to 24 MHz • Two-Level Program Memory Lock • 128 x 8-Bit Internal RAM • 15 Programmable I/O Lines • Two 16-Bit Timer/Counters • 8-BitSix Interrupt Sources • Programmable Serial UART Channel • Direct LED Drive Outputs Microcontroller • On-Chip Analog Comparator • Low Power Idle and Power Down Modes with 2 Kbytes

Description Flash

The AT89C2051 is a low-voltage, high-performance CMOS 8-bit microcomputer with 2 Kbytes of Flash programmable and erasable read only memory (PEROM). The device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51 instruction set and pinout. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C2051 is a powerful microcomputer which provides a highly flexible and cost effective solution to many embedded control applications. The AT89C2051 provides the following standard features: 2 Kbytes of Flash, 128 bytes of RAM, 15 I/O lines, two 16-bit timer/counters, a five vector two-level interrupt architecture, a full duplex serial port, a precision analog comparator, on-chip oscilla- tor and clock circuitry. In addition, the AT89C2051 is designed with static logic for operation down to zero frequency and supports two software selectable power sav- ing modes. The Idle Mode stops the CPU while allowing the RAM, timer/counters, serial port and interrupt system to continue functioning. The Power Down Mode saves the RAM contents but freezes the oscillator disabling all other chip functions until the next hardware reset.

Pin Configuration

PDIP/SOIC 0368C 3-17, Block Diagram 3-18 AT89C2051,

Pin Description Oscillator Characteristics

VCC XTAL1 and XTAL2 are the input and output, respectively, Supply voltage. of an inverting amplifier which can be configured for use GND as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive Ground. the device from an external clock source, XTAL2 should Port 1 be left unconnected while XTAL1 is driven as shown in Port 1 is an 8-bit bidirectional I/O port. Port pins P1.2 to Figure 2. There are no requirements on the duty cycle of P1.7 provide internal pullups. P1.0 and P1.1 require exter- the external clock signal, since the input to the internal nal pullups. P1.0 and P1.1 also serve as the positive input clocking circuitry is through a divide-by-two flip-flop, but (AIN0) and the negative input (AIN1), respectively, of the minimum and maximum voltage high and low time specifi- on-chip precision analog comparator. The Port 1 output cations must be observed. buffers can sink 20 mA and can drive LED displays di- rectly. When 1s are written to Port 1 pins, they can be Figure 1. Oscillator Connections used as inputs. When pins P1.2 to P1.7 are used as inputs and are externally pulled low, they will source current (IIL) because of the internal pullups. Port 1 also receives code data during Flash programming and program verification. Port 3 Port 3 pins P3.0 to P3.5, P3.7 are seven bidirectional I/O pins with internal pullups. P3.6 is hard-wired as an input to the output of the on-chip comparator and is not accessible as a general purpose I/O pin. The Port 3 output buffers can sink 20 mA. When 1s are written to Port 3 pins they are pulled high by the internal pullups and can be used as inputs. As inputs, Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups. Port 3 also serves the functions of various special features Notes: C1, C2 = 30 pF ± 10 pF for Crystals of the AT89C2051 as listed below: = 40 pF ± 10 pF for Ceramic Resonators Port Pin Alternate Functions Figure 2. External Clock Drive Configuration P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT0 (external interrupt 0) P3.3 INT1 (external interrupt 1) P3.4 T0 (timer 0 external input) P3.5 T1 (timer 1 external input) Port 3 also receives some control signals for Flash pro- gramming and programming verification.

RST

Reset input. All I/O pins are reset to 1s as soon as RST goes high. Holding the RST pin high for two machine cy- cles while the oscillator is running resets the device. Each machine cycle takes 12 oscillator or clock cycles. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. 3-19,

Special Function Registers

A map of the on-chip memory area called the Special random data, and write accesses will have an indetermi- Function Register (SFR) space is shown in the table be- nate effect. low. User software should not write 1s to these unlisted loca- Note that not all of the addresses are occupied, and unoc- tions, since they may be used in future products to invoke cupied addresses may not be implemented on the chip. new features. In that case, the reset or inactive values of Read accesses to these addresses will in general return the new bits will always be 0. Table 1. AT89C2051 SFR Map and Reset Values 0F8H 0FFH 0F0H B00000000 0F7H 0E8H 0EFH 0E0H ACC00000000 0E7H 0D8H 0DFH 0D0H PSW00000000 0D7H 0C8H 0CFH 0C0H 0C7H 0B8H IPXXX00000 0BFH 0B0H P311111111 0B7H 0A8H IE0XX00000 0AFH 0A0H 0A7H 98H SCON SBUF00000000 XXXXXXXX 9FH 90H P111111111 97H 88H TCON TMOD TL0 TL1 TH0 TH100000000 00000000 00000000 00000000 00000000 00000000 8FH 80H SP DPL DPH PCON00000111 00000000 00000000 0XXX0000 87H 3-20 AT89C2051,

Restrictions on Certain Instructions

The AT89C2051 and is an economical and cost-effective For applications involving interrupts the normal interrupt member of Atmel’s growing family of microcontrollers. It service routine address locations of the 80C51 family ar- contains 2 Kbytes of flash program memory. It is fully com- chitecture have been preserved. patible with the MCS-51 architecture, and can be pro- grammed using the MCS-51 instruction set. However, there are a few considerations one must keep in mind 2. MOVX-related instructions, Data Memory: when utilizing certain instructions to program this device. The AT89C2051 contains 128 bytes of internal data mem- All the instructions related to jumping or branching should ory. Thus, in the AT89C2051 the stack depth is limited to be restricted such that the destination address falls within 128 bytes, the amount of available RAM. External DATA the physical program memory space of the device, which memory access is not supported in this device, nor is ex- is 2K for the AT89C2051. This should be the responsibil- ternal PROGRAM memory execution. Therefore, no ity of the software programmer. For example, LJMP 7E0H MOVX [...] instructions should be included in the program. would be a valid instruction for the AT89C2051 (with 2K of A typical 80C51 assembler will still assemble instructions, memory), whereas LJMP 900H would not. even if they are written in violation of the restrictions men- tioned above. It is the responsibility of the controller user to know the physical features and limitations of the device 1. Branching instructions: being used and adjust the instructions used correspond- LCALL, LJMP, ACALL, AJMP, SJMP, JMP @A+DPTR ingly. These unconditional branching instructions will execute correctly as long as the programmer keeps in mind that the destination branching address must fall within the physical boundaries of the program memory size (loca- tions 00H to 7FFH for the 89C2051). Violating the physi- cal space limits may cause unknown program behavior. CJNE [...], DJNZ [...], JB, JNB, JC, JNC, JBC, JZ, JNZ With these conditional branching instructions the same rule above applies. Again, violating the memory bounda- ries may cause erratic execution. 3-21,

Program Memory Lock Bits Programming The Flash

On the chip are two lock bits which can be left unpro- The AT89C2051 is shipped with the 2 Kbytes of on-chip grammed (U) or can be programmed (P) to obtain the ad- PEROM code memory array in the erased state (i.e., con- ditional features listed in the table below: tents = FFH) and ready to be programmed. The code memory array is programmed one byte at a time. Once the

Lock Bit Protection Modes(1) array is programmed, to re-program any non-blank byte,

the entire memory array needs to be erased electrically. Program Lock Bits Internal Address Counter: The AT89C2051 contains LB1 LB2 Protection Type an internal PEROM address counter which is always reset1UUNo program lock features. to 000H on the rising edge of RST and is advanced by applying a positive going pulse to pin XTAL1. 2PUFurther programming of theFlash is disabled. Programming Algorithm: To program the AT89C2051, the following sequence is recommended. 3PPSame as mode 2, also verifyis disabled. 1. Power-up sequence: Apply power between VCC and GND pins Note: 1. The Lock Bits can only be erased with the Chip Erase Set RST and XTAL1 to GND operation With all other pins floating, wait for greater than 10

Idle Mode milliseconds

2. Set pin RST to ’H’ In idle mode, the CPU puts itself to sleep while all the on- Set pin P3.2 to ’H’ chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the spe- 3. Apply the appropriate combination of ’H’ or ’L’ logic cial functions registers remain unchanged during this levels to pins P3.3, P3.4, P3.5, P3.7 to select one of mode. The idle mode can be terminated by any enabled the programming operations shown in the PEROM interrupt or by a hardware reset. Programming Modes table. To Program and Verify the Array: P1.0 and P1.1 should be set to ’0’ if no external pullups are used, or set to ’1’ if external pullups are used. 4. Apply data for Code byte at location 000H to P1.0 to P1.7. It should be noted that when idle is terminated by a hard- ware reset, the device normally resumes program execu- 5. Raise RST to 12V to enable programming. tion, from where it left off, up to two machine cycles before 6. Pulse P3.2 once to program a byte in the PEROM ar- the internal reset algorithm takes control. On-chip hard- ray or the lock bits. The byte-write cycle is self-timed ware inhibits access to internal RAM in this event, but ac- and typically takes 1.2 ms. cess to the port pins is not inhibited. To eliminate the pos- 7. To verify the programmed data, lower RST from 12V sibility of an unexpected write to a port pin when Idle is to logic ’H’ level and set pins P3.3 to P3.7 to the ap- terminated by reset, the instruction following the one that propiate levels. Output data can be read at the port invokes Idle should not be one that writes to a port pin or P1 pins. to external memory. 8. To program a byte at the next address location, pulse XTAL1 pin once to advance the internal address

Power Down Mode counter. Apply new data to the port P1 pins.

In the power down mode the oscillator is stopped, and the 9. Repeat steps 5 through 8, changing data and advanc- instruction that invokes power down is the last instruction ing the address counter for the entire 2 Kbytes array executed. The on-chip RAM and Special Function Regis- or until the end of the object file is reached. ters retain their values until the power down mode is termi- 10.Power-off sequence: nated. The only exit from power down is a hardware reset. set XTAL1 to ’L’ Reset redefines the SFRs but does not change the on- set RST to ’L’ chip RAM. The reset should not be activated before VCC Float all other I/O pins is restored to its normal operating level and must be held Turn Vcc power off active long enough to allow the oscillator to restart and stabilize. P1.0 and P1.1 should be set to ’0’ if no external pullups are used, or set to ’1’ if external pullups are used. 3-22 AT89C2051, Data Polling: The AT89C2051 features Data Polling to Chip Erase: The entire PEROM array (2 Kbytes) and the indicate the end of a write cycle. During a write cycle, an two Lock Bits are erased electrically by using the proper attempted read of the last byte written will result in the combination of control signals and by holding P3.2 low for complement of the written data on P1.7. Once the write 10 ms. The code array is written with all “1"s in the Chip cycle has been completed, true data is valid on all outputs, Erase operation and must be executed before any non- and the next cycle may begin. Data Polling may begin any blank memory byte can be re-programmed. time after a write cycle has been initiated. Reading the Signature Bytes: The signature bytes are Ready/Busy: The Progress of byte programming can read by the same procedure as a normal verification of also be monitored by the RDY/BSY output signal. Pin locations 000H, 001H, and 002H, except that P3.5 and P3.1 is pulled low after P3.2 goes High during program- P3.7 must be pulled to a logic low. The values returned ming to indicate BUSY. P3.1 is pulled High again when are as follows. programming is done to indicate READY. (000H) = 1EH indicates manufactured by Atmel Program Verify: If lock bits LB1 and LB2 have not been (001H) = 21H indicates 89C2051 programmed code data can be read back via the data lines for verification: Programming Interface 1. Reset the internal address counter to 000H by bring- Every code byte in the Flash array can be written and the ing RST from ’L’ to ’H’. entire array can be erased by using the appropriate com- 2. Apply the appropriate control signals for Read Code bination of control signals. The write operation cycle is data and read the output data at the port P1 pins. self-timed and once initiated, will automatically time itself 3. Pulse pin XTAL1 once to advance the internal address to completion. counter. All major programming vendors offer worldwide support 4. Read the next code data byte at the port P1 pins. for the Atmel microcontroller series. Please contact your 5. Repeat steps 3 and 4 until the entire array is read. local programming vendor for the appropriate software re- The lock bits cannot be verified directly. Verification of the vision. lock bits is achieved by observing that their features are enabled.

Flash Programming Modes

P3.2/ Mode RST PROG P3.3 P3.4 P3.5 P3.7 Write Code Data(1,3) 12VLHHHRead Code Data(1) HHLLHHWrite Lock Bit - 1 12VHHHHBit - 2 12VHHLL(2) Chip Erase 12VHLLLRead Signature ByteHHLLLLNotes: 1. The internal PEROM address counter is reset to 000H 2. Chip Erase requires a 10 ms PROG pulse. on the rising edge of RST and is advanced by a posi- 3. P3.1 is pulled Low during programming to indicate tive pulse at XTAL1 pin. RDY/BSY\. 3-23, Figure 3. Programming the Flash Memory Figure 4. Verifying the Flash Memory

Flash Programming and Verification Characteristics

TA = 21°C to 27°C, VCC = 5.0 ± 10% Symbol Parameter Min Max Units VPP Programming Enable Voltage 11.5 12.5 V IPP Programming Enable Current 250 µA tDVGL Data Setup to PROG Low 1.0 µs tGHDX Data Hold After PROG 1.0 µs tEHSH P3.4 (ENABLE) High to VPP 1.0 µs tSHGL VPP Setup to PROG Low 10 µs tGHSL VPP Hold After PROG 10 µs tGLGH PROG Width 1 110 µs tELQV ENABLE Low to Data Valid 1.0 µs tEHQZ Data Float After ENABLE 0 1.0 µs tGHBL PROG High to BUSY Low 50 ns tWC Byte Write Cycle Time 2.0 ms tBHIH RDY/BSY\ to Increment Clock Delay 1.0 µs tIHIL Increment Clock High 200 ns Note: 1. Only used in 12-volt programming mode. 3-24 AT89C2051,

Flash Programming and Verification Waveforms Absolute Maximum Ratings*

*NOTICE: Stresses beyond those listed under “Absolute Maxi- Operating Temperature... -55°C to +125°C mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the Storage Temperature... -65°C to +150°C device at these or any other conditions beyond those indi- Voltage on Any Pin cated in the operational sections of this specification is not with Respect to Ground ... -1.0 V to +7.0 V implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage ... 6.6 V DC Output Current ... 25.0 mA 3-25,

D.C. Characteristics

TA = -40°C to 85°C, VCC = 2.7 V to 6.0 V (unless otherwise noted) Symbol Parameter Condition Min Max Units VIL Input Low Voltage -0.5 0.2 VCC-0.1 V VIH Input High Voltage (Except XTAL1, RST) 0.2 VCC+0.9 VCC+0.5 V VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC+0.5VVOutput Low Voltage (1) IOL = 20 mA, VCC = 5 V OL (Ports 1, 3) I = 10 mA, V = 2.7 V 0.5 VOL CC IOH = -80 µA, VCC = 5 V ± 10% 2.4VVOutput High VoltageOH (Ports 1, 3) IOH = -30 µA 0.75 VCC V IOH = -12 µA 0.9 VCCVILogical 0 Input CurrentIL (Ports 1, 2, 3) VIN = 0.45 V -50 µA I Logical 1 to 0 TransitionTL Current (Ports 1, 2, 3) VIN = 2 V -750 µA I Input Leakage Current LI (Port P1.0, P1.1) 0 < VIN < VCC ±10 µA V Comparator Input OffsetOS Voltage VCC = 5 V 20 mV V Comparator InputCM Common Mode Voltage 0 VCC V RRST Reset Pulldown Resistor 50 300 KΩ CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF Active Mode, 12 MHz, VCC = 6 V/3 V 15/5.5 mA Power Supply Current Idle Mode, 12 MHz, VCC = 6 V/3 V ICC P1.0 & P1.1 = 0V or V 5/1 mA

CC

Power Down Mode(2) VCC = 6 V P1.0 & P1.1 = 0V or VCC 100 µA VCC = 3 V P1.0 & P1.1 = 0V or VCC 20 µA Notes: 1. Under steady state (non-transient) conditions, IOL If IOL exceeds the test condition, VOL may exceed the must be externally limited as follows: related specification. Pins are not guaranteed to sink Maximum IOL per port pin:20 mA current greater than the listed test conditions. Maximum total IOL for all output pins:80 mA 2. Minimum VCC for Power Down is 2 V. 3-26 AT89C2051,

External Clock Drive Waveforms External Clock Drive

Symbol Parameter VCC = 2.7 V to 6.0 V VCC = 4.0 V to 6.0 V Units Min Max Min Max 1/tCLCL Oscillator Frequency 0 12 0 24 MHz tCLCL Clock Period 83.3 41.6 ns tCHCX High Time 30 15 ns tCLCX Low Time 30 15 ns tCLCH Rise Time 20 20 ns tCHCL Fall Time 20 20 ns 3-27,

Serial Port Timing: Shift Register Mode Test Conditions

(VCC = 5.0 V ± 20%; Load Capacitance = 80 pF) 12 MHz Osc Variable Oscillator Symbol Parameter Min Max Min Max Units tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-33 ns tXHDX Input Data Hold After Clock Rising Edge00ns tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133 ns

Shift Register Mode Timing Waveforms AC Testing Input/Output Waveforms (1) Float Waveforms (1)

Note: 1. AC Inputs during testing are driven at VCC - 0.5 V for a Note: 1. For timing purposes, a port pin is no longer floating logic 1 and 0.45 V for a logic 0. Timing measure- when a 100 mV change from load voltage occurs. ments are made at VIH min. for a logic 1 and VIL A port pin begins to float when a 100 mV change max. for a logic 0. from the loaded VOH/VOL level occurs. 3-28 AT89C2051,

AT89C2051

TYPICAL ICC - ACTIVE (85°C) Vcc=6.0V I 15 C Vcc=5.0V C 10 Vcc=3.0VmA50612 18 24 FREQUENCY (MHz)

AT89C2051

TYPICAL ICC - IDLE (85°C) Vcc=6.0V

I

C 2 Vcc=5.0V

C

m 1

A

Vcc=3.0V036912 FREQUENCY (MHz) 3-29,

AT89C2051 TYPICAL ICC vs. VOLTAGE- POWER DOWN (85°C) I 15 C C 10

µ

A 5

3.0V 4.0V 5.0V 6.0V

Vcc VOLTAGE

Note: 1. XTAL1 tied to GND for ICC (power down). 2. P.1.0 and P1.1 = VCC or GND. 3. Lock bits programmed. 3-30 AT89C2051,

Ordering Information

Speed Power (MHz) Supply Ordering Code Package Operation Range 12 2.7 V to 6.0 V AT89C2051-12PC 20P3 Commercial AT89C2051-12SC 20S (0°C to 70°C) AT89C2051-12PI 20P3 Industrial AT89C2051-12SI 20S (-40°C to 85°C) 24 4.0 V to 6.0 V AT89C2051-24PC 20P3 Commercial AT89C2051-24SC 20S (0°C to 70°C) AT89C2051-24PI 20P3 Industrial AT89C2051-24SI 20S (-40°C to 85°C) Package Type 20P3 20 Lead, 0.300" Wide, Plastic Dual In-line Package (PDIP) 20S 20 Lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC) 3-31]

15