Download: OUTLINE OF CIRCUIT DESCRIPTION 1-1. CA1 and A PART OF CA2 CIRCUIT DESCRIPTIONS Around CCD block 10987654321

OUTLINE OF CIRCUIT DESCRIPTION 1-1. CA1 and A PART OF CA2 CIRCUIT DESCRIPTIONS Around CCD block 109876543211. IC Configuration CA1 board IC903 (ICX274AQ) CCD imagerGBGBIC901, IC902 (CXD3400N) V driverRGRGCA2 boardGBGBRGRGIC911 (H driver, CDS, AGC and A/D converter) GBGBRGRG2. IC903 (CCD imager) GBGBRGRG(Note) [Structure] Horizontal register Interline type CCD image sensor Image size Diagonal 8.293 mm (1/1.8 type) Pixels in total 1688 (H) x 1248 (V) 11 12 13 14 15 16 17 18 19 20 Recording pixels 1600 (H) x 1200 (V) (Note) : Photo sensor Fig. 1-1. CCD Block Diagram Pin No. Symbol Pin Descripti...
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OUTLINE OF CIRCUIT DESCRIPTION 1-1. CA1 and A PART OF CA2 CIRCUIT

DESCRIPTIONS Around CCD block 10987654321

1. IC Configuration CA1 board IC903 (ICX274AQ) CCD imagerGBGBIC901, IC902 (CXD3400N) V driverRGRGCA2 boardGBGBRGRGIC911 (H driver, CDS, AGC and A/D converter) GBGBRGRG2. IC903 (CCD imager) GBGBRGRG(Note) [Structure] Horizontal register Interline type CCD image sensor Image size Diagonal 8.293 mm (1/1.8 type) Pixels in total 1688 (H) x 1248 (V) 11 12 13 14 15 16 17 18 19 20 Recording pixels 1600 (H) x 1200 (V) (Note) : Photo sensor Fig. 1-1. CCD Block Diagram Pin No. Symbol Pin Description Pin No. Symbol Pin Description 1 Vø4 Vertical register transfer clock 11 VDD Circuit power 2 Vø3A Vertical register transfer clock 12 øRG Reset gate clock 3 Vø3B Vertical register transfer clock 13 Hø2B Horizontal register transfer clock 4 Vø3C Vertical register transfer clock 14 Hø1B Horizontal register transfer clock 5 Vø2A Vertical register transfer clock 15 GND GND 6 Vø2B Vertical register transfer clock 16 øSUB Substrate clock 7 Vø2C Vertical register transfer clock 17 CSUB Substrate bias 8 Vø1 Vertical register transfer clock 18 VL Protection transistor bias 9 GND GND 19 Hø1A Horizontal register transfer clock 10 VOUT Signal output 20 Hø2A Horizontal register transfer clock Table 1-1. CCD Pin Description 3. IC901, IC902 (V Driver) and IC911 (H Driver) An H driver and V driver are necessary in order to generate the clocks (vertical transfer clock, horizontal transfer clock and electronic shutter clock) which driver the CCD. IC901 and IC902 are V driver. In addition the XV1-XV4 sig- nals which are output from IC102 are the vertical transfer clocks, and the XSG signal which is output from IC102 is su- perimposed onto XV2 and XV3 at IC901 and IC902 in order to generate a ternary pulse. In addition, the XSUB signal which is output from IC102 is used as the sweep pulse for the elec- tronic shutter. A H driver is inside IC911, and H1A, H1B, H2A, H2B and RG clock are generated at IC911. – 2 – VDD VOUT

GND

Vertical register

GND CSUB VL

, 4. IC911 (CDS, AGC Circuit and A/D Converter) 5. Lens drive block The video signal which is output from the CCD is input to Pin 5-1. Iris and shutter drive (29) of IC911. There are inside the sampling hold block, AGC When the drive signals (IRSTB, ICW, IOEB and ICLK) which block and A/D converter block. are output from the ASIC, the stepping motor is sine-wave The setting of sampling phase and AGC amplifier is carried driven by the micro-step motor driver (IC952), and are then out by serial data at Pin (37) of IC911. The video signal is used to drive the iris steps and open/close the shutter. carried out A/D converter, and is output by 12-bit. 5-2. Focus drive VRT VRB When the drive signals (FRSTB, FCW, FOEB and FCLK) which are output from the ASIC, the focus stepping motor is sine- wave driven by the micro-step motor driver (IC951). Detection

VREF

2~36 dB of the standard focusing positions is carried out by means of CDS PxGA VGA ADC DOUT the photointerruptor (FOCUS PI) inside the lens block.CCDIN CLAMP CLAMP 5-3. Iris drive

INTERNAL

CLOCKS CLPOB The zoom stepping motor drive signals (ZIN1, ZIN2, ZIN3 and CLPDM ZIN4) which are output from the ASIC are used to drive by the

PBLK

RG HORIZONTAL PRECISION motor driver (IC953). Detection of the zoom positions is car-4 TIMING CLI H1-H4 DRIVERS CORE ried out by means of photointerruptor (ZOOM PI) inside the lens block. SYNC INTERNAL GENERATOR REGISTERS HD VD SL SCK SDATA Fig. 1-2. IC911 Block Diagram – 3 –, 1-2. CA2 CIRCUIT DESCRIPTION 1. Circuit Description 1-8. 8-bit D/A circuit (Audio) 1-1. Scannning converter (Interlace converter) This circuit converts the audio signals (analog signals) from This circuit uses the function of a 128-Mbit SDRAMs to con- the microphone to 8-bit digital signals. vert the non-interlaced signal which is output from the CCD into an interlaced signal for the video monitor. 1-9. 8-bit A/D circuit (Audio) The audio signals which were converted to digial form by the 1-2. Camera signal processor 8-bit A/D circuit are temporarily to a sound buffer and then This comprises circuits such as the digial clamp circuit, white recorded in the SSFDC card. During playback, the 8-bit D/A balance circuit, γ circuit, color signal generation circuit, ma- circuit converts these signals into analog audio signals. trix circuit and horizontal aperture circuit. 1-10. Sound buffer 1. Digital clamp circuit Audio memory The optical black section of the CCD extracts 16-pixel aver- aged values from the subsequent data to make the black level 1-11. LCD driver of the CCD output data uniform for each line. The 16-pixel The Y/C signals which are input to the LCD driver are con- averaged value for each line is taken as the sum of the value verted to RGB signals, and the timing signal which is neces- for the previous line multiplied by the coefficient k and the sary for LCD monitor display and the RGB signals are then value for the current line multiplied by the coefficient 1-k. supplied to the LCD monitor. 2. White balance circuit 1-12. LCD monitor This circuit controls the white balance by using the AWB judge- This is the image display device which displays the image ment value computed by the CPU to control the gain for each signals supplied from the LCD driver. R, G and B pixel based on the CCD data which has been read. 1-13. Memory card control This reads data from the memory card and stores it in SDRAM, 3. γ circuit and writes out the image data stored in SDRAM. In addition, This circuit performs (gamma) correction in order to maintain error correction is carried out when the data is read. a linear relationship between the light input to the camera and the light output from the picture screen. 1-14. MJPEG compression Still and continuous frame data is converted to JPEG format, 4. Color generation circuit and movie images are compressed and expanded in MJPEG This circuit converts the CCD data into RGB signals. format. 5. Matrix circuit 2. Outline of Operation This circuit generates the Y signals, R-Y signals and B-Y sig- When the shutter opens, the reset signals, TEST0, TEST1 nals from the RGB signals. and the serial signals (“take a picture” commands) from the 8-bit microprocessor are input and record operation starts. 6. Horizontal aperture circuit When the TG drives the CCD, picture data passes through This circuit is used generate the aperture signal. the A/D and is then input to the ASIC as 10-bit data. This data then passes through the DCLP, AWB, shutter and γ circuit, 1-3. SDRAM controller after which it is input to the SDRAM. The AWB, shutter, γ, and This circuit outputs address, RAS, CAS and AS data for con- AGC value are computed from this data, and two exposures trolling the SDRAM. It also refreshes the SDRAM. are made to obtain the optimum picture. The data which has already been stored in the SDRAM is read by the CPU and 1-4. PIO color generation is carried out. Each pixel is interpolated from The expansion parallel port can be used for functions such the surrounding data as being either R, G or B primary color as stroboscope control and LCD driver control. data to produce R, G and B data. At this time, correction of the lens distortion which is a characteristic of wide-angle 1-5. SIO (Serial control) lenses is carried out. Aperture correction is carried out, and This is the interface for the 4-bit microprocessor. in case of still picture the data is then compressed by the JPEG method and in case of picture it is compressed by 1-6. USB control MJPEG method and is written to compact flash card. When This is comunicated PC with 12 Mbps. the data is to be output to an external device, it is read JPEG picture data from the compact flash card and output to PC via 1-7. TG, SG block the USB. This is the timing generation circuit which generates the clocks (vertical transfer clock and electronic shutter clock) which drive the CCD. – 4 –, 3. LCD Block During EE, gamma conversion is carried out for the 10-bit RGB data which is input from the A/D conversion block of the CCD to the ASIC in order that the γ revised can be displayed on the video. The YUV of 640 x 480 is then transferred to the SVRAM. The data which has accumulated in the SDRAM is after D/A conversion is carried out by SDRAM control circuit inside the ASIC, makes Y/C signal, the data is sent to the LCD panel and displayed. If the shutter button is pressed in this condition, the 10-bit data which is output from the A/D conversion block of the CCD is sent to the SDRAM (DMA transfer), and is displayed on the LCD as a freeze-frame image. During playback, the JPEG image data which has accumu- lated in the compact flash card is converted to RGB signals. In the same way as for EE, the data is then sent to the SDRAM, after which D/A conversion is carried out inside the ASIC, and then the data is sent to the LCD panel and displayed. The LCD driver is converted Y/C signals to RGB signals from ASIC, and these RGB signals and the control signal which is output by the LCD driver are used to drive the LCD panel. The RGB signals are 1H transposed so that no DC compo- nent is present in the LCD element, and the two horizontal shift register clocks drive the horizontal shift registers inside the LCD panel so that the 1H transposed RGB signals are applied to the LCD panel. Because the LCD closes more as the difference in potential between the VCOM (common polar voltage: fixed at DC) and the R, G and B signals becomes greater, the display becomes darker; if the difference in potential is smaller, the element opens and the LCD become brighter. In addition, the bright- ness and contrast settings for the LCD can be varied by means of the serial data from the ASIC. – 5 –, 1-3. CA3 CIRCUIT DESCRIPTION 1. Outline 3. Lens system 3.4 V Power Output This is the main CA3 power block, and is comprised of the 3.4 V (D) C is output for lens. Feedback is provided to the following blocks. swiching controller (Pin (1) of IC511) so that PWM control Switching controller (IC511) can be carried out. Also when this power output is ON and Lens system 3.4 V power output (L5101, Q5102, D5101, OFF, Q5124 turns on and it rises to 3.7 V output. C5114) Backlight power output (L5103, Q5106, C5121) 4. Backlight Power Output Analog and LCD system power output (Q5112, T5101) 10 mA (L) is output. The backlighting turns on when current flows in the direction from pin (1) to pin (2) of CN531. At this 2. Switching Controller (IC511) time, a feedback signal is sent from pin (2) of CN531 to pin This is the basic circuit which is necessary for controlling the (12) of IC511 through R5137 so that PWM control is carried power supply for a PWM-type switching regulator, and is pro- out to keep the current at a constant level (10 mA). vided with four built-in channels. They are CH1 (lens system 3.4 V), CH2 (backlight) and CH4 (analog and LCD system). 5. Analog and LCD System Power Output CH3 is not used. Feedback from 3.4 V (D) C (CH1), +15.0 V 15.0 V (A), –7.7 V (A), 12.4 V (L) and 15 V (L) are output. (A) or +12.4 V (L) power supply output are received, and the Feedback for the 15.0 V (A) with view mode and 12.4 V (L) PWM duty is varied so that each one is maintained at the with play mode is provided to the switching controller (Pin correct voltage setting level. CH2 is feedback from 10 mA (36) of IC511) so that PWM control can be carried out. power supply output are received, and the PWM duty is var- ied so that each one is maintained at the correct voltage set- ting level. 2-1. Short-circuit protection circuit If output is short-circuited for the length of time determined by the condenser which is connected to Pin (33) of IC511, all output is turned off. The control signal (P(A) ON and LCD ON) are recontrolled to restore output. – 6 –]
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