Download: OUTLINE OF CIRCUIT DESCRIPTION 1-1. CA1 and A PART OF CA2 CIRCUIT DESCRIPTIONS Around CCD block 10987654321

OUTLINE OF CIRCUIT DESCRIPTION 1-1. CA1 and A PART OF CA2 CIRCUIT DESCRIPTIONS Around CCD block 109876543211. IC Configuration CA1 board IC901 (ICX274AQ) CCD imagerGBGBCA2 boardRGRGIC901 (H driver, CDS, AGC and A/D converter) GBGBRGRGGBGB2. IC901 (CA1) (CCD imager) RGRG[Structure] GBGBRGRG(Note) Interline type CCD image sensor Horizontal register Image size Diagonal 8.293 mm (1/1.8 type) Pixels in total 1688 (H) x 1248 (V) Recording pixels 1600 (H) x 1200 (V) 11 12 13 14 15 16 17 18 19 20 (Note) : Photo sensor Fig. 1-1. CCD Block Diagram Pin No. Symbol Pin Description Pin No. Symbol Pin Desc...
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OUTLINE OF CIRCUIT DESCRIPTION 1-1. CA1 and A PART OF CA2 CIRCUIT

DESCRIPTIONS Around CCD block 10987654321

1. IC Configuration CA1 board IC901 (ICX274AQ) CCD imagerGBGBCA2 boardRGRGIC901 (H driver, CDS, AGC and A/D converter) GBGBRGRGGBGB2. IC901 (CA1) (CCD imager) RGRG[Structure] GBGBRGRG(Note) Interline type CCD image sensor Horizontal register Image size Diagonal 8.293 mm (1/1.8 type) Pixels in total 1688 (H) x 1248 (V) Recording pixels 1600 (H) x 1200 (V) 11 12 13 14 15 16 17 18 19 20 (Note) : Photo sensor Fig. 1-1. CCD Block Diagram Pin No. Symbol Pin Description Pin No. Symbol Pin Description 1 Vø4 Vertical register transfer clock 11 VDD Circuit power 2 Vø3A Vertical register transfer clock 12 øRG Reset gate clock 3 Vø3B Vertical register transfer clock 13 Hø2B Horizontal register transfer clock 4 Vø3C Vertical register transfer clock 14 Hø1B Horizontal register transfer clock 5 Vø2A Vertical register transfer clock 15 GND GND 6 Vø2B Vertical register transfer clock 16 øSUB Substrate clock 7 Vø2C Vertical register transfer clock 17 CSUB Substrate bias 8 Vø1 Vertical register transfer clock 18 VL Protection transistor bias 9 GND GND 19 Hø1A Horizontal register transfer clock 10 VOUT Signal output 20 Hø2A Horizontal register transfer clock Table 1-1. CCD Pin Description 3. IC904 (V Driver) and IC901 (CA2 board) (H driver) An H driver and V driver are necessary in order to generate VRT VRB the clocks (vertical transfer clock, horizontal transfer clock and electronic shutter clock) which driver the CCD. VREF 2~36 dB IC904 are V driver. In addition the XV1-XV4 signals which are 12 output from IC102 are the vertical transfer clocks, and the CCDIN CDS PxGA VGA ADC DOUT XSG signal which is output from IC102 is superimposed onto

CLAMP

XV2 and XV3 at IC902 in order to generate a ternary pulse. CLAMPINTERNAL CLOCKS CLPOB In addition, the XSUB signal which is output from IC102 is CLPDM used as the sweep pulse for the electronic shutter. A H driver PBLK RG PRECISION is inside IC901 (CA2 board), and H1A, H1B, H2A, H2B and 4 HORIZONTAL TIMING CLIH1-H4 DRIVERS CORE RG clock are generated at IC901 (CA2 board). SYNC INTERNAL 4. IC901 (CA2 board) GENERATOR REGISTERS (CDS, AGC Circuit and A/D Converter) HD VD SL SCK SDATA The video signal which is output from the CCD is input to Pin (29) of IC901 (CA2 board). There are inside the sampling hold block, AGC block and A/D converter block. Fig. 1-2. IC901 Block Diagram The setting of sampling phase and AGC amplifier is carried out by serial data at Pin (37) of IC911. The video signal is carried out A/D converter, and is output by 10-bit. – 2 – VDD VOUT

GND

Vertical register

GND CSUB VL

, 1-2. CA2 CIRCUIT DESCRIPTION 1. Circuit Description 1-8. Sound buffer 1-1. Scannning converter (Interlace converter) Audio memory This circuit uses the function of a 128-Mbit SDRAMs to con- vert the non-interlaced signal which is output from the CCD 1-9. LCD driver into an interlaced signal for the video monitor. The 8-bit digital YUV signals which are input to the LCD driver are converted to RGB signals, and the timing signal which is 1-2. Camera signal processor necessary for LCD monitor display and the RGB signals are This comprises circuits such as the digial clamp circuit, white then supplied to the LCD monitor. balance circuit, γ circuit, color signal generation circuit, ma- trix circuit and horizontal aperture circuit. 1-10. LCD monitor This is the image display device which displays the image 1. Digital clamp circuit signals supplied from the LCD driver. The optical black section of the CCD extracts 16-pixel aver- aged values from the subsequent data to make the black level 1-11. Memory card control of the CCD output data uniform for each line. The 16-pixel This reads data from the memory card and stores it in SDRAM, averaged value for each line is taken as the sum of the value and writes out the image data stored in SDRAM. In addition, for the previous line multiplied by the coefficient k and the error correction is carried out when the data is read. value for the current line multiplied by the coefficient 1-k. 1-12. MJPEG compression 2. White balance circuit Still and continuous frame data is converted to JPEG format, This circuit controls the white balance by using the AWB judge- and movie images are compressed and expanded in MJPEG ment value computed by the CPU to control the gain for each format. R, G and B pixel based on the CCD data which has been read. 2. Outline of Operation When the shutter opens, the reset signals, ZTEST0, ZTEST1, 3. γ circuit ZTEST2 signals and the serial signals (“take a picture” com- This circuit performs (gamma) correction in order to maintain mands) from the 8-bit microprocessor are input and record a linear relationship between the light input to the camera operation starts. When the TG drives the CCD, picture data and the light output from the picture screen. passes through the A/D and is then input to the ASIC as 10- bit data. This data then passes through the DCLP, AWB, shutter 4. Color generation circuit and γ circuit, after which it is input to the SDRAM. The AWB, This circuit converts the CCD data into RGB signals. shutter, γ, and AGC value are computed from this data, and two exposures are made to obtain the optimum picture. The 5. Matrix circuit data which has already been stored in the SDRAM is read by This circuit generates the Y signals, R-Y signals and B-Y sig- the CPU and color generation is carried out. Each pixel is nals from the RGB signals. interpolated from the surrounding data as being either R, G or B primary color data to produce R, G and B data. At this 6. Horizontal aperture circuit time, correction of the lens distortion which is a characteristic This circuit is used generate the aperture signal. of wide-angle lenses is carried out. Aperture correction is car- ried out, and in case of still picture the data is then compressed 1-3. SDRAM controller by the JPEG method and in case of picture it is compressed This circuit outputs address, RAS, CAS and AS data for con- by MJPEG method and is written to compact flash card. When trolling the SDRAM. It also refreshes the SDRAM. the data is to be output to an external device, it is read JPEG picture data from the compact flash card and output to PC via 1-4. PIO the USB. The expansion parallel port can be used for functions such as stroboscope control and LCD driver control. 1-5. SIO (Serial control) This is the interface for the 4-bit microprocessor. 1-6. USB control This is comunicated PC with 12 Mbps. 1-7. TG, SG block This is the timing generation circuit which generates the clocks (vertical transfer clock and electronic shutter clock) which drive the CCD. – 3 –, 3. LCD Block During EE, gamma conversion is carried out for the 10-bit RGB data which is input from the A/D conversion block of the CCD to the ASIC in order that the γ revised can be displayed on the video. The YUV of 640 x 480 is then transferred to the SVRAM. The data which has accumulated in the SDRAM is converted to digital YUV signal in conformity to ITUR-601 inside the ASIC by SDRAM control circuit inside the ASIC, the data is sent to the LCD driver IC and displayed the image to LCD panel. If the shutter button is pressed in this condition, the 10-bit data which is output from the A/D conversion block of the CCD is sent to the SDRAM (DMA transfer), and is displayed on the LCD as a freeze-frame image. During playback, the JPEG image data which has accumu- lated in the compact flash card is converted to YUV signals. In the same way as for EE, the data is then sent to the SDRAM, converted to digital YUV signal in conformity to ITUR-601 in- side the ASIC, the data is sent to the LCD driver IC and dis- played the image to LCD panel. The LCD driver is converted digital YUV signals to RGB sig- nals from ASIC, and these RGB signals and the control sig- nal which is output by the LCD driver are used to drive the LCD panel. The RGB signals are 1H transposed so that no DC component is present in the LCD element, and the two horizontal shift register clocks drive the horizontal shift regis- ters inside the LCD panel so that the 1H/1V transposed RGB signals are applied to the LCD panel. Because the LCD closes more as the difference in potential between the VCOM (common polar voltage: AC drive) and the R, G and B signals becomes greater, the display becomes darker; if the difference in potential is smaller, the element opens and the LCD become brighter. In addition, the bright- ness and contrast settings for the LCD can be varied by means of the serial data from the ASIC. – 4 –, 1-3. PW1 POWER CIRCUIT and LENS DRIVE

BLOCK DESCRIPTION

1. Outline 7. LED Backlight Power Output This is the main power circuit, and is comprised of the follow- A constant current flows to the backlight LEDs. Feedback for ing blocks. the voltage of R5098 is provided to the power controller (Pin Switching power controller (IC501) (2) of IC501) so that PWM control can be carried out. Analog and LCD system power output (Q5001, T5001) Digital 1.85 V power output (Q5009, L5008) 8. 5 V System Power Output Digital 3.35 V power output (Q5010, L5009) 5 V is output. Feedback for the5Vis provided to the swiching Digital 3.35 V step-up power output (Q5011, L5010) controller (Pin (4) of IC501) so that PWM control can be car- LED backlight power output (Q5012, L5011) ried out. 5 V system power output (Q5015, L5012) 9. Lens drive block 2. Switching Controller 9-1. Iris drive This is the basic circuit which is necessary for controlling the When the drive signals (IRIS_A, IRIS_/A, IRIS_B and IRIS_/ power supply for a PWM-type switching regulator, and is pro- B) which are output from the ASIC, the stepping motor is driven vided with six built-in channels, only CH1 (analog and LCD by the driver (IC951), and are then used to drive the iris steps. system power output), CH2 (digital 1.85 V system power out- put), CH3 (digital 3.35 V system power output), CH4 (digital 9-2. Focus drive 3.35 V step-up power output), CH5 (LED back light power When the drive signals (FRSTB, FCW, FOEB and FCLK) which output) and CH6 (5 V system power output) are used. Feed- are output from the ASIC, the focus stepping motor is sine- back from 15.0 V (A) (CH1), 1.85 V (D) (CH2), 3.35 V (D) wave driven by the micro-step motor driver (IC953). Detection (CH3), 4.7 V (L) (CH4), LED backlight output (CH5) and5Vof the standard focusing positions is carried out by means of (CH6) power supply outputs are received, and the PWM duty the photointerruptor (FOCUS PI) inside the lens block. is varied so that each one is maintained at the correct voltage setting level. 9-3. Iris drive The zoom DC motor drive signals (ZOOM_A and ZOOM_/A) 2-1. Short-circuit Protection which are output from the ASIC are used to drive by the motor If output is short-circuited for the length of time determined driver (IC951). Detection of the zoom positions is carried out by the condenser which is connected to Pin (37) of IC501, all by means of photointerruptor (ZOOM PI) inside the lens block. output is turned off. The control signal (P ON) are recontrolled to restore output. 9-4. Shutter drive When the shutter drive signals (SHUT_A and SHUT_/A) which 3. Analog and LCD System Power Output are output from the ASIC, it is driven regular current by the 15.0 V (A), -7.5 V (A) and 9.6 V (L) are output. Feedback for motor driver IC (IC951). the 15.0 V (A) is provided to the switching controller (Pin (40) of IC501) so that PWM control can be carried out. 4. Digital 1.85 V Power Output 1.85 V (D) is output. Feedback for the 1.85 V (D) is provided to the switching controller (Pins (43) of IC501) so that PWM 5. Digital 3.35 V Power Output 3.35 V (D) is output. Feedback for the 3.35 V (D) is provided to the swiching controller (Pin (45) of IC501) so that PWM 6. Digital 3.35 V Step-up Power Output 4.7 V is output. Feedback for the 4.7 V is provided to the swiching controller (Pin (47) of IC501) so that PWM control can be carried out. – 5 –]
15

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