Download: OUTLINE OF CIRCUIT DESCRIPTION 1-1. CA-A CIRCUIT DESCRIPTIONS Around CCD block

OUTLINE OF CIRCUIT DESCRIPTION 1-1. CA-A CIRCUIT DESCRIPTIONS Around CCD block 1. IC Configuration IC903 (RJ24J1AA0PT) CCD imager IC902 (TC74VHC04FTP) H driver IC904 (LR366854) V driver432124 23 22 21 IC905 (AD9806KST) CDS, AGC, A/D converter 2. IC905 (CCD) PS1 5 20 [Structure] PS3(LCC24 Frame transfer type CCD image sensor PS2 6 Top View) 19 PS4 Optical size 1/2.8 type VPW 7 Effective pixels 1300 (H) x 980 (V) 18 NSUB Pixels in total 1353 (H) x 1006 (V) VOUT 8 17 VOG Optical black Horizontal (H) direction: left 2 pixels, right 51 pixels Vertical (V) direction: upper 10 pixels, below 12 pixe...
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OUTLINE OF CIRCUIT DESCRIPTION 1-1. CA-A CIRCUIT DESCRIPTIONS

Around CCD block

1. IC Configuration IC903 (RJ24J1AA0PT) CCD imager IC902 (TC74VHC04FTP) H driver IC904 (LR366854) V driver432124 23 22 21 IC905 (AD9806KST) CDS, AGC, A/D converter 2. IC905 (CCD) PS1 5 20 [Structure] PS3(LCC24 Frame transfer type CCD image sensor PS2 6 Top View) 19 PS4 Optical size 1/2.8 type VPW 7 Effective pixels 1300 (H) x 980 (V) 18 NSUB Pixels in total 1353 (H) x 1006 (V) VOUT 8 17 VOG Optical black Horizontal (H) direction: left 2 pixels, right 51 pixels Vertical (V) direction: upper 10 pixels, below 12 pixels Dummy bit number Horizontal : 20 Vertical : 4 9 10 11 12 13 14 15 16 Fig. 1-2. CCD Terminal Name

V

H 51 Fig. 1-1.Optical Black Location (Top View) Pin No. Symbol Pin Description Waveform Voltage 1, 2, 23, 24 NC - 3, 4 PI3, PI4 Image clock Frame shift 0~12 V Frame shift 5, 6 PS1, PS2 Accumulation clock 0~12 V Line sending 7 PW P well DC8V8VOUT CCD output DC Approx. 13V9VDD Power DC 20 V 10 VSS GND DC0V11 VRD Reset drain DC 20 V 12 PR Reset gate L=18 V, H=23 V 13, 15 PH4, PH2 L=2.5 V, H=7.5 V Horizontal register clock 14, 16 PH1, PH3 L=0 V, H=5 V 17 VOG CCD output gate DC 3.3 V 18 VSUB N substrate L=26 V, H=29 V Frame shift 19, 20 PS4, PS3 Accumulation clock 0~12 V Line sending 21, 22 PI1, PI2 Image clock Frame shift 0~12 V Table 1-1. CCD Pin Description – 2 – VDD PI4 VSS PI3 VRD (NC) PR (NC) PH4 (NC) PH1 (NC) PH2 PI2 PH3 PI1, 3. IC903 (H Driver) and IC902 (V Driver) 4. IC901 (CDS, AGC Circuit and A/D Converter) An H driver (IC903) and V driver (IC902) are necessary in The video signal which is output from the CCD is input to order to generate the clocks (vertical transfer clock, horizon- Pins (26) and (27) of IC901. There are S/H blocks inside IC905 tal transfer clock and electronic shutter clock) which driver generated from the XSHP and XSHD pulses, and it is here the CCD. that CDS (correlated double sampling) is carried out. IC902 is an inverter IC which drives the horizontal CCDs (H1 After passing through the CDS circuit, the signal passes and H2). In addition the VREG 0~7, VXREG2 and VXREG3 through the AGC amplifier. It is A/C converted internally into signals which are output from IC102 are the vertical transfer a 10-bit signal, and is then input to IC102. clocks. The clock is drived until peak value which necessary CCD at IC902. PBLK CLPDM SHP SHD ADCCLK 19 23 29 30 21 22 16 CLAMP TIMING 1A 1 14 VCC GENERATOR PIN 27 PGA

CDS

1Y 2 13 6A 1026 2 DIN MUX S/H A/D DOUT 36 112A 3 12 6Y ADCIN CLAMP 12 DRVDD 2Y 4 11 5A REFERENCE AD9802 17 DVDD 3A 5 10 5Y 37 48 47 18 20 41 33 43 CMLEVEL VRT VTB STBY CLPOB ADCMODE ACVDD ADVDD 3Y694A GND784Y Fig. 1-5. IC901 Block Diagram Fig. 1-3. IC903 Block Diagram 30 VDD 29 OCNT GND 1 28 DUTY OUT_1 2 OCNT circuitDUTY circuit 27 IN_1 OUT_2 3 26 IN_2 OUT_3 4 25 IN_3 OUT_4 5 24 IN_4 OUT_5 6 23 IN_5 OUT_6 7 22 IN_6 OUT_7 8 21 IN_7 OUT_8 9 20 IN_8 OUT_9 10 19 IN_9 OUT_10 11 18 IN_10 OUT_NSUB 12 OCNT circuit 17 IN_NSUB CAP5V 13 16 VDD CAPNS 14 GND 15 Power circuit Fig. 1-4. IC902 Block Diagram – 3 –, 5. Transfer of Electric Charge by the Horizontal CCD The transfer system for the horizontal CCD emplays a 4-phase drive method. The electric charges sent to the final stage of the horizontal CCD are transferred to the floating diffusion (FD), as shown in Fig. 1-6. PR is turned on by the timing in (1), and the floating diffusion is charged to the potential of RD. The PR is turned off by the timing in (2). In this condition, the floating diffusion is floated at high impedance. The H2 potential becomes shallow by the timing in (3), and the electric charge now moves to the floating diffusion. Here, the electric charges are converted into voltages at the rate of V = Q/C by the equivalent capacitance C of the floating diffusion. PR is then turned on again by the timing in (1) when the H2 potential becomes deep. Thus, the potential of the floating diffusion changes in proportion to the quantity of transferred electric charge, and becomes CCD output after being received by the source follower. The equivalent circuit for the output circuit is shown in Fig. 1-7. (1) PR OG H2 H1 H4 H3 H2 H1 H4 H3 (1)(2) (3) H3 H4 (2) PR OG H2 H1 H4 H3 H2 H1 H4 H3 H1 H2

PR

(3) PR OG H2 H1 H4 H3 H2 H1 H4 H3 RD FD CCD OUT Fig. 1-6. Horizontal Transfer of CCD Imager and Extraction of Signal Voltage 6. Lens drive block 6-1. Shutter drive The regulator (IC952) drives by P ON signal which is output Reset gate pulse from the power control IC (IC501) is drived, and then power is20 V Pre-charge drain bias (PD) supplied to iris shutter drive IC (IC951). The drive signal (GPIO4, GPIO5, GPIO6, GPIO7) which is output from the ASIC (IC102) is drived the iris shutter drive IC (IC951), and the iris shutter spring is open and closed. Direction of transfer H Register Voltage output Electric charge Floating diffusion gate is floated at a high impedance. C is charged equivalently Fig. 1-7. Theory of Signal Extraction Operation – 4 –, 1-2. CA-B CIRCUIT DESCRIPTION 1. Circuit description 2. Outline of Operation 1-1. PTG When the shutter opens, detect the 8-bit microprocessor and This is program timing generator. Generates the timing signal transmit to record operation starts. that is needed in order to drive the FT-CCD sensor. When the PTG drives the FT-CCD, picture data passes through the A/D and is then input to the ASIC as 10-bit data. 1-2. FCP This data then sends FCP, after which it is carried out various The FCP receives the output data from the FT-CCD sensor processing operations on the data (such as gamma correc- via the PTG, and then carries out various processing opera- tion and white balance). The data is then sent to the ITP where tions on the data (such as gamma correction and white processing such as contour emphasis and chroma are car- banance). ried out, after which it is temporarily stored in the SDRAM. In case of still picture the data is then compressed by the 1-3. ITP JPEG method and in case of picture it is compressed by The ITP is a pixel conversion processor. It carries out various MJPEG method and is written to compact flash card. processing operations (such as contour emphasis and chroma) on the image data that is input from the FCP or from memory, 3. LCD Block and then stores the processed data in memory. RGB signals corresponding to the LCD driver are output from the ASIC (video player). The LCD driver converts the RGB 1-4. CPU signals that are output from the ASIC to a signal level that is This is 32 bit RISC CPU. appropriate for the LCD monitor. These RGB signals and the control signal which is output by the LCD driver are used to 1-5. Memory controller drive the LCD panel. This is controlled SDRAM, flash ROM and CF card etc. The RGB signals are 1H transposed so that no DC compo- nent is present in the LCD element, and the two horizontal 1-6. Video player shift register clocks drive the horizontal shift registers inside Outputs the RGB signals that are needed to control the graphic the LCD panel so that the 1H transposed RGB signals are overlay function and to drive the LCD. applied to the LCD panel. Because the LCD closes more as the difference in potential 1-7. GPIO between the VCOM (common polar voltage: fixed at DC) and This is a multipurpose I/O. (It can be used as an input/output the R, G and B signals becomes greater, the display becomes port.) darker; if the difference in potential is smaller, the element opens and the LCD become brighter. In addition, the bright- 1-8. COM port ness and contrast settings for the LCD can be varied by means This is communication block. Supports USB communication. of the serial data from the ASIC. 1-9. Serial communication This is the interface for the 8-bit microprocessor. 1-10. LCD driver The RGB output signals that are output from the ASIC are converted to a signal level that is appropriate for the LCD moni- tor. 1-11. LCD monitor This is the image display device which displays the image signals supplied from the LCD driver. – 5 –, 1-3. CP1 POWER CIRCUIT DESCRIPTION 1. Outline 3. Digital 3.4 V Power Output This is the main power circuit, and is comprised of the follow- 3.4 V (D) is output. Feedback is sent to pin (41) of the switch- ing blocks. ing controller (IC501) for PWM control to be carried out. Switching controller (IC501) Digital5Vand analog system power output (T5001, Q5001) 4. Digital5Vand Analog System Power Output Digital 2.5 V system power supply (Q5007) 5.1 V (D) , 26.4 V (A), 20 V (A), 13 V (A) and 5.1 V (A) are Digital 3.4 V system power supply (Q5018) output. Feedback for the 5.1 V (D) is provided to the switch- LCD system power supply (Q5008, T5002) ing controller (Pins (35) of IC501) so that PWM control can Backlight power supply output (Q5013) be carried out. Inverter output (T5003, Q5017) 5. Digital 2.5 V System Power Output 2. Switching Controller (IC501) 2.5 V (D) is output. Feedback is provided to the swiching con- This is the basic circuit which is necessary for controlling the troller (Pin (23) of IC501) so that PWM control can be carried power supply for a PWM-type switching regulator, and is pro- out. vided with five built-in channels, only CH2 (digital 5 V, analog system), CH4 (LCD system), CH3 (digital 2.5 V), CH1 (digital 6. LCD System Power Output 3.4 V) and CH5 (backlight system) are used. Feedback from 12.4 V (L) is output. Feedback for the 12.4 V (L) is provided5V(D) (CH2), 2.5 V (D) (CH3) , 12.4 V (L) (CH4), 3.4 V (D) to the switching controller (Pins (22) of IC501) so that PWM (CH1) and7V(L) (CH5) power supply outputs are received, control can be carried out. and the PWM duty is varied so that each one is maintained at the correct voltage setting level. 7. Backlight Power Supply output 7.0 V (L) is output. Feedback is sent to pin (17) of the switch- 2-1. Short-circuit protection circuit ing controller (IC501) for PWM control to be carried out. If output is short-circuited for the length of time determined by the condenser which is connected to Pin (29) of IC501, all 8. Inverter Output output is turned off. The control signal (P ON) are recontrolled The backlight uses a flat picture tube. When INV CLK is in- to restore output. put, Q5017 carries out switching operations, so that T5003 is energized and a high-voltage pulse is generated between pins (3) and (4) of T5003. This high-voltage pulse is applied to the backlight to make it illuminate. – 6 –]
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