Download: Features • Compatible with MCS-51 Products • 4 Kbytes of In-System Reprogrammable Flash Memory • Fully Static Operation: 0 Hz to 24 MHz • Three-Level Program Memory Lock

Features

• Compatible with MCS-51 Products • 4 Kbytes of In-System Reprogrammable Flash Memory

Endurance: 1,000 Write/Erase Cycles

• Fully Static Operation: 0 Hz to 24 MHz • Three-Level Program Memory Lock • 128 x 8-Bit Internal RAM • 32 Programmable I/O Lines • Two 16-Bit Timer/Counters • Six Interrupt Sources • 8-BitProgrammable Serial Channel • Low Power Idle and Power Down Modes Microcontroller

Description with 4 Kbytes The AT89C51 is a low-power, high-performance CMOS 8-bit microcomputer with 4 Kbytes of Flash Programmable and Erasable Read Only Memory (PEROM). The Flash

device is manufactured using Atmel’s high density nonvolatile memory technology and is compatible with the industry standard MCS-51 instruction set and pinout.

The on-chip Flash allows the program memory to be reprogrammed in-system or by

a conventional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89C51 is a powerful microcomputer AT89C51 which provides a highly flexible and cost effective solution to many embedded control applications. (continued)

Pin Configurations PDIP/Cerdip

P 1 . 0140VCCP1. 1239P0. 0 ( AD0) P 1 . 2338P0. 1 ( AD1) P 1 . 3437P0. 2 ( AD2) P 1 . 4536P0. 3 ( AD3) P 1 . 5635P0. 4 ( AD4) P 1 . 6734P0. 5 ( AD5) P 1 . 7833P0. 6 ( AD6) RST932P0. 7 ( AD7) PQFP/TQFP ( RXD) P 3 . 01031EA/ VPP( TXD) P 3 . 11130ALE/ PROG( INT0) P 3 . 21229PSEN( INT1) P 3 . 31328P2. 7 ( A15) INDEX( T 0 ) P 3 . 41427P2. 6 ( A14) CORNER( T 1 ) P 3 . 51526P2. 5 ( A13) ( W R ) P 3 . 61625P2. 4 ( A12) ( R D ) P 3 . 71724P2. 3 ( A11) 444240383634XTAL21823P2. 2 ( A10) 4341393735XTAL11922P2. 1 ( A 9 ) P 1 . 5133P0. 4 ( AD4) GND2021P2. 0 ( A 8 ) P 1 . 6232P0. 5 ( AD5) P 1 . 7331P0. 6 ( AD6) RST430P0. 7 ( AD7) ( RXD) P 3 . 0529EA/ VPPPLCC/LCCNC628NC( TXD) P 3 . 1727ALE/ PROG( INT0) P 3 . 2826PSEN( INT1) P 3 . 3925P2. 7 ( A15) INDEX( T 0 ) P 3 . 41024P2. 6 ( A14) CORNER( T 1 ) P 3 . 51123P2. 5 ( A13) 1315171921121416182022642444240P1. 57531434139P0. 4 ( AD4) P 1 . 6838P0. 5 ( AD5) P 1 . 7937P0. 6 ( AD6) RST1036P0. 7 ( AD7) ( RXD) P 3 . 01135EA/ VPPNC1234NC( TXD) P 3 . 11333ALE/ PROG( INT0) P 3 . 21432PSEN( INT1) P 3 . 31531P2. 7 ( A15) ( T 0 ) P 3 . 41630P2. 6 ( A14) ( T 1 ) P 3 . 517192123252729P2. 5 ( A13) 1820222426280265E ( W R ) P 3 . 6P1. 4 ( R D ) P 3 . 7P1. 3 X TAL2P1. 2 X TAL1P1. 1GNDP1. 0GNDNC( A 8 ) P 2 . 0VCC( A 9 ) P 2 . 1P0. 0 ( AD0) ( A10) P 2 . 2P0. 1 ( AD1) ( A11) P 2 . 3P0. 2 ( AD2) ( A12) P 2 . 4P0. 3 ( AD3) ( W R ) P 3 . 6P1. 4 ( R D ) P 3 . 7P1. 3 X TAL2P1. 2 X TAL1P1. 1GNDP1. 0NCNC( A 8 ) P 2 . 0VCC( A 9 ) P 2 . 1P0. 0 ( AD0) ( A10) P 2 . 2P0. 1 ( AD1) ( A11) P 2 . 3P0. 2 ( AD2) ( A12) P 2 . 4P0. 3 ( AD3),

Block Diagram

P0.0 - P0.7 P2.0 - P2.7

VCC

PORT 0 DRIVERS PORT 2 DRIVERS

GND

RAM ADDR. PORT 0 REGISTER RAM PORT 2 LATCH LATCH FLASH STACK PROGRAMB ADDRESS REGISTER ACC POINTER REGISTER

BUFFER

TMP2 TMP1

PC

ALU INCREMENTER INTERRUPT, SERIAL PORT, AND TIMER BLOCKS

PROGRAM

PSW COUNTER

PSEN

ALE/PROG TIMING AND INSTRUCTION DPTR EA / VPP CONTROL

REGISTER RST

PORT 1 PORT 3 LATCH LATCH

OSC

PORT 1 DRIVERS PORT 3 DRIVERS P1.0 - P1.7 P3.0 - P3.7 2 AT89C51,

Description (Continued) @ DPTR). In this application it uses strong internal pullups

when emitting 1s. During accesses to external data mem- The AT89C51 provides the following standard features: 4 ory that use 8-bit addresses (MOVX @ RI), Port 2 emits Kbytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16-bit the contents of the P2 Special Function Register. timer/counters, a five vector two-level interrupt architec- ture, a full duplex serial port, on-chip oscillator and clock Port 2 also receives the high-order address bits and some circuitry. In addition, the AT89C51 is designed with static control signals during Flash programming and verification. logic for operation down to zero frequency and supports Port 3 two software selectable power saving modes. The Idle Port 3 is an 8-bit bidirectional I/O port with internal pullups. Mode stops the CPU while allowing the RAM, timer/count- The Port 3 output buffers can sink/source four TTL inputs. ers, serial port and interrupt system to continue function- When 1s are written to Port 3 pins they are pulled high by ing. The Power Down Mode saves the RAM contents but the internal pullups and can be used as inputs. As inputs, freezes the oscillator disabling all other chip functions until Port 3 pins that are externally being pulled low will source the next hardware reset. current (IIL) because of the pullups.

Pin Description Port 3 also serves the functions of various special features

of the AT89C51 as listed below:

VCC

Supply voltage. Port Pin Alternate Functions P3.0 RXD (serial input port)

GND

Ground. P3.1 TXD (serial output port) P3.2 INT0 (extenal interrupt 0) Port 0 P3.3 INT1 (extenal interrupt 1) Port 0 is an 8-bit open drain bidirectional I/O port. As an output port each pin can sink eight TTL inputs. When 1s P3.4 T0 (timer 0 extenal input) are written to port 0 pins, the pins can be used as high-im- P3.5 T1 (timer 1 external input) pedance inputs. P3.6 WR (extenal data memory write strobe) Port 0 may also be configured to be the multiplexed low- P3.7 RD (external data memory read strobe) order address/data bus during accesses to external pro- gram and data memory. In this mode P0 has internal pul- Port 3 also receives some control signals for Flash pro- lups. gramming and programming verification.

RST

Port 0 also receives the code bytes during Flash program- ming, and outputs the code bytes during program verifica- Reset input. A high on this pin for two machine cycles tion. External pullups are required during program verifica- while the oscillator is running resets the device. tion. ALE/PROG Port 1 Address Latch Enable output pulse for latching the low Port 1 is an 8-bit bidirectional I/O port with internal pullups. byte of the address during accesses to external memory. The Port 1 output buffers can sink/source four TTL inputs. This pin is also the program pulse input (PROG) during When 1s are written to Port 1 pins they are pulled high by Flash programming. the internal pullups and can be used as inputs. As inputs, In normal operation ALE is emitted at a constant rate of Port 1 pins that are externally being pulled low will source 1/6 the oscillator frequency, and may be used for external current (IIL) because of the internal pullups. timing or clocking purposes. Note, however, that one ALE Port 1 also receives the low-order address bytes during pulse is skipped during each access to external Data Flash programming and program verification. Memory. Port 2 If desired, ALE operation can be disabled by setting bit 0 Port 2 is an 8-bit bidirectional I/O port with internal pullups. of SFR location 8EH. With the bit set, ALE is active only The Port 2 output buffers can sink/source four TTL inputs. during a MOVX or MOVC instruction. Otherwise, the pin is When 1s are written to Port 2 pins they are pulled high by weakly pulled high. Setting the ALE-disable bit has no ef- the internal pullups and can be used as inputs. As inputs, fect if the microcrontroller is in external execution mode. Port 2 pins that are externally being pulled low will source PSEN current (IIL) because of the internal pullups. Program Store Enable is the read strobe to external pro- Port 2 emits the high-order address byte during fetches gram memory. from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX (continued),

Pin Description (Continued) mode. The idle mode can be terminated by any enabled

interrupt or by a hardware reset. When the AT89C51 is executing code from external pro- gram memory, PSEN is activated twice each machine cy- It should be noted that when idle is terminated by a hard- cle, except that two PSEN activations are skipped during ware reset, the device normally resumes program execu- each access to external data memory. tion, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hard- EA/VPP External Access Enable. EA must be strapped to GND in Figure 1. Oscillator Connections order to enable the device to fetch code from external pro- gram memory locations starting at 0000H up to FFFFH. C2 Note, however, that if lock bit 1 is programmed, EA will be XTAL2 internally latched on reset. EA should be strapped to VCC for internal program execu- tions. C1 This pin also receives the 12-volt programming enable XTAL1 voltage (VPP) during Flash programming, for parts that re- quire 12-volt VPP. XTAL1 Input to the inverting oscillator amplifier and input to the GND internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier. Notes: C1, C2 = 30 pF ± 10 pF for Crystals

Oscillator Characteristics = 40 pF ± 10 pF for Ceramic Resonators

XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier which can be configured for use Figure 2. External Clock Drive Configuration as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum voltage high and low time specifi- cations must be observed.

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on- chip peripherals remain active. The mode is invoked by software. The content of the on-chip RAM and all the spe- cial functions registers remain unchanged during this

Status of External Pins During Idle and Power Down

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal11Data Data Data Data Idle External11Float Data Address Data Power Down Internal00Data Data Data Data Power Down External00Float Data Data Data 4 AT89C51, ware inhibits access to internal RAM in this event, but ac- is restored to its normal operating level and must be held cess to the port pins is not inhibited. To eliminate the pos- active long enough to allow the oscillator to restart and sibility of an unexpected write to a port pin when Idle is stabilize. terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or Program Memory Lock Bits to external memory. On the chip are three lock bits which can be left unpro-

Power Down Mode grammed (U) or can be programmed (P) to obtain the ad-ditional features listed in the table below:

In the power down mode the oscillator is stopped, and the When lock bit 1 is programmed, the logic level at the EA instruction that invokes power down is the last instruction pin is sampled and latched during reset. If the device is executed. The on-chip RAM and Special Function Regis- powered up without a reset, the latch initializes to a ran- ters retain their values until the power down mode is termi- dom value, and holds that value until reset is activated. It nated. The only exit from power down is a hardware reset. is necessary that the latched value of EA be in agreement Reset redefines the SFRs but does not change the on- with the current logic level at that pin in order for the device chip RAM. The reset should not be activated before VCC to function properly.

Lock Bit Protection Modes

Program Lock Bits LB1 LB2 LB3 Protection Type1UUUNo program lock features. MOVC instructions executed from external program memory are disabled from2PUUfetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash is disabled. 3PPUSame as mode 2, also verify is disabled. 4PPPSame as mode 3, also external execution is disabled.

Programming the Flash

The AT89C51 is normally shipped with the on-chip Flash The AT89C51 code memory array is programmed byte- memory array in the erased state (that is, contents = FFH) by-byte in either programming mode. To program any and ready to be programmed. The programming interface non-blank byte in the on-chip Flash Memory, the entire accepts either a high-voltage (12-volt) or a low-voltage memory must be erased using the Chip Erase Mode. (VCC) program enable signal. The low voltage program- Programming Algorithm: Before programming the ming mode provides a convenient way to program the AT89C51, the address, data and control signals should be AT89C51 inside the user’s system, while the high-voltage set up according to the Flash programming mode table programming mode is compatible with conventional third and Figures 3 and 4. To program the AT89C51, take the party Flash or EPROM programmers. following steps. The AT89C51 is shipped with either the high-voltage or 1. Input the desired memory location on the address low-voltage programming mode enabled. The respective lines. top-side marking and device signature codes are listed in 2. Input the appropriate data byte on the data lines. the following table. 3. Activate the correct combination of control signals. VPP = 12 V VPP = 5 V 4. Raise EA/VPP to 12 V for the high-voltage program- ming mode. AT89C51 AT89C51 5. Pulse ALE/PROG once to program a byte in the Flash Top-Side Mark xxxx xxxx-5 array or the lock bits. The byte-write cycle is self-timed and yyww yyww typically takes no more than 1.5 ms. Repeat steps 1 (030H)=1EH (030H)=1EH through 5, changing the address and data for the entire Signature (031H)=51H (031H)=51H array or until the end of the object file is reached. (032H)=FFH (032H)=05H Data Polling: The AT89C51 features Data Polling to indi- cate the end of a write cycle. During a write cycle, an at- (continued),

Programming the Flash (Continued) Reading the Signature Bytes: The signature bytes are

read by the same procedure as a normal verification of tempted read of the last byte written will result in the com- locations 030H, plement of the written datum on PO.7. Once the write cy- 031H, and 032H, except that P3.6 and P3.7 must be cle has been completed, true data are valid on all outputs, pulled to a logic low. The values returned are as follows. and the next cycle may begin. Data Polling may begin any time after a write cycle has been initiated. (030H) = 1EH indicates manufactured by Atmel (031H) = 51H indicates 89C51 Ready/Busy: The progress of byte programming can (032H) = FFH indicates 12 V programming also be monitored by the RDY/BSY output signal. P3.4 is (032H) = 05H indicates5Vprogramming pulled low after ALE goes high during programming to in- dicate BUSY. P3.4 is pulled high again when program- ming is done to indicate READY. Programming Interface Program Verify: If lock bits LB1 and LB2 have not been Every code byte in the Flash array can be written and the programmed, the programmed code data can be read entire array can be erased by using the appropriate com- back via the address and data lines for verification. The bination of control signals. The write operation cycle is lock bits cannot be verified directly. Verification of the lock self-timed and once initiated, will automatically time itself bits is achieved by observing that their features are en- to completion. abled. All major programming vendors offer worldwide support Chip Erase: The entire Flash array is erased electrically for the Atmel microcontroller series. Please contact your by using the proper combination of control signals and by local programming vendor for the appropriate software re- holding ALE/PROG low for 10 ms. The code array is writ- vision. ten with all “1"s. The chip erase operation must be exe- cuted before the code memory can be re-programmed.

Flash Programming Modes

ALE/ EA/ Mode RST PSEN PROG VPP P2.6 P2.7 P3.6 P3.7 Write Code DataHLH/12V(1) LHHHRead Code DataHLHHLLHHWrite Lock Bit - 1HLH/12VHHHHBit - 2HL(2) H/12VHHLLBit - 3HLH/12VHLHLChip EraseHLH/12VHLLLRead Signature ByteHLHHLLLLNotes: 1. The signature byte at location 032H designates 2. Chip Erase requires a 10 ms PROG pulse. whether VPP = 12 V or VPP = 5 V should be used to enable programming. 6 AT89C51, Figure 3. Programming the Flash Figure 4. Verifying the Flash +5V +5V AT89C51 AT89C51 A0 - A7 ADDR. P1 VCC A0 - A7ADDR. P1 VCC OOOOH/OFFFH PGM OOOOH/0FFFH PGM DATA P2.0 - P2.3 P0 P2.0 - P2.3 P0 A8 - A11 DATA (USE 10KA8 - A11 P2.6 PULLUPS)P2.6 SEE FLASH P2.7 ALE PROG SEE FLASH P2.7 ALE PROGRAMMING PROGRAMMING MODES TABLE P3.6 MODES TABLE P3.6

V

P3.7 IHP3.7 XTAL 2 EA VIH/VPP XTAL 2 EA 4-24 MHz 4-24 MHz XTAL 1 RST VIH XTAL 1 RST VIH GND PSEN GND PSEN

Flash Programming and Verification Characteristics

TA = 21°C to 27°C, VCC = 5.0 ± 10% Symbol Parameter Min Max Units V (1)PP Programming Enable Voltage 11.5 12.5VI(1)PP Programming Enable Current 1.0 mA 1/tCLCL Oscillator Frequency 4 24 MHz tAVGL Address Setup to PROG Low 48tCLCL tGHAX Address Hold After PROG 48tCLCL tDVGL Data Setup to PROG Low 48tCLCL tGHDX Data Hold After PROG 48tCLCL tEHSH P2.7 (ENABLE) High to VPP 48tCLCL tSHGL VPP Setup to PROG Low 10 µs t (1)GHSL VPP Hold After PROG 10 µs tGLGH PROG Width 1 110 µs tAVQV Address to Data Valid 48tCLCL tELQV ENABLE Low to Data Valid 48tCLCL tEHQV Data Float After ENABLE 0 48tCLCL tGHBL PROG High to BUSY Low 1.0 µs tWC Byte Write Cycle Time 2.0 ms Note: 1. Only used in 12-volt programming mode.,

Flash Programming and Verification Waveforms - High Voltage Mode

PROGRAMMING VERIFICATION P1.0 - P1.7 P2.0 - P2.3 ADDRESS ADDRESS tAVQV PORT 0 DATA IN DATA OUT tDVGL tGHDX tAVGL tGHAX ALE/PROG tSHGL tt GHSLGLGH VPP LOGIC 1 EA/VPP LOGIC 0 tEHSH tEHQZ P2.7 tELQV (ENABLE) tGHBL P3.4 (RDY/BSY) BUSY READY tWC

Flash Programming and Verification Waveforms - Low Voltage Mode

PROGRAMMING VERIFICATION P1.0 - P1.7 P2.0 - P2.3 ADDRESS ADDRESS tAVQV PORT 0 DATA IN DATA OUT tDVGL tGHDX tAVGL tGHAX ALE/PROG tSHGL tGLGH LOGIC 1 EA/VPP LOGIC 0 tEHSH tEHQZ P2.7 tELQV (ENABLE) tGHBL P3.4 (RDY/BSY) BUSY READY tWC 8 AT89C51,

Absolute Maximum Ratings*

*NOTICE: Stresses beyond those listed under “Absolute Maxi- Operating Temperature... -55°C to +125°C mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the Storage Temperature... -65°C to +150°C device at these or any other conditions beyond those indi- Voltage on Any Pin cated in the operational sections of this specification is not with Respect to Ground ... -1.0 V to +7.0 V implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage ... 6.6 V DC Output Current ... 15.0 mA

D.C. Characteristics

TA = -40°C to 85°C, VCC = 5.0 V ± 20% (unless otherwise noted) Symbol Parameter Condition Min Max Units VIL Input Low Voltage (Except EA) -0.5 0.2 VCC-0.1 V VIL1 Input Low Voltage (EA) -0.5 0.2 VCC-0.3 V VIH Input High Voltage (Except XTAL1, RST) 0.2 VCC+0.9 VCC+0.5 V VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC+0.5VVOutput Low Voltage (1) OL (Ports 1,2,3) IOL = 1.6 mA 0.45VVOutput Low Voltage (1) OL1 (Port 0, ALE, PSEN) IOL = 3.2 mA 0.45 V IOH = -60 µA, VCC = 5 V ± 10% 2.4VVOutput High VoltageOH (Ports 1,2,3, ALE, PSEN) IOH = -25 µA 0.75 VCC V IOH = -10 µA 0.9 VCC V IOH = -800 µA, VCC = 5 V ± 10% 2.4VVOutput High VoltageOH1 (Port 0 in External Bus Mode) IOH = -300 µA 0.75 VCC V IOH = -80 µA 0.9 VCCVILogical 0 Input CurrentIL (Ports 1,2,3) VIN = 0.45 V -50 µA I Logical 1 to 0 TransitionTL Current (Ports 1,2,3) VIN = 2 V -650 µA I Input Leakage Current LI (Port 0, EA) 0.45 < VIN < VCC ±10 µA RRST Reset Pulldown Resistor 50 300 KΩ CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF Active Mode, 12 MHz 20 mA Power Supply Current I Idle Mode, 12 MHz 5 mACC V = 6 V 100 µA Power Down Mode(2) CC VCC = 3 V 40 µA Notes: 1. Under steady state (non-transient) conditions, IOL Maximum total IOL for all output pins:71 mA must be externally limited as follows: If IOL exceeds the test condition, VOL may exceed the Maximum IOL per port pin:10 mA related specification. Pins are not guaranteed to sink Maximum IOL per 8-bit port: current greater than the listed test conditions. Port 0:26 mA 2. Minimum VCC for Power Down is 2 V. Ports 1,2, 3:15 mA,

A.C. Characteristics

(Under Operating Conditions; Load Capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; Load Capacitance for all other outputs = 80 pF)

External Program and Data Memory Characteristics

12 MHz Oscillator 16 to 24 MHz Oscillator Symbol Parameter Min Max Min Max Units 1/tCLCL Oscillator Frequency 0 24 MHz tLHLL ALE Pulse Width 127 2tCLCL-40 ns tAVLL Address Valid to ALE Low 28 tCLCL-13 ns tLLAX Address Hold After ALE Low 48 tCLCL-20 ns tLLIV ALE Low to Valid Instruction In 233 4tCLCL-65 ns tLLPL ALE Low to PSEN Low 43 tCLCL-13 ns tPLPH PSEN Pulse Width 205 3tCLCL-20 ns tPLIV PSEN Low to Valid Instruction In 145 3tCLCL-45 ns tPXIX Input Instruction Hold After PSEN00ns tPXIZ Input Instruction Float After PSEN 59 tCLCL-10 ns tPXAV PSEN to Address Valid 75 tCLCL-8 ns tAVIV Address to Valid Instruction In 312 5tCLCL-55 ns tPLAZ PSEN Low to Address Float 10 10 ns tRLRH RD Pulse Width 400 6tCLCL-100 ns tWLWH WR Pulse Width 400 6tCLCL-100 ns tRLDV RD Low to Valid Data In 252 5tCLCL-90 ns tRHDX Data Hold After RD00ns tRHDZ Data Float After RD 97 2tCLCL-28 ns tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns tAVDV Address to Valid Data In 585 9tCLCL-165 ns tLLWL ALE Low to RD or WR Low 200 300 3tCLCL-50 3tCLCL+50 ns tAVWL Address to RD or WR Low 203 4tCLCL-75 ns tQVWX Data Valid to WR Transition 23 tCLCL-20 ns tQVWH Data Valid to WR High 433 7tCLCL-120 ns tWHQX Data Hold After WR 33 tCLCL-20 ns tRLAZ RD Low to Address Float00ns tWHLH RD or WR High to ALE High 43 123 tCLCL-20 tCLCL+25 ns 10 AT89C51,

External Program Memory Read Cycle

tLHLL

ALE

tPLPH tAVLL tt LLIVLLPL PSEN tPLIVttPXAVPLAZttPXIZLLAX tPXIX PORT 0 A0 - A7 INSTR IN A0 - A7 tAVIV PORT 2 A8 - A15 A8 - A15

External Data Memory Read Cycle

tLHLL

ALE

tWHLH

PSEN

tLLDV tRLRH tLLWL RD tLLAXttRLDV tRHDZ AVLL tRLAZ tRHDX PORT 0 A0 - A7 FROM RI OR DPL DATA IN A0 - A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH,

External Data Memory Cycle

tLHLL

ALE

tWHLH

PSEN

tLLWL tWLWH WR tLLAXtttAVLL QVWX WHQX tQVWH PORT 0 A0 - A7 FROM RI OR DPL DATA OUT A0 - A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH

External Clock Drive Waveforms

tCHCX tCHCX tCLCH tCHCLVCC- 0.5V 0.7 VCC 0.2 VCC - 0.1V 0.45V tCLCX tCLCL

External Clock Drive

Symbol Parameter Min Max Units 1/tCLCL Oscillator Frequency 0 24 MHz tCLCL Clock Period 41.6 ns tCHCX High Time 15 ns tCLCX Low Time 15 ns tCLCH Rise Time 20 ns tCHCL Fall Time 20 ns 12 AT89C51,

Serial Port Timing: Shift Register Mode Test Conditions

(VCC = 5.0 V ± 20%; Load Capacitance = 80 pF) 12 MHz Osc Variable Oscillator Symbol Parameter Min Max Min Max Units tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-33 ns tXHDX Input Data Hold After Clock Rising Edge00ns tXHDV Clock Rising Edge to Input Data Valid 700 10tCLCL-133 ns

Shift Register Mode Timing Waveforms

INSTRUCTION012345678

ALE

tXLXL

CLOCK

tQVXH tXHQX WRITE TO SBUF01234567tXHDX OUTPUT DATA t SET TIXHDV CLEAR RI VALID VALID VALID VALID VALID VALID VALID VALID INPUT DATA SET RI (1)

AC Testing Input/Output Waveforms (1) Float Waveforms

VCC- 0.5V V + 0.1V - 0.1V0.2 VC C + 0.9V LOAD

VOL

TEST POINTS V Timing ReferenceLOAD Points 0.2 VC C - 0.1V V - 0.1VLOAD V + 0.1V0.45V OL Note: 1. AC Inputs during testing are driven at VCC - 0.5 V for a Note: 1. For timing purposes, a port pin is no longer floating logic 1 and 0.45 V for a logic 0. Timing measure- when a 100 mV change from load voltage occurs. ments are made at VIH min. for a logic 1 and VIL A port pin begins to float when a 100 mV change max. for a logic 0. from the loaded VOH/VOL level occurs.,

Ordering Information

Speed Power (MHz) Supply Ordering Code Package Operation Range 125V± 20% AT89C51-12AC 44A Commercial AT89C51-12JC 44J (0°C to 70°C) AT89C51-12PC 40P6 AT89C51-12QC 44Q AT89C51-12AI 44A Industrial AT89C51-12JI 44J (-40°C to 85°C) AT89C51-12PI 40P6 AT89C51-12QI 44Q AT89C51-12AA 44A Automotive AT89C51-12JA 44J (-40°C to 125°C) AT89C51-12PA 40P6 AT89C51-12QA 44Q5V± 10% AT89C51-12DM 40D6 Military AT89C51-12LM 44L (-55°C to 125°C) AT89C51-12DM/883 40D6 Military/883C AT89C51-12LM/883 44L Class B, Fully Compliant (-55°C to 125°C) 165V± 20% AT89C51-16AC 44A Commercial AT89C51-16JC 44J (0°C to 70°C) AT89C51-16PC 40P6 AT89C51-16QC 44Q AT89C51-16AI 44A Industrial AT89C51-16JI 44J (-40°C to 85°C) AT89C51-16PI 40P6 AT89C51-16QI 44Q AT89C51-16AA 44A Automotive AT89C51-16JA 44J (-40°C to 125°C) AT89C51-16PA 40P6 AT89C51-16QA 44Q 205V± 20% AT89C51-20AC 44A Commercial AT89C51-20JC 44J (0°C to 70°C) AT89C51-20PC 40P6 AT89C51-20QC 44Q AT89C51-20AI 44A Industrial AT89C51-20JI 44J (-40°C to 85°C) AT89C51-20PI 40P6 AT89C51-20QI 44Q 14 AT89C51,

Ordering Information

Speed Power (MHz) Supply Ordering Code Package Operation Range 245V± 20% AT89C51-24AC 44A Commercial AT89C51-24JC 44J (0°C to 70°C) AT89C51-24PC 44P6 AT89C51-24QC 44Q AT89C51-24AI 44A Industrial AT89C51-24JI 44J (-40°C to 85°C) AT89C51-24PI 44P6 AT89C51-24QI 44Q Package Type 44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 40D6 40 Lead, 0.600" Wide, Non-Windowed, Ceramic Dual Inline Package (Cerdip) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 44L 44 Pad, Non-Windowed, Ceramic Leadless Chip Carrier (LCC) 40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 44Q 44 Lead, Plastic Gull Wing Quad Flatpack (PQFP)]

15