Download: 8-bit RISC Microcontroller Application Note AVR151: Setup And Use of The SPI Features Introduction

8-bit RISC Microcontroller Application Note Rev. 2585A–AVR–11/04 AVR151: Setup And Use of The SPI Features • SPI Pin Functionality • Multi Slave Systems • SPI Timing • SPI Transmission Conflicts • Emulating the SPI • Code examples for Polled operation • Code examples for Interrupt Controlled operation Introduction This application note describes how to setup and use the on-chip Serial Peripheral Interface (SPI) of the AVR micro-controller. Most AVR devices come with an on board SPI and can be configured according to this document. After a theoretical background it will be shown how to configur...
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8-bit RISC

Microcontroller Application Note

Rev. 2585A–AVR–11/04

AVR151: Setup And Use of The SPI Features

• SPI Pin Functionality • Multi Slave Systems • SPI Timing • SPI Transmission Conflicts • Emulating the SPI • Code examples for Polled operation • Code examples for Interrupt Controlled operation

Introduction

This application note describes how to setup and use the on-chip Serial Peripheral Interface (SPI) of the AVR micro-controller. Most AVR devices come with an on board SPI and can be configured according to this document. After a theoretical background it will be shown how to configure the SPI to run in both master mode and slave mode Figure 1. Master and Slave Interface. Master Mode Slave Mode Receive Buffer Receive Buffer DATABUS DATABUS Shift- MISO Shift-MOSI MISO MISO MOSI Register Register

MOSI

SPI SCK Clock Generator SS SS

VCC

,

General description of the SPI

The SPI allows high-speed synchronous data transfer between the AVR and peripheral devices or between several AVR devices. On most parts the SPI has a second purpose where it is used for In System Programming (ISP). See application note AVR910 for details. The interconnection between two SPI devices always happens between a master device and a slave device. Compared to some peripheral devices like sensors which can only run in slave mode, the SPI of the AVR can be configured for both master and slave mode. The mode the AVR is running in is specified by the settings of the master bit (MSTR) in the SPI control register (SPCR). Special considerations about the SS pin have to be taken into account. This will be described later in the section “Multi Slave Systems - SS pin Functionality” on page 3. The master is the active part in this system and has to provide the clock signal a serial data transmission is based on. The slave is not capable of generating the clock signal and thus can not get active on its own. The slave just sends and receives data if the master generates the necessary clock signal. The master however generates the clock signal only while sending data. That means that the master has to send data to the slave to read data from the slave. Note: This can be confusing especially if “passive” peripherals like sensors are used. The need to send random data to a sensor just to read its data is not always clear. Data transmission between The interaction between a master and a slave AVR is shown in Figure 1 on page 1. Two Master and Slave identical SPI units are displayed. The left unit is configured as master while the right unit is configured as slave. The MISO, MOSI and SCK lines are connected with the corre- sponding lines of the other part. The mode in which a part is running determines if they are input or output signal lines. Because a bit is shifted from the master to the slave and from the slave to the master simultaneously in one clock cycle both 8-bit shift registers can be considered as one 16-bit circular shift register. This means that after eight SCK clock pulses the data between master and slave will be exchanged. The system is single buffered in the transmit direction and double buffered in the receive direction. This influences the data handling in the following ways: 1. New bytes to be sent can not be written to the data register (SPDR) / shift regis- ter before the entire shift cycle is completed. 2. Received bytes are written to the Receive Buffer immediately after the transmis- sion is completed. 3. The Receive Buffer has to be read before the next transmission is completed or data will be lost. 4. Reading the SPDR will return the data of the Receive Buffer. After a transfer is completed the SPI Interrupt Flag (SPIF) will be set in the SPI Status Register (SPSR). This will cause the corresponding interrupt to be executed if this inter- rupt and the global interrupts are enabled. Setting the SPI Interrupt Enable (SPIE) bit in the SPCR enables the interrupt of the SPI while setting the I bit in the SREG enables the global interrupts. Pins of the SPI The SPI consists of four different signal lines. These lines are the shift clock (SCK), the Master Out Slave In line (MOSI), the Master In Slave Out line (MISO) and the active low 2 AVR151,

AVR151

Slave Select line (SS). When the SPI is enabled, the data direction of the MOSI, MISO, SCK and SS pins are overridden according to the following table. Table 1. SPI Pin overrides Pin Direction Master Mode Direction Slave Mode MOSI User Defined Input MISO Input User Defined SCK User Defined Input SS User Defined Input This table shows that just the input pins are automatically configured. The output pins have to be initialized manually by software. The reason for this is to avoid damages e.g. through driver contention. Multi Slave Systems - The Slave Select (SS) pin plays a central role in the SPI configuration. Depending on SS pin Functionality the mode the part is running in and the configuration of this pin, it can be used to acti- vate or deactivate the devices. The SS pin can be compared with a chip select pin which has some extra features. In master mode, the SS pin must be held high to ensure master SPI operation if this pin is configured as an input pin. A low level will switch the SPI into slave mode and the hardware of the SPI will perform the following actions: 1. The master bit (MSTR) in the SPI Control Register (SPCR) is cleared and the SPI system becomes a slave. The direction of the pins will be switched accord- ing to Table 1. 2. The SPI Interrupt Flag (SPIF) in the SPI Status Register (SPSR) will be set. If the SPI interrupt and the global interrupts are enabled the interrupt routine will be executed. This can be useful in systems with more than one master to avoid that two masters are accessing the SPI bus at the same time. If the SS pin is configured as output pin it can be used as a general purpose output pin which does not affect the SPI system. Note: In cases where the AVR is configured for master mode and it can not be ensured that the SS pin will stay high between two transmissions, the status of the MSTR bit has to be checked before a new byte is written. Once the MSTR bit has been cleared by a low level on the SS line, it must be set by the application to re-enable SPI master mode. In slave mode the SS pin is always an input. When SS is held low, the SPI is activated and MISO becomes output if configured so by the user. All other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means that it will not receive incoming data. Table 2 shows an overview of the SS Pin Functionality. Note: In slave mode, the SPI logic will be reset once the SS pin is brought high. If the SS pin is brought high during a transmission, the SPI will stop sending and receiving immediately and both data received and data sent must be considered as lost., Table 2. Overview of the SS pin functionality Mode SS Configuration SS Pin-level Description High Slave deactivated (deselected) Slave Always Input Low Slave activated (selected) High Master activated (selected) Input Low Master deactivated, switched to slave mode Master High Output Master activated (selected) Low As shown in Table 2, the SS pin in slave mode is always an input pin. A low level acti- vates the SPI of the device while a high level causes its deactivation. A Single Master Multiple Slave System with an AVR configured in master mode and SS configured as output pin is shown in Figure 2. The amount of slaves which can be connected to this AVR is only limited by the number of I/O pins to generate the slave select signals. Figure 2. Multi Slave System SCK SCK MOSI MOSI MISO SMISO 1 SS (PB4) SS

SCK S

MISO 2 PB0 SS

SCK

Master Mode MOSI S PB1 SS

SCK

MOSI S MISO N PB7 SS The ability to connect several devices to the same SPI-bus is based on the fact that only one master and only one slave is active at the same time. The MISO, MOSI and SCK lines of all the other slaves are tristated (configured as input pins of a high impedance with no pullup resistors enabled). A false implementation (e.g. if two slaves are activated at the same time) can cause a driver contention which can lead to a CMOS latchup state and must be avoided. Resistances of 1 to 10 k ohms in series with the pins of the SPI can be used to prevent the system from latching up. However this affects the maximum usable data rate, depending on the loading capacitance on the SPI pins. Unidirectional SPI devices require just the clock line and one of the data lines. If the device is using the MISO line or the MOSI line depends on its purpose. Simple sensors for instance are just sending data (see S2 in Figure 2), while an external DAC usually just receives data (see S3 in Figure 2). 4 AVR151,

AVR151

SPI Timing The SPI has four modes of operation, 0 through 3. These modes essentially control the way data is clocked in or out of an SPI device. The configuration is done by two bits in the SPI control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active high or active low clock. The clock phase (CPHA) control bit selects one of the two fundamentally different transfer formats. To ensure a proper com- munication between master and slave both devices have to run in the same mode. This can require a reconfiguration of the master to match the requirements of different peripheral slaves. The settings of CPOL and CPHA specify the different SPI modes, shown in Table 3. Because this is no standard and specified different in other literature, the configuration of the SPI has to be done carefully. Table 3. SPI Mode Configuration SPI Mode CPOL CPHA Shift SCK-edge Capture SCK-edge000Falling Rising101Rising Falling210Rising Falling311Falling Rising The clock polarity has no significant effect on the transfer format. Switching this bit causes the clock signal to be inverted (active high becomes active low and idle low becomes idle high). The settings of the clock phase, however, selects one of the two dif- ferent transfer timings, which are described closer in the next two chapters. Since the MOSI and MISO lines of the master and the slave are directly connected to each other, the diagrams show the timing of both devices, master and slave. The SS line is the slave select input of the slave. The SS pin of the master is not shown in the diagrams. It has to be inactive by a high level on this pin (if configured as input pin) or by configuring it as an output pin. A.) CPHA = 0 and CPOL = 0 The timing of a SPI transfer where CPHA is zero is shown in Figure 3. Two wave forms (Mode 0) and are shown for the SCK signal - one for CPOL equals zero and another for CPOL equals CPHA = 0 and CPOL = 1 one. (Mode 1) Figure 3. SPI Transfer Format with CPHA = 0 SCK CYCLE# 12345678(FOR REFERENCE) SCK (CPOL=0) SCK (CPOL=1)

MOSI

(FROM MASTER) MSB654321LSB MISO MSB654321LSB * (FROM SLAVE) SS (TO SLAVE)

SAMPLE

*Not defined but normally MSB of character just received., When the SPI is configured as a slave, the transmission starts with the falling edge of the SS line. This activates the SPI of the slave and the MSB of the byte stored in its data register (SPDR) is output on the MISO line. The actual transfer is started by a software write to the SPDR of the master. This causes the clock signal to be generated. In cases where the CPHA equals zero, the SCK signal remains zero for the first half of the first SCK cycle. This ensures that the data is stable on the input lines of both the master and the slave. The data on the input lines is read with the edge of the SCK line from its inac- tive to its active state (rising edge if CPOL equals zero and falling edge if CPOL equals one). The edge of the SCK line from its active to its inactive state (falling edge if CPOL equals zero and rising edge if CPOL equals one) causes the data to be shifted one bit further so that the next bit is output on the MOSI and MISO lines. After eight clock pulses the transmission is completed. In both the master and the slave device the SPI interrupt flag (SPIF) is set and the received byte is transferred to the receive buffer. B.) CPHA = 1 and CPOL = 0 The timing of a SPI transfer where CPHA is one is shown in Figure 4. Two wave forms (Mode 2) and are shown for the SCK signal - one for CPOL equals zero and another for CPOL equals CPHA = 1 and CPOL = 1 one. (Mode 3) Figure 4. SPI Transfer Format with CPHA = 1 SCK CYCLE# 12345678(FOR REFERENCE) SCK (CPOL=0) SCK (CPOL=1)

MOSI

(FROM MASTER) MSB654321LSB MISO * MSB654321LSB (FROM SLAVE) SS (TO SLAVE)

SAMPLE

*Not defined but normally LSB of previously transmitted character. Like in the previous cases the falling edge of the SS lines selects and activates the slave. Compared to the previous cases, where CPHA equals zero, the transmission is not started and the MSB is not output by the slave at this stage. The actual transfer is started by a software write to the SPDR of the master what causes the clock signal to be generated. The first edge of the SCK signal from its inactive to its active state (rising edge if CPOL equals zero and falling edge if CPOL equals one) causes both the master and the slave to output the MSB of the byte in the SPDR. As shown in Figure 4, there is no delay of half a SCK-cycle like in Mode 0 and 1. The SCK line changes its level immediately at the beginning of the first SCK-cycle. The data on the input lines is read with the edge of the SCK line from its active to its inactive state (falling edge if CPOL equals zero and rising edge if CPOL equals one). After eight clock pulses the transmission is completed. In both the master and the slave device the SPI interrupt flag (SPIF) is set and the received byte is transferred to the receive buffer. 6 AVR151,

AVR151

Considerations for high speed Parts which run at higher system clock frequencies and SPI modules capable of running transmissions at speed grades up to half the system clock require a more specific timing to match the needs of both the sender and receiver. The following two diagrams show the timing of the AVR in master and in slave mode for the SPI Modes 0 and 1. The exact values of the displayed times vary between the different parts and are not an issue in this applica- tion note. However the functionality of all parts is in principle the same so that the following considerations apply to all parts. Figure 5. Timing Master Mode

SS

6 1

SCK

(CPOL = 0) 2 2

SCK

(CPOL = 1) 453

MISO

(Data Input) MSB ... LSB78

MOSI

(Data Output) MSB ... LSB The minimum timing of the clock signal is given by the times “1” and “2”. The value “1” specifies the SCK period while the value “2” specifies the high / low times of the clock signal. The maximum rise and fall time of the SCK signal is specified by the time “3”. These are the first timings of the AVR to check if they match the requirements of the slave. The Setup time “4” and Hold time “5” are important times because they specify the requirements the AVR has on the interface of the slave. These times determine how long before the clock edge the slave has to have valid output data ready and how long after the clock edge this data has to be valid. If the Setup and Hold time are long enough the slave suits to the requirements of the AVR but does the AVR suit to the requirements of the slave? The time “6” (Out to SCK) specifies the minimum time the AVR has valid output data ready before the clock edge occurs. This time can be compared to the Setup time “4” of the slave. The time “7” (SCK to Out) specifies the maximum time after which the AVR outputs the next data bit while the time “8” (SCK to Out high) the minimum time specifies during which the last data bit is valid on the MOSI line after the SCK was set back to its idle state., Figure 6. Timing Slave Mode

SS SCK

(CPOL = 0) 11 11

SCK

(CPOL = 1) 13 14 12

MOSI

(Data Input) MSB ... LSB 15 15

MISO

(Data Output) MSB ... LSB X In principle the timings are the same in slave mode like previously described in master mode. Because of the switching of the roles between master and slave the requirements on the timing are inverted as well. The minimum times of the master mode are now max- imum times and vice versa. SPI Transmission A write collision occurs if the SPDR is written while a transfer is in progress. Since this Conflicts register is just single buffered in the transmit direction, writing to SPDR causes data to be written directly into the SPI shift register. Because this write operation would corrupt the data of the current transfer, a write-collision error in generated by setting the WCOL bit in the SPSR. The write operation will not be executed in this case and the transfer continues undisturbed. A write collision is generally a slave error because a slave has no control over when a master will initiate a transfer. A master, however, knows when a transfer is in progress. Thus a master should not generate write collision errors, although the SPI logic can detect these errors in a master as well as in a slave mode. Emulating the SPI When emulating the SPI using the ICE200 hardware emulator, be aware of the fact that the peripherals on this emulator are not stopped on a break point but continue to run with the speed they are configured for. When emulating the SPI using the ICEPRO the timing can be less accurate than it is the case on the part itself. This is caused by longer internal signal lines of the ICEPRO which is the price we had to pay for its ability to upgrade and its flexibility. Setup the SPI The configuration of the SPI in master mode will be shown in two different ways. The first example will show how to implement an SPI communication which is controlled by polling the interrupt flags. The second example will show how to implement an interrupt controlled communication. A communication between two AVR devices will be shown by sending a “Text String” from the part configured as master to the other part configured as slave. The received characters will be compared to the expected ones and the result of this communication test will be output on the Port D. These examples are well suited to be implement by using two development boards like the STK500. In all the examples shown here the SPI is configured to run in mode 0 with MSB trans- mitted first. This is done by setting the bits CPOL, CPHA and DORD in the register SPCR to zero. In the same register the SPI is enabled by setting the SPE bit, while the 8 AVR151,

AVR151

SCK frequency is specified to CK/4 in the first example and the assembler code of the second example. It is set to CK/16 in the C code of the second example. To compare the configuration of the SPI in the different examples the attention has to be directed on the settings of the Master / Slave Select (MSTR) bit and the SPI Interrupt Enable (SPIE) bit. Notes: 1. Because both examples show the transmission between a single master and a single slave it is not necessary to check if the MSTR bit is still set before the master initiates a new transmission. This code has to be added in a multi master application. 2. Although the settings of the Clock Rate Select bits have no effect in slave mode it has to be ensured that the system clock (CK) of the slave is at least four times higher than the SPI clock (SCK). 3. Pending SPI interrupts are cleared by a dummy access to the SPSR and the SPDR. Four files come along with this application note which contain the assembler and C code shown in this examples. To run the code, setup two STK500 development boards as shown in Figure 7. The code is written for ATmega162, but can be compiled for any part with hardware SPI and PORTA, PORTB and PORTD. Figure 7. Hardware setup STK500 #1 STK500 #2 8 LEDs 8 LEDs PORTD PORTD

PORTB

ATmega162 ATmega162 as SPI Master as SPI Slave

PORTA

8 switches, Example 1 - SPI communication controlled by polling: Master Side: If no interrupts are used there is just the SPI module and its pins to configure. Important in this example is the setting of the SS pin as output pin. This has to be done before the SPI is enabled in master mode. Enabling the SPI while the SS pin is still configured as an input pin would cause the SPI to switch to slave mode immediately if a low level is applied to this pin. This pin is always configured as an input pin in slave mode (see Fig- ure 8 on page 10). Using polling gives the fastest communication. This is why polling is most commonly used in master mode. Figure 8. Polled master - initialization and transmission Master Initialization Send String Configure /SS, MOSI and SCK as Current output pins character Yes = 0 ? No Set bits SPE and Return MSTR of the Copy character to SPCR register SPDR register Clear SPI Interrupt Wait for SPI Flag by reading Interrupt Flag SPSR and SPDR Advance to next character of string Return Slave Side: To configure the AVR to run in slave mode there is no order required in which the regis- ters have to be initialized. The MISO pin has to be defined as an output pin, while all other pins are configured automatically as input pins if the SPI is enabled (see Table 9). To configure the AVR to run in slave mode the MSTR bit has to be set to zero. In this case the Clock Rate Select bits SPR0 and SPR1 do not care because of the synchro- nous transmission. All other settings of the SPI configuration register (SPCR) have to be the same as in master mode. This is essential for a successful communication between the two devices. 10 AVR151,

AVR151 Figure 9. Polled slave - initialization and reception

Slave Receive/Verify Initialization String Configure MISO Current as output pin character Yes = 0 ? No Transmission Set bit SPE of the successful SPCR register Wait for SPI Interrupt Flag Clear SPI Interrupt Flag by reading SPDR = SPSR and SPDR current No character ? Yes Transmission Return failed Advance to next character of string, Example 2 - SPI In master mode interrupt controlled communication makes mainly sense if the SCK communication controlled by clock is generated by dividing the system clock by a large division factor (like 64 or 128). interrupts: In this case the processor can do other processing instead of just waiting to send/receive the next byte. In slave mode where the part does not know when a com- munication starts an interrupt controlled implementation can ensure that the part will react in time so that write collision errors will be avoided. Master Side: The initialization of the SPI happens in a similar way to the one in the previous example. Like before in master mode the SS pin has to be set as output first and then the SPI can be enabled. The SPI interrupt is enabled by setting the SPIE bit in the SPCR. Figure 10. Interrupt controlled master - initialization and transmission Master SPI Interrupt Initialization Handler Send String Configure /SS, Advance to next MOSI and SCK as character of string ClearToSend = output pins true ? Current Yes Set bits SPE and character Yes MSTR of the = 0 ? Copy character to SPCR register SPDR No No Select SPI speed Copy character to ClearToSend = ClearToSend = and enable SPI SPDR register true false Interrupt Clear SPI Interrupt Return Send String Flag by reading SPSR and SPDR Enable global interrupts Return Slave Side: A slave never knows when the master is going to start a new communication. Interrupts are a perfect feature to react on such undetermined events so this is a common way to implement the SPI in slave mode. In this example the main program has to be notified about transmission errors and the completion of the transmission. 12 AVR151,

AVR151 Figure 11. Interrupt controlled slave - initialization and transmission

Slave SPI Interrupt Receive/Verify Initialization Handler String Configure MISO SPDR = as output pin current No Use LEDs to show character ? TransmitState Yes Set bit SPE of the SPCR register Advance to next TransmitState = character of string error Disable SPI Enable SPI Current Interrupt Interrupt character = 0 ? Yes Clear SPI Interrupt Flag by reading TransmitState = SPSR and SPDR success No Disable SPI Enable global Interrupt interrupts Return Return,

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AVR465: Single-Phase Power/Energy Meter with Tamper Detection Features • Cost-Effective and Flexible Single-Phase Energy Meter • Fulfills IEC 61036 Accuracy Requirements for Class 1 Meters • Detects, Signals and Continues to Measure Accurately Under At Least 20 Different Tamper Conditions • Design E
AVR453: Smart Battery Reference Design
AVR453: Smart Battery Reference Design Features • Support for up to 4 Li-Ion series-connected battery cells • Battery protection by dedicated Hardware - Deep under voltage protection - Over-current protection during charging - Over-current protection during discharging - Short circuit protection • C
8-bit Microcontroller Application Note AVR450: Battery Charger for SLA, NiCd, NiMH and Li-Ion Batteries Features
8-bit Microcontroller Application Note Rev. 1659B–AVR–11/02 AVR450: Battery Charger for SLA, NiCd, NiMH and Li-Ion Batteries Features • Complete Battery Charger Design • Modular “C” Source Code and Extremely Compact Assembly Code • Low Cost • Supports Most Common Battery Types • Fast Charging Algori
Getting started with the AVR battery charger reference design.
Getting started with the AVR battery charger reference design. The AVR battery charger reference design is designed for use with several types of batteries and various number of battery cells. The AVR battery charger reference design is supplied with resistor values for scaling down the charge volta
8-bit Microcontroller Application Note
8-bit Microcontroller Application Note Rev. 2534A–AVR–05/03 AVR415: RC5 IR Remote Control Transmitter Features • Utilizes ATtiny28 Special HW Modulator and High Current Drive Pin • Size Efficient Code, Leaves Room for Large User Code • Low Power Consumption through Intensive Use of Sleep Modes • Cos
AVR336: ADPCM Decoder
AVR336: ADPCM Decoder Features • AVR Application Decodes ADPCM Signal in Real-Time • Supports Bit Rates of 16, 24, 32 and 40 kbit/s • More Than One Minute Playback Time on ATmega128 (at 16 kbit/s) • Decoded Signal Played Using Timer/Counter in PWM Mode 1 Introduction Adaptive Differential Pulse Code
8-bit Microcontroller Application Note
8-bit Microcontroller Application Note Rev. 1181B–AVR–04/03 AVR360: Step Motor Controller Features • High-speed Step Motor Controller • Interrupt Driven • Compact Code (Only 10 Bytes Interrupt Routine) • Very High Speed • Low Computing Requirement • Supports all AVR Devices Introduction This applica
8-bit RISC Microcontroller Application Note AVR335: Digital Sound Recorder with AVR and Serial DataFlash Features
8-bit RISC Microcontroller Application Note Rev. 1456B–01/04 AVR335: Digital Sound Recorder with AVR and Serial DataFlash Features • Digital Voice Recorder • 8-bit Sound Recording • 8 KHz Sampling Rate • Sound Frequency up to 4000 Hz • Maximum Recording Time 2 1/4 Minutes • Very Small Board Size • O
USB in a Nutshell. Making Sense of the USB Standard.
USB in a Nutshell. Making Sense of the USB Standard. Starting out new with USB can be quite daunting. With the USB 2.0 specification at 650 pages one could easily be put off just by the sheer size of the standard. This is only the beginning of a long list of associated standards for USB. There are U
What is USB Enumeration? What does enumeration look like?
What is USB Enumeration? Enumeration is the process by which a USB device is attached to a system and is assigned a specific numerical address that will be used to access that particular device. It is also the time at which the USB host controller queries the device in order to decide what type of d
Draft
CYCLIC REDUNDANCY CHECKS IN USB Introduction The USB specification calls for the use of Cyclic Redundancy Checksums (CRC) to protect all non-PID fields in token and data packets from errors during transmission. This paper describes the mathematical basis behind CRC in an intuitive fashion and then e
File: X:\USERS\IGOR\DOC\WORD\Atmel\USB to RS232 Application Note\Firmware\USBtoRS232_ATmega8\AVR Studio 4 project\USBtoRS232.asm 1.2.2004
1 ;*************************************************************************** 2 ;* USBSTACKFORTHEAVRFAMILY3;* 4 ;* File Name :"USBtoRS232.asm" 5 ;* Title :AVR309:USB to UART protocol converter 6 ;* Date :01.02.2004 7 ;* Version :2.8 8 ;* Target MCU :ATmega8 9 ;* AUTHOR :Ing. Igor Cesko 10 ;* Slovak
File: X:\USERS\IGOR\DOC\WORD\Atmel\USB to RS232 Application Note\Firmware\USBtoRS232_AT90S2313\AVR Studio 4 project\USB90S2313.asm 26.1.2004
1 ;*************************************************************************** 2 ;* USBSTACKFORTHEAVRFAMILY3;* 4 ;* File Name :"USB90S2313.asm" 5 ;* Title :AVR309:USB to UART protocol converter (simple - small FIFO) 6 ;* Date :26.01.2004 7 ;* Version :2.2 8 ;* Target MCU :AT90S2313-10 9 ;* AUTHOR :I
AVR309: Software Universal Serial Bus (USB)
AVR309: Software Universal Serial Bus (USB) Features • USB (Universal Serial Bus) protocol implemented in firmware • Supports Low Speed USB (1.5Mbit/s) in accordance with USB2.0 • Implementation runs on very small AVR devices, from 2kBytes and up • Few external components required - One resistor for
Application Note
8-bit Microcontrollers Application Note AVR270: USB Mouse Demonstration Features • Runs with AT90USB Microcontrollers at 8MHz • USB Low Power Bus Powered Device (less then 100mA) • Supported by any PC running Windows® (98SE or later), Linux® or Mac OS®. • 3Kbytes of Code Required • X, Y Movement, Le