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8-bit Microcontroller Application Note Rev. 0938B–AVR–01/03 AVR204: BCD Arithmetics Features • Conversion 16 Bits ↔ 5 Digits, 8 Bits ↔ 2 Digits • 2-digit Addition and Subtraction • Superb Speed and Code Density • Runable Example Program Introduction This application note lists routines for BCD arithmetics. A listing of all implementations with key performance specifications is given in Table 1. Table 1. Performance Figures Summary Code Size Execution Time Application (Words) (Cycles) 16-bit Binary to 5-digit BCD Conversion 25 760 8-bit Binary to 2-digit BCD Conversion 6 28 5-digit BCD to 16-bi...
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8-bit

Microcontroller Application Note

Rev. 0938B–AVR–01/03

AVR204: BCD Arithmetics Features

• Conversion 16 Bits ↔ 5 Digits, 8 Bits ↔ 2 Digits • 2-digit Addition and Subtraction • Superb Speed and Code Density • Runable Example Program

Introduction

This application note lists routines for BCD arithmetics. A listing of all implementations with key performance specifications is given in Table 1. Table 1. Performance Figures Summary Code Size Execution Time Application (Words) (Cycles) 16-bit Binary to 5-digit BCD Conversion 25 760 8-bit Binary to 2-digit BCD Conversion 6 28 5-digit BCD to 16-bit Binary Conversion 30 108 2-digit BCD to 8-bit Binary Conversion 4 26 2-digit Packed BCD Addition 19 19 2-digit Packed BCD Subtraction 13 15 16-bit Binary to 5-digit BCD Conversion – “bin2BCD16” This subroutine converts a 16-bit binary value to a 5-digit packed BCD number. The implementation is Code Size optimized. This implementation uses the Z-pointer's auto-decrement facility, and can not be used as is for the AT90Sxx0x series. To use this routine on an AT90Sxx0x, add an “INC ZL” instruction where indicated in the file listing.,

Algorithm Description “bin2BCD16” implements the following algorithm:

1. Load Loop counter with 16. 2. Clear all three bytes of result. 3. Shift left input value Low byte. 4. Shift left carry into input value High byte. 5. Shift left carry into result byte 0 (two least significant digits). 6. Shift left carry into result byte 1. 7. Shift left carry into result byte 2 (most significant digit). 8. Decrement Loop counter 9. If Loop counter is zero, return from subroutine. 10. Add $03 to result byte 2. 11. If bit 3 is zero after addition, restore old value of byte 2. 12. Add $30 to result byte 2. 13. If bit 7 is zero after addition, restore old value of byte 2. 14. Add $03 to result byte 1. 15. If bit 3 is zero after addition, restore old value of byte 1. 16. Add $30 to result byte 1. 17. If bit 7 is zero after addition, restore old value of byte 1. 18. Add $03 to result byte 0. 19. If bit 3 is zero after addition, restore old value of byte 0. 20. Add $30 to result byte 0. 21. If bit 7 is zero after addition, restore old value of byte 0. 22. Goto Step 3. In the implementation. Steps 10 - 21 are carried out inside a loop, where the Z-pointer is used for successive access of all three bytes of the result. This is shown in the flow chart shown in Figure 1. 2 AVR204,

AVR204 Figure 1. “bin2BCD16” Flow Chart

BIN2BCD16 LOOP COUNTER ← 16 CLEAR RESULT (3 BYTES) SHIFT LEFT INPUT LOW BYTE SHIFT LEFT INPUT HIGH BYTE WITH CARRY SHIFT LEFT RESULT BYTE 0 WITH CARRY SHIFT LEFT RESULT BYTE 1 WITH CARRY SHIFT LEFT RESULT BYTE 2 WITH CARRY

DECREMENT

LOOP COUNTER LOOP Y

RETURN

COUNTER = 0

N

Z ← ADRESS OF RESULT BYTE 2 + 1 Z ← Z 1, TMP16A ← @Z TMP16A ← TMP16A + $03 TMP16A ← TMP16A + $30

N

BIT 3 OF N BIT 7 OFNZ= ADDRESS Y TMP16A SET? TMP16A SET? OF RESULT BYTE 0? Y Y @Z ← TMP16A @Z ← TMP16A,

Usage 1. Load the 16-bit register variable “fbinH:fbinL” with the 16-bit number to be con-

verted (High byte in “fbinH”). 2. Call “bin2BCD16”. 3. The result is found in the 3-byte register variable “fBCD2:fBCD1:fBCD0” with MSD in the lower nibble of “fBCD2”.

Performance

Table 2. “bin2BCD16” Register Usage Register Input Internal Output R13 “fBCD0” – BCD Digits 1 and 0 R14 “fBCD1” – BCD Digits 2 and 3 R15 “fBCD2” – BCD Digit 4 R16 “fbinL” – Binary Value Low Byte R17 “fbinH” – Binary Value High Byte R18 “cnt16a” – Loop Counter R19 “tmp16a” – Temporary Storage R30 ZL R31 ZH Table 3. “bin2BCD16” Performance Figures Parameter Value Code Size (Words) 25 Average Execution Time (Cycles) 760 Register Usage • Low Registers :3 • High Registers :4 • Pointers :Z Interrupts Usage None Peripherals Usage None 4 AVR204,

AVR204

8-bit Binary to 2-digit This subroutine converts an 8-bit binary value to a 2-digit BCD number. The binary num-

BCD Conversion – ber must not exceed 99, since a 2-digit BCD number can only represent 0 - 99. The

implementation does not generate a packed result, i.e., the two digits are represented in “bin2BCD8” two separate bytes. To accomplish this, some smaller modifications must be done to the algorithm as shown in the following section.

Algorithm Description “bin2BCD8” implements the following algorithm:

1. Clear result MSD. 2. Subtract 10 from the 8-bit input number. 3. If result negative, add back 10 to 8-bit input number and return. 4. Increment result MSD and goto step 2. LSD of the result is found in the same register as the input number. If a packed result is needed, make the following changes to the algorithm: • Instead of incrementing MSD in Step 4, add $10 to MSD. • After adding back 10 to the input number in step 3, add LSD and MSD together. Where to make these changes is indicated in the program listing. Figure 2. “bin2BCD8” Flow Chart BIN2BCD8 CLEAR RESULT MSD INPUT ← INPUT 10 RESULT N INCREMENT RESULT MSD NEGATIVE ?

Y

INPUT ← INPUT + 10

RETURN Usage 1. Load the register variable “fbin” with the value to be converted.

2. Call “bin2BCD8”. 3. The result MSD and LSD is found in “fBCDH” and “fBCDL”, respectively.,

Performance

Table 4. “bin2BCD8” Register Usage Register Input Internal Output R16 “fbin” – Binary Value “tBCDL” – LSD of Result R17 “tBCDH” – MSD of Result Table 5. “bin2BCD8” Performance Figures Parameter Value Code Size (Words) 6 + return Average Execution Time (Cycles) 28 Register Usage • Low registers :None • High registers :2 • Pointers :None Interrupts Usage None Peripherals Usage None 5-digit BCD to 16-bit This subroutine converts a 5-digit packed BCD number to a 16-bit binary value.

BCD Conversion –

“BCD2bin16”

Algorithm Description Let a, b, c, d, e denote the 5 digits in the BCD number (a = MSD, e = LSD). The result is

generated by computing the following equation: 10(10(10(10a + b) + c) + d) + e The four times repeated operation “multiply-by-10-and-add” is implemented as a sub- routine. This subroutine takes the 16-bit register variable “mp10H:mp10L” and the register variable “adder” as input parameters. The subroutine can be called by two sep- arate addresses, “mul10a” and “mul10b”. The difference is summarized as follows: • “mul10a” – multiplies “mp10H:mp10L” and adds the higher nibble of “adder”. • “mul10b” – multiplies “mp10H:mp10L” and adds the lower nibble of “adder”. The subroutine implements the following algorithm: 1. Swap high/low nibble of “adder”. 2. Make a copy of “mp10H:mp10L”. 3. Multiply original by two (Shift left). 4. Multiply copy by eight (Shift left x 3). 5. Add copy and original. 6. Clear upper nibble of “adder”. 7. Add lower nibble of “adder”. 8. If carry set, increment “mp10H”. When calling “mul10b”, Step 1 is omitted. 6 AVR204,

AVR204

The main routine follows this algorithm: 1. Clear upper nibble of BCD byte 2 (MSD). 2. Clear “mp10H”. 3. “mp10H” ← BCD byte 2. 4. “adder” ← BCD byte 1. 5. Call “mul10a”. 6. “adder” ← BCD byte 1. 7. Call “mul10b”. 8. “adder” ← BCD byte 0. 9. Call “mul10a”. 10. “adder” ← BCD byte 0. 11. Call “mul10b”.

Usage 1. Load the 3-byte register variable “fBCD2:fBCD1:fBCD0” with the value to be con-

verted (MSD in the lower nibble of “fBCD2”). 2. Call “BCD2bin16”. 3. The 16-bit result is found in “tbinH:tbinL”.

Performance

Table 6. “BCD2bin16” Register Usage Register Input Internal Output R12 “copyL” – Temporary Value Used by “mul10a/mul10b” R13 “copyH” – Temporary Value Used by “mul10a/mul10B” R14 “mp10L” – Low Byte of “tbinL” – Low Byte of 16- Input to be Multiplied by bit Result “mul10a/mul10b” R15 “mp10H” – High Byte of “tbinH” – High Byte of 16- Input to be Multiplied by bit Result “mul10a/mul10b” R16 “fBCD0” – BCD Digits 1 and 0 R17 “fBCD1” – BCD Digits 2 and 3 R18 “fBCD2” – BCD Digit 4, Table 7. “BCD2bin16” Performance Figures Parameter Value Code Size (Words) 30 Execution Time (Cycles) 108 Register Usage • Low registers :4 • High registers :4 • Pointers :None Interrupts Usage None Peripherals Usage None 2-digit BCD to 8-bit This subroutine converts a 2-digit BCD number to an 8-bit binary value. The implemen-

Binary Conversion – tation does not accept a packed BCD input, i.e., the two digits must be represented in

two separate bytes. To accomplish this, some modifications will have to be made to the “BCD2bin8” algorithm as shown in the following section.

Algorithm Description “BCD2bin8” implements the following algorithm:

1. Subtract 1 from input MSD. 2. If result negative, return. 3. Add 10 to 8-bit result/input LSD. 4. Goto Step 1. The result is found in the same register as the input number LSD. To make the algorithm accept a packed BCD input, use this algorithm: 1. Copy BCD input to result. 2. Clear higher nibble of result. 3. Subtract $10 from input MSD. 4. If half carry set, return. 5. Add decimal 10 to result. 6. Goto Step 3. The program listing shows how and where to make the changes. Figure 3 shows the flowchart which applies to the non-packed input implementation. 8 AVR204,

AVR204

Figure 3. “BCD2bin8” Flow Chart BCD2BIN8 MSD ← MSD 1 MSD N ADD 10 TO LSD/RESULT NEGATIVE ?

Y RETURN Usage 1. Load the register variables “fBCDH” and “fBCDL” with the input MSD and LSD,

respectively. 2. Call “BCD2bin8”. 3. The 8-bit result is found in “tbin”.

Performance

Table 8. “BCD2bin8” Register Usage Register Input Internal Output R16 “fBCDL” – LSD of BCD Input “tbin” – 8-bit of Result R17 “fBCDH” – MSD of BCD Input Table 9. “BCD2bin8” Performance Figures Parameter Value Code Size (Words) 4 + return Average Execution Time (Cycles) 26 Register Usage • Low registers :None • High registers :2 • Pointers :None Interrupts Usage None Peripherals Usage None, 2-digit Packed BCD This subroutine adds two 2-digit packed BCD numbers. The output is the sum of the two

Addition – “BCDadd” input numbers, also as 2-digit packed BCD, and any overflow carry. Algorithm Description “BCDadd” implements the following algorithm:

1. Add the values binary. 2. If half carry set, set BCD carry, add 6 to LSD, and Goto Step 5. 3. Clear BCD carry and add 6 to LSD. 4. If half carry clear after adding 6, LSD ≤ 9, so restore LSD by subtracting 6. 5. Add 6 to MSD. 6. If carry set in step 1, 3, or 5 above, then MSD > 9, so set BCD carry and return. 7. If carry was set during Step 1, restore MSD by subtracting 6.

Figure 4. “BCDadd” Flow Chart BCDADD

BCD1 ← BCD1 + BCD2 CLEAR BCD CARRY

Y

CARRY SET? SET BCD CARRY

N

HALF N BCD1 ← BCD1 + 6 CARRY SET? (LSD ← LSD + 6)

Y HALF

BCD1 ← BCD1 + 6 CARRY SET N BCD1 ← BCD1 – 6 (LSD ← LSD + 6) (LSD > 9)? (RESTORE LSD)

Y

HALF Y SET BCD CARRY CARRY SET?

N

BCD1 ← BCD1 + $60 (MSD ← MSD + 6) N N BCD1 ← BCD1 – $60 CARRY SET? BCD CARRY SET? (RESTORE MSD) Y Y SET BCD CARRY

RETURN

10 AVR204,

AVR204 Usage 1. Load the register variables “BCD1” and “BCD2” with the numbers to be added.

2. Call “BCDadd”. 3. The BCD sum is found in “BCD1” and the overflow carry in “BCD2”.

Performance

Table 10. “BCDadd” Register Usage Register Input Internal Output R16 “BCD1” – BCD Number 1 “BCD1” – BCD Result R17 “BCD2” – BCD Number 2 “BCD2” – Overflow Carry R18 “tmpadd” – Holds Values $06 and $60 to be Added Table 11. “BCDadd” Performance Figures Parameter Value Code Size (Words) 19 Average Execution Time (Cycles) 19 Register Usage • Low registers :None • High registers :3 • Pointers :None Interrupts Usage None Peripherals Usage None 2-digit Packed BCD This subroutine subtract two 2-digit packed BCD numbers. The output is the difference

Subtraction – of the two input numbers, also as 2-digit packed BCD, and any underflow carry.

“BCDsub”

Algorithm Description “BCDadd” implements the following algorithm:

1. Add the values binary. 2. If carry set, set BCD carry. 3. If half carry set, subtract 6 from LSD. 4. If BCD carry clear, return. 5. Subtract six from MSD and set BCD carry. 6. If carry set, set BCD carry.,

Figure 5. “BCDsub” Flow Chart

BCD2SUB BCDA ← BCDA BCDB CLEAR BCD CARRY

Y

CARRY SET? Set BCD CARRY

N

HALF Y BCDA ← BCDA 6 CARRY SET? (LSD ← LSD 6)

N N

BCD CARRY SET?

Y

BCD1 ← BCD1 $60 (MSD ← MSD 6) SET BCD CARRY

N

CARRY SET? CLEAR BCD CARRY

Y RETURN Usage 1. Load the register variable “BCDa” with the number to be subtracted and “BCDb”

with the number subtract. 2. Call “BCDsub”. 3. The BCD sum is found in “BCDa” and the underflow carry in “BCDb”. 12 AVR204,

AVR204 Performance

Table 12. “BCDadd” Register Usage Register Input Internal Output R16 “BCDa” – BCD Number to Subtract From “BCD1” – BCD Result R17 “BCDb” – BCD Number to Subtract “BCD2” – Underflow Carry Table 13. “BCDadd” Performance Figures Parameter Value Code Size (Words) 13 Average Execution Time (Cycles) 15 Register Usage • Low registers :None • High registers :2 • Pointers :None Interrupts Usage None Peripherals Usage None,

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http://www.atmel.com © Atmel Corporation 2003. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical components in life support devices or systems. ATMEL® and AVR® are the registered trademarks of Atmel. Other terms and product names may be the trademarks of others. Printed on recycled paper. 0938B–AVR–01/03 0M]
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