Download: Microcontroller Core Features: RA5/SS/AN4 7 34 RB1RE0/RD/AN5 8 33 RB0/INT

Device Pins A/D PSP Pin Diagram PIC16C63A 28 NO NO PDIP, Windowed CERDIP PIC16C73B 28 YES NO MCLR/VPP 1 40 RB7 PIC16C65B 40 NO YES RA0/AN0 2 39 RB6 RA1/AN1 3 38 RB5 PIC16C74B 40 YES YES RA2/AN2 4 37 RB4 RA3/AN3/VREF 5 36 RB3 RA4/T0CKI 6 35 RB2 Microcontroller Core Features: RA5/SS/AN4 7 34 RB1RE0/RD/AN5 8 33 RB0/INT RE1/WR/AN6 9 32 VDD • High-performance RISC CPU RE2/CS/AN7 10 31 VSS VDD 11 30 RD7/PSP7 • Only 35 single word instructions to learn VSS 12 29 RD6/PSP6 OSC1/CLKIN 13 28 RD5/PSP5 • All single cycle instructions except for program OSC2/CLKOUT 14 27 RD4/PSP4 branches which are two cycl...
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Device Pins A/D PSP Pin Diagram PIC16C63A 28 NO NO PDIP, Windowed CERDIP PIC16C73B 28 YES NO MCLR/VPP 1 40 RB7 PIC16C65B 40 NO YES RA0/AN0 2 39 RB6 RA1/AN1 3 38 RB5 PIC16C74B 40 YES YES RA2/AN2 4 37 RB4 RA3/AN3/VREF 5 36 RB3 RA4/T0CKI 6 35 RB2

Microcontroller Core Features: RA5/SS/AN4 7 34 RB1RE0/RD/AN5 8 33 RB0/INT

RE1/WR/AN6 9 32 VDD • High-performance RISC CPU RE2/CS/AN7 10 31 VSS VDD 11 30 RD7/PSP7 • Only 35 single word instructions to learn VSS 12 29 RD6/PSP6 OSC1/CLKIN 13 28 RD5/PSP5 • All single cycle instructions except for program OSC2/CLKOUT 14 27 RD4/PSP4 branches which are two cycle RC0/T1OSO/T1CKI 15 26 RC7/RX/DTRC1/T1OSI/CCP2 16 25 RC6/TX/CK • Operating speed: DC - 20 MHz clock input RC2/CCP1 17 24 RC5/SDORC3/SCK/SCL 18 23 RC4/SDI/SDA DC - 200 ns instruction cycle RD0/PSP0 19 22 RD3/PSP3 RD1/PSP1 20 21 RD2/PSP2 • 4K x 14 words of Program Memory, 192x8bytes of Data Memory (RAM) • Interrupt capability (up to 12 internal/external interrupt sources) Peripheral Features: • Eight level deep hardware stack • Timer0: 8-bit timer/counter with 8-bit prescaler • Direct, indirect, and relative addressing modes • Timer1: 16-bit timer/counter with prescaler, • Power-on Reset (POR) can be incremented during sleep via external crystal/clock • Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler • Watchdog Timer (WDT) with its own on-chip RC oscillator for reliable operation • Two Capture, Compare, PWM modules • Programmable code-protection • Capture is 16-bit, max. resolution is 12.5 ns, Compare is 16-bit, max. resolution is 200 ns, • Power saving SLEEP mode PWM maximum resolution is 10-bit • Selectable oscillator options • 8-bit multi-channel Analog-to-Digital converter • Low-power, high-speed CMOS EPROM • Synchronous Serial Port (SSP) with Enhanced technology SPI and I2C • Fully static design • Universal Synchronous Asynchronous Receiver • In-Circuit Serial Programming™ (ICSP) Transmitter (USART/SCI) • Wide operating voltage range: 2.5V to 5.5V • Parallel Slave Port (PSP) 8-bits wide, with • High Sink/Source Current 25/25 mA external RD, WR and CS controls • Commercial, Industrial and Extended temperature • Brown-out detection circuitry for ranges Brown-out Reset (BOR) • Low-power consumption: - < 2 mA @ 5V, 4 MHz - 22.5 µA typical @ 3V, 32 kHz - < 1 µA typical standby current

PIC16C74B M PIC16C63A/65B/73B/74B

28/40-Pin 8-Bit CMOS Microcontrollers 1998 Microchip Technology Inc. DS30605A-page 1,

Pin Diagrams SDIP, SOIC, SSOP, Windowed CERDIP SDIP, SOIC, SSOP, Windowed CERDIP

MCLR/VPP • 1 28 RB7 MCLR/VPP • 1 28 RB7 RA0/AN0 2 27 RB6 RA0 2 27 RB6 RA1/AN1 3 26 RB5 RA1 3 26 RB5 RA2/AN2 4 25 RB4 RA2 4 25 RB4 RA3/AN3/VREF 5 24 RB3 RA3 5 24 RB3 RA4/T0CKI 6 23 RB2 RA4/T0CKI 6 23 RB2 RA5/SS/AN4 7 22 RB1 RA5/SS 7 22 RB1 VSS 8 21 RB0/INT VSS 8 21 RB0/INT OSC1/CLKIN 9 20 VDD OSC1/CLKIN 9 20 VDD OSC2/CLKOUT 10 19 VSS OSC2/CLKOUT 10 19 VSS RC0/T1OSO/T1CKI 11 18 RC7/RX/DT RC0/T1OSO/T1CKI 11 18 RC7/RX/DT RC1/T1OSI/CCP2 12 17 RC6/TX/CK RC1/T1OSI/CCP2 12 17 RC6/TX/CK RC2/CCP1 13 16 RC5/SDO RC2/CCP1 13 16 RC5/SDO RC3/SCK/SCL 14 15 RC4/SDI/SDA RC3/SCK/SCL 14 15 RC4/SDI/SDA

PIC16C73B PIC16C63A PDIP, Windowed CERDIP MQFP TQFP

MCLR/VPP 1 40 RB7 RA0 2 39 RB6 RA1 3 38 RB5 RA2 4 37 RB4 RA3 5 36 RB3 RA4/T0CKI 6 35 RB2 RA5/SS 7 34 RB1 RC7/RX/DT 1 33 NC RE0/RD 8 33 RB0/INT RD4/PSP4 2 32 RC0/T1OSO/T1CKI RE1/WR 9 32 VDD RD5/PSP5 3 31 OSC2/CLKOUT RE2/CS 10 31 VSS RD6/PSP6 4 30 OSC1/CLKIN VDD 11 30 RD7/PSP7 RD7/PSP7 5 29 VSS VSS 12 29 RD6/PSP6 VSS 6 28 VDD OSC1/CLKIN 13 28 RD5/PSP5 VDD 7

PIC16C65B 27 RE2/CS

OSC2/CLKOUT 14 27 RD4/PSP4 RB0/INT 8 26 RE1/WR RC0/T1OSO/T1CKI RC7/RX/DT RB1 9 25 RE0/RD15 26 10 24 RC1/T1OSI/CCP2 RC6/TX/CK RB2 RA5/SS16 25 RB3 11 23 RA4/T0CKI RC2/CCP1 17 24 RC5/SDO RC3/SCK/SCL 18 23 RC4/SDI/SDA RD0/PSP0 19 22 RD3/PSP3 RD1/PSP1 20 21 RD2/PSP2

PIC16C65B PLCC

RA4/T0CKI 7 39 RB3 RA5/SS 8 38 RB2 RE0/RD 9 37 RB1 RE1/WR 10 36 RB0/INT RE2/CS 11 35 VDD VDD 12 PIC16C65B 34 VSSVSS 13 33 RD7/PSP7 OSC1/CLKIN 14 32 RD6/PSP6 OSC2/CLKOUT 15 31 RD5/PSP5 RC0/T1OSO/T1CKI 16 30 RD4/PSP4 NC 17 29 RC7/RX/DT RC1/T1OSI/CCP2 18 6 RA3 RC2/CCP1 19 5 RA2 RC3/SCK/SCL 20 4 RA1 RD0/PSP0 21 3 RA0 RD1/PSP1 22 2 MCLR/VPP RD2/PSP2 23 1 NC RD3/PSP3 24 44 RB7 RC4/SDI/SDA 25 43 RB6 RC5/SDO 26 42 RB5 RC6/TX/CK 27 41 RB4 NC 28 40 NC NC 12 44 RC6/TX/CK NC 13 43 RC5/SDO RB4 14 42 RC4/SDI/SDA RB5 15 41 RD3/PSP3 RB6 16 40 RD2/PSP2 RB7 17 39 RD1/PSP1 MCLR/VPP 18 38 RD0/PSP0 RA0 19 37 RC3/SCK/SCL RA1 20 36 RC2/CCP1 RA2 21 35 RC1/T1OSI/CCP2 RA3 22 34 NC

DS30605A-page 2 1998 Microchip Technology Inc.

,

Pin Diagrams (Cont.’d) PLCC MQFP TQFP

RA4/T0CKI 7 39 RB3 RA5/SS/AN4 8 38 RB2 RC7/RX/DT 1 33 NC RE0/RD/AN5 9 37 RB1 RD4/PSP4 2 32 RC0/T1OSO/T1CKI RE1/WR/AN6 10 36 RB0/INT RD5/PSP5 3 31 OSC2/CLKOUT RE2/CS/AN7 11 35 VDD RD6/PSP6 4 30 OSC1/CLKIN VDD 12 RD7/PSP7 5 29 VSS VSS 13 PIC16C74B 34

VSS

33 RD7/PSP7 VSS 6 VDD 7 PIC16C74B 28 VDD OSC1/CLKIN 14 32 RD6/PSP6 27 RE2/CS/AN7 OSC2/CLKOUT 15 31 RD5/PSP5 RB0/INT 8 26 RE1/WR/AN6 RC0/T1OSO/T1CKI 16 30 RD4/PSP4 RB1 9 25 RE0/RD/AN5 10 24 NC 17 29 RC7/RX/DT RB2 RA5/SS/AN4 RB3 11 23 RA4/T0CKI

Key Features PICmicro Mid-Range Reference Manual PIC16C63A PIC16C65B PIC16C73B PIC16C74B

(DS33023)

Operating Frequency DC - 20 MHz DC - 20 MHz DC - 20 MHz DC - 20 MHz Resets (and Delays) POR, BOR POR, BOR POR, BOR POR, BOR

(PWRT, OST) (PWRT, OST) (PWRT, OST) (PWRT, OST)

Program Memory (14-bit words) 4K 4K 4K 4K Data Memory (bytes) 192 192 192 192 Interrupts 10 11 11 12 I/O Ports Ports A,B,C Ports A,B,C,D,E Ports A,B,C Ports A,B,C,D,E Timers3333 Capture/Compare/PWM modules2222 Serial Communications SSP, USART SSP, USART SSP, USART SSP, USART Parallel Communications — PSP — PSP

8-bit Analog-to-Digital Module — — 5 input channels 8 input channels

Instruction Set 35 Instructions 35 Instructions 35 Instructions 35 Instructions

RC1/T1OSI/CCP2 18 6 RA3/AN3/VREF RC2/CCP1 19 5 RA2/AN2 RC3/SCK/SCL 20 4 RA1/AN1 RD0/PSP0 21 3 RA0/AN0 RD1/PSP1 22 2 MCLR/VPP RD2/PSP2 23 1 NC RD3/PSP3 24 44 RB7 RC4/SDI/SDA 25 43 RB6 RC5/SDO 26 42 RB5 RC6/TX/CK 27 41 RB4 NC 28 40 NC NC 12 44 RC6/TX/CK NC 13 43 RC5/SDO RB4 14 42 RC4/SDI/SDA RB5 15 41 RD3/PSP3 RB6 16 40 RD2/PSP2 RB7 17 39 RD1/PSP1 MCLR/VPP 18 38 RD0/PSP0 RA0/AN0 19 37 RC3/SCK/SCL RA1/AN1 20 36 RC2/CCP1 RA2/AN2 21 35 RC1/T1OSI/CCP2 RA3/AN3/VREF 22 34 NC 1998 Microchip Technology Inc. DS30605A-page 3,

Table of Contents

1.0 Device Overview ... 5 2.0 Memory Organization... 11 3.0 I/O Ports ... 25 4.0 Timer0 Module ... 37 5.0 Timer1 Module ... 39 6.0 Timer2 Module ... 43 7.0 Capture/Compare/PWM (CCP) Module(s)... 45 8.0 Synchronous Serial Port (SSP) Module ... 51 9.0 Universal Synchronous Asynchronous Receiver Transmitter (USART) ... 61 10.0 Analog-to-Digital Converter (A/D) Module... 75 11.0 Special Features of the CPU... 81 12.0 Instruction Set Summary... 95 13.0 Development Support ... 97 14.0 Electrical Characteristics... 101 15.0 DC and AC Characteristics Graphs and Tables... 123 16.0 Packaging Information ... 125 Appendix A: Revision History ... 137 Appendix B: Device Differences ... 137 Appendix C: Conversion Considerations ... 137 Appendix D: Migration from Baseline to Midrange Devices... 138 Appendix E: Bit/Register Cross-Reference List ... 139 Index ... 141 On-Line Support... 147 Reader Response ... 148 PIC16C63A/65B/73B/74B Product Identification System ... 149

To Our Valued Customers

Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please check our worldwide web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number, found on the bottom outside corner of any page. The last character of the literature number is the version number. e.g., DS30000A is version A of docu- ment DS30000. Errata An errata sheet may exist for current devices, describing minor operational differences (from the data sheet) and rec- ommended workarounds. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s worldwide web site at http://www.microchip.com • Your local Microchip sales office (see last page) • The Microchip Corporate Literature Center; U.S. FAX: (602) 786-7277 When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Corrections to this Data Sheet We constantly strive to improve the quality of all our products and documentation. We have spent a great deal of time to ensure that this document is correct. However, we realize that we may have missed a few things. If you find any information that is missing or appears in error, please: • Fill out and mail in the reader response form in the back of this data sheet, or • E-mail us at email is hidden. We appreciate your assistance in making this a better document. DS30605A-page 4 1998 Microchip Technology Inc., 1.0 DEVICE OVERVIEW There are four devices (PIC16C63A, PIC16C65B, PIC16C73B, PIC16C74B) covered by this data sheet. This document contains device-specific information. These devices come in 28- and 40-pin packages. The Additional information may be found in the PICmicro 28-pin devices do not have a Parallel Slave Port imple- Mid-Range Reference Manual (DS33023) which may mented. The PIC16C6X devices do not have the A/D be obtained from your local Microchip Sales Represen- module implemented. tative or downloaded from the Microchip web site. The Reference Manual should be considered a comple- The following two figures are device block diagrams mentary document to this data sheet, and is highly rec- sorted by pin number; 28-pin for Figure 1-1 and 40-pin ommended reading for a better understanding of the for Figure 1-2. The 28-pin and 40-pin pinouts are listed device architecture and operation of the peripheral in Table 1-1 and Table 1-2 respectively. modules.

FIGURE 1-1: PIC16C63A/PIC16C73B BLOCK DIAGRAM

13 Data Bus 8 PORTA Program Counter EPROM RA0/AN0(2) RA1/AN1(2)4K x 14 RA2/AN2(2) Program 8 Level Stack RAM RA3/AN3/VREF(2) Memory (13-bit) 192x8RA4/T0CKI File RA5/SS/AN4(2)Registers Program 14 Bus RAM Addr(1) 9 PORTB Addr MUX Instruction reg RB0/INT Direct Addr 7 Indirect8 Addr FSR reg RB7:RB1 STATUS reg 8 PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 3 RC2/CCP1 Power-up MUX RC3/SCK/SCL Timer RC4/SDI/SDA Instruction Oscillator RC5/SDO Decode & Start-up Timer RC6/TX/CK Control ALUPower-on RC7/RX/DT Reset 8 Timing Watchdog Generation Timer W reg OSC1/CLKIN Brown-out OSC2/CLKOUT Reset MCLR VDD, VSS Timer0 Timer1 Timer2 A/D(2) Synchronous CCP1 CCP2 Serial Port USART Note 1: Higher order bits are from the STATUS register. 2: The A/D module is not available on the PIC16C63A. 1998 Microchip Technology Inc. DS30605A-page 5,

FIGURE 1-2: PIC16C65B/PIC16C74B BLOCK DIAGRAM

13 Data Bus 8 PORTA Program Counter EPROM RA0/AN0(2) RA1/AN1(2) 4K x 14 RA2/AN2(2) RAM RA3/AN3/VREF(2) Program 8 Level Stack (13-bit) 192 x 8Memory RA4/T0CKI File RA5/SS/AN4(2) Registers Program 14 Bus RAM Addr (1) 9 PORTB Addr MUX Instruction reg Indirect RB0/INTDirect Addr78Addr FSR reg RB7:RB1 STATUS reg 8 PORTC RC0/T1OSO/T1CKI RC1/T1OSI/CCP2 3 RC2/CCP1 Power-up MUX RC3/SCK/SCL Timer RC4/SDI/SDA Instruction Oscillator RC5/SDO Decode & Start-up Timer RC6/TX/CK Control ALUPower-on RC7/RX/DT Reset 8 PORTD Timing Watchdog Generation Timer W reg OSC1/CLKIN Brown-out OSC2/CLKOUT Reset RD7/PSP7:RD0/PSP0 Parallel Slave Port PORTE MCLR VDD, VSS RE0/RD/AN5(2) RE1/WR/AN6(2) Timer0 Timer1 Timer2 A/D(2) RE2/CS/AN7(2) Synchronous CCP1 CCP2 Serial Port USART Note 1: Higher order bits are from the STATUS register. 2: The A/D module is not available on the PIC16C65B. DS30605A-page 6 1998 Microchip Technology Inc.,

TABLE 1-1: PIC16C63A/PIC16C73B PINOUT DESCRIPTION

DIP SOIC I/O/P Buffer Pin Name Description Pin# Pin# Type Type OSC1/CLKIN99IST/CMOS(3) Oscillator crystal input/external clock source input. OSC2/CLKOUT 10 10 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, the OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP11I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0/AN0(4) 2 2 I/O TTL RA0 can also be analog input0 RA1/AN1(4) 3 3 I/O TTL RA1 can also be analog input1 RA2/AN2(4) 4 4 I/O TTL RA2 can also be analog input2 RA3/AN3/VREF(4) 5 5 I/O TTL RA3 can also be analog input3 or analog reference voltage RA4/T0CKI66I/O ST RA4 can also be the clock input to the Timer0 module. Output is open drain type. RA5/SS/AN4(4) 7 7 I/O TTL RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 21 21 I/O TTL/ST(1) RB0 can also be the external interrupt pin. RB1 22 22 I/O TTL RB2 23 23 I/O TTL RB3 24 24 I/O TTL RB4 25 25 I/O TTL Interrupt on change pin. RB5 26 26 I/O TTL Interrupt on change pin. RB6 27 27 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock. RB7 28 28 I/O TTL/ST(2) Interrupt on change pin. Serial programming data. PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 11 11 I/O ST RC0 can also be the Timer1 oscillator output or Timer1 clock input. RC1/T1OSI/CCP2 12 12 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 13 13 I/O ST RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL 14 14 I/O ST RC3 can also be the synchronous serial clock input/output for both SPI and I2C modes. RC4/SDI/SDA 15 15 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 16 16 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 17 17 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 18 18 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. VSS 8, 19 8, 19 P — Ground reference for logic and I/O pins. VDD 20 20 P — Positive supply for logic and I/O pins. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 4: The A/D module is not available on the PIC16C63A. 1998 Microchip Technology Inc. DS30605A-page 7,

TABLE 1-2: PIC16C65B/PIC16C74B PINOUT DESCRIPTION

DIP PLCC QFP I/O/P Buffer Pin Name Description Pin# Pin# Pin# Type Type OSC1/CLKIN 13 14 30 I ST/CMOS(4) Oscillator crystal input/external clock source input. OSC2/CLKOUT 14 15 31 O — Oscillator crystal output. Connects to crystal or resonator in crystal oscillator mode. In RC mode, OSC2 pin outputs CLKOUT which has 1/4 the frequency of OSC1, and denotes the instruction cycle rate. MCLR/VPP1218 I/P ST Master clear (reset) input or programming voltage input. This pin is an active low reset to the device. PORTA is a bi-directional I/O port. RA0/AN0(5) 2 3 19 I/O TTL RA0 can also be analog input0 RA1/AN1(5) 3 4 20 I/O TTL RA1 can also be analog input1 RA2/AN2(5) 4 5 21 I/O TTL RA2 can also be analog input2 RA3/AN3/VREF(5) 5 6 22 I/O TTL RA3 can also be analog input3 or analog reference voltage RA4/T0CKI6723 I/O ST RA4 can also be the clock input to the Timer0 timer/ counter. Output is open drain type. RA5/SS/AN4(5) 7 8 24 I/O TTL RA5 can also be analog input4 or the slave select for the synchronous serial port. PORTB is a bi-directional I/O port. PORTB can be software programmed for internal weak pull-up on all inputs. RB0/INT 33 36 8 I/O TTL/ST(1) RB0 can also be the external interrupt pin. RB1 34 37 9 I/O TTL RB2 35 38 10 I/O TTL RB3 36 39 11 I/O TTL RB4 37 41 14 I/O TTL Interrupt on change pin. RB5 38 42 15 I/O TTL Interrupt on change pin. RB6 39 43 16 I/O TTL/ST(2) Interrupt on change pin. Serial programming clock. RB7 40 44 17 I/O TTL/ST(2) Interrupt on change pin. Serial programming data. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 5: The A/D module is not available on the PIC16C65B. DS30605A-page 8 1998 Microchip Technology Inc.,

TABLE 1-2: PIC16C65B/PIC16C74B PINOUT DESCRIPTION (Cont.’d)

DIP PLCC QFP I/O/P Buffer Pin Name Description Pin# Pin# Pin# Type Type PORTC is a bi-directional I/O port. RC0/T1OSO/T1CKI 15 16 32 I/O ST RC0 can also be the Timer1 oscillator output or a Timer1 clock input. RC1/T1OSI/CCP2 16 18 35 I/O ST RC1 can also be the Timer1 oscillator input or Capture2 input/Compare2 output/PWM2 output. RC2/CCP1 17 19 36 I/O ST RC2 can also be the Capture1 input/Compare1 output/ PWM1 output. RC3/SCK/SCL 18 20 37 I/O ST RC3 can also be the synchronous serial clock input/ output for both SPI and I2C modes. RC4/SDI/SDA 23 25 42 I/O ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO 24 26 43 I/O ST RC5 can also be the SPI Data Out (SPI mode). RC6/TX/CK 25 27 44 I/O ST RC6 can also be the USART Asynchronous Transmit or Synchronous Clock. RC7/RX/DT 26 29 1 I/O ST RC7 can also be the USART Asynchronous Receive or Synchronous Data. PORTD is a bi-directional I/O port or parallel slave port when interfacing to a microprocessor bus. RD0/PSP0 19 21 38 I/O ST/TTL(3) RD1/PSP1 20 22 39 I/O ST/TTL(3) RD2/PSP2 21 23 40 I/O ST/TTL(3) RD3/PSP3 22 24 41 I/O ST/TTL(3) RD4/PSP4 27 30 2 I/O ST/TTL(3) RD5/PSP5 28 31 3 I/O ST/TTL(3) RD6/PSP6 29 32 4 I/O ST/TTL(3) RD7/PSP7 30 33 5 I/O ST/TTL(3) PORTE is a bi-directional I/O port. (3) RE0/RD/AN5(5) 8 9 25 I/O ST/TTL RE0 can also be read control for the parallel slave port, or analog input5. (5) 9 10 26 I/O ST/TTL(3)RE1/WR/AN6 RE1 can also be write control for the parallel slave port, or analog input6. (5) 10 11 27 I/O ST/TTL(3)RE2/CS/AN7 RE2 can also be select control for the parallel slave port, or analog input7. VSS 12,31 13,34 6,29 P — Ground reference for logic and I/O pins. VDD 11,32 12,35 7,28 P — Positive supply for logic and I/O pins. NC — 1,17,28, 12,13, — These pins are not internally connected. These pins should 40 33,34 be left unconnected. Legend: I = input O = output I/O = input/output P = power — = Not used TTL = TTL input ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as an external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. 3: This buffer is a Schmitt Trigger input when configured as general purpose I/O and a TTL input when used in the Parallel Slave Port mode (for interfacing to a microprocessor bus). 4: This buffer is a Schmitt Trigger input when configured in RC oscillator mode and a CMOS input otherwise. 5: The A/D module is not available on the PIC16C65B. 1998 Microchip Technology Inc. DS30605A-page 9, NOTES: DS30605A-page 10 1998 Microchip Technology Inc., 2.0 MEMORY ORGANIZATION 2.2 Data Memory Organization There are two memory blocks in each of these PICmicro The data memory is partitioned into multiple banks microcontrollers. Each block (Program Memory and which contain the General Purpose Registers and the Data Memory) has its own bus so that concurrent Special Function Registers. Bits RP1 and RP0 are the access can occur. bank select bits. Additional information on device memory may be found RP1(1) RP0 (STATUS<6:5>) in the PICmicro Mid-Range Reference Manual (DS33023). = 00 → Bank0 = 01 → Bank1 2.1 Program Memory Organization = 10 → Bank2 (not implemented) = 11 → Bank3 (not implemented) The PIC16C63A/65B/73B/74B microcontrollers have a 13-bit program counter capable of addressing an 8K x Note 1: Maintain this bit clear to ensure upward compati- bility with future products. 14 program memory space. Each device has 4K x 14 words of program memory. Accessing a location above Each bank extends up to 7Fh (128 bytes). The lower the physically implemented address will cause a wrap- locations of each bank are reserved for the Special around. Function Registers. Above the Special Function Regis- The reset vector is at 0000h and the interrupt vector is ters are General Purpose Registers, implemented as at 0004h. static RAM. All implemented banks contain special function registers. Some “high use” special function registers from one bank may be mirrored in another FIGURE 2-1: PROGRAM MEMORY MAP bank for code reduction and quicker access. AND STACK 2.2.1 GENERAL PURPOSE REGISTER FILE PC<12:0> The register file can be accessed either directly, or indi- CALL, RETURN 13 rectly through the File Select Register FSRRETFIE, RETLW (Section 2.5). Stack Level 1 Stack Level 8 Reset Vector 0000h Interrupt Vector 0004h On-chip Program 0005h Memory (Page 0) 07FFh On-chip Program 0800h Memory (Page 1) 0FFFh 1000h 1FFFh User Memory Space 1998 Microchip Technology Inc. DS30605A-page 11,

FIGURE 2-2: REGISTER FILE MAP 2.2.2 SPECIAL FUNCTION REGISTERS

File File The Special Function Registers are registers used by Address Address the CPU and Peripheral Modules for controlling the 00h INDF(1) INDF(1) 80h desired operation of the device. These registers are 01h TMR0 OPTION_REG 81h implemented as static RAM. A list of these registers is give in Table 2-1. 02h PCL PCL 82h 03h STATUS STATUS 83h The special function registers can be classified into two 04h FSR FSR 84h sets; core (CPU) and peripheral. Those registers asso- ciated with the core functions are described in detail in 05h PORTA TRISA 85h this section. Those related to the operation of the 06h PORTB TRISB 86h peripheral features are described in detail in that 07h PORTC TRISC 87h peripheral feature section. 08h PORTD(2) TRISD(2) 88h 09h PORTE(2) TRISE(2) 89h 0Ah PCLATH PCLATH 8Ah 0Bh INTCON INTCON 8Bh 0Ch PIR1 PIE1 8Ch 0Dh PIR2 PIE2 8Dh 0Eh TMR1L PCON 8Eh 0Fh TMR1H 8Fh 10h T1CON 90h 11h TMR2 91h 12h T2CON PR2 92h 13h SSPBUF SSPADD 93h 14h SSPCON SSPSTAT 94h 15h CCPR1L 95h 16h CCPR1H 96h 17h CCP1CON 97h 18h RCSTA TXSTA 98h 19h TXREG SPBRG 99h 1Ah RCREG 9Ah 1Bh CCPR2L 9Bh 1Ch CCPR2H 9Ch 1Dh CCP2CON 9Dh 1Eh ADRES(3) 9Eh 1Fh ADCON0(3) ADCON1(3) 9Fh 20h A0h General General Purpose Purpose Register Register 7Fh FFh Bank 0 Bank 1 Unimplemented data memory locations, read as ’0’. Note 1: Not a physical register. 2: These registers are not implemented on the PIC16C63A/73B, read as '0'. 3: These registers are not implemented on the PIC16C63A/65B, read as '0'. DS30605A-page 12 1998 Microchip Technology Inc., ll tsuuuuuuuuuuuuuuxuuu

TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY

Value on Value on a Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other rese BOR (5)

Bank 0

00h INDF(1) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 000 01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuu 02h PCL(1) Program Counter's (PC) Least Significant Byte 0000 0000 0000 000 03h STATUS(1) IRP(6) RP1(6) RP0 TO PD Z DC C rr01 1xxx rr0q quu 04h FSR(1) Indirect data memory address pointer xxxx xxxx uuuu uuu 05h PORTA(7) — — PORTA Data Latch when written: PORTA pins when read -0x 0000 -0u 000 06h PORTB(8) PORTB Data Latch when written: PORTB pins when read xxxx xxxx uuuu uuu 07h PORTC(8) PORTC Data Latch when written: PORTC pins when read xxxx xxxx uuuu uuu 08h PORTD(3,8) PORTD Data Latch when written: PORTD pins when read xxxx xxxx uuuu uuu 09h PORTE(3,8) — — — — — RE2 RE1 RE0 - -xxx - -uu 0Ah PCLATH(1,2) — — — Write Buffer for the upper 5 bits of the Program Counter -0 0000 -0 000 0Bh INTCON(1) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000 0Ch PIR1 PSPIF(3) ADIF(4) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 000 0Dh PIR2 — — — – — — — CCP2IF - -0 - - 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -00 0000 -uu uuu 11h TMR2 Timer2 module’s register 0000 0000 0000 000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 000 15h CCPR1L Capture/Compare/PWM Register1 (LSB) xxxx xxxx uuuu uuu 16h CCPR1H Capture/Compare/PWM Register1 (MSB) xxxx xxxx uuuu uuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 -00 0000 -00 000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00 19h TXREG USART Transmit Data Register 0000 0000 0000 000 1Ah RCREG USART Receive Data Register 0000 0000 0000 000 1Bh CCPR2L Capture/Compare/PWM Register2 (LSB) xxxx xxxx uuuu uuu 1Ch CCPR2H Capture/Compare/PWM Register2 (MSB) xxxx xxxx uuuu uuu 1Dh CCP2CON — — CCP2X CCP2Y CCP2M3 CCP2M2 CCP2M1 CCP2M0 -00 0000 -00 000 1Eh ADRES(4) A/D Result Register xxxx xxxx uuuu uuu 1Fh ADCON0(4) ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON 0000 00-0 0000 00- Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', Shaded locations are unimplemented, read as '0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: PORTD and PORTE are not implemented on the PIC16C63A/73B, maintain as ’0’. 4: A/D not implemented on the PIC16C63A/65B, maintain as ’0’. 5: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 6: The IRP and RP1 bits are reserved. Always maintain these bits clear. 7: On any device reset, these pins are configured as inputs. 8: This is the value that will be in the port output latch. 1998 Microchip Technology Inc. DS30605A-page 13, ll tsuuuu

TABLE 2-1 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)

Value on Value on a Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other rese BOR (5) Bank 1 80h INDF(1) Addressing this location uses contents of FSR to address data memory (not a physical register) 0000 0000 0000 000 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 111 82h PCL(1) Program Counter's (PC) Least Significant Byte 0000 0000 0000 000 83h STATUS(1) IRP(6) RP1(6) RP0 TO PD Z DC C rr01 1xxx rr0q quu 84h FSR(1) Indirect data memory address pointer xxxx xxxx uuuu uuu 85h TRISA — — PORTA Data Direction Register -11 1111 -11 111 86h TRISB PORTB Data Direction Register 1111 1111 1111 111 87h TRISC PORTC Data Direction Register 1111 1111 1111 111 88h TRISD(3) PORTD Data Direction Register 1111 1111 1111 111 89h TRISE(3) IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -11 8Ah PCLATH(1,2) — — — Write Buffer for the upper 5 bits of the Program Counter -0 0000 -0 000 8Bh INTCON(1) GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000 8Ch PIE1 PSPIE(3) ADIE(4) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 000 8Dh PIE2 — — — — — — — CCP2IE - -0 - - 8Eh PCON — — — — — — POR BOR - -qq - -u 8Fh — Unimplemented — — 90h — Unimplemented — — 91h — Unimplemented — — 92h PR2 Timer2 Period Register 1111 1111 1111 111 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 000 94h SSPSTAT SMP CKE D/APSR/W UA BF 0000 0000 0000 000 95h — Unimplemented — — 96h — Unimplemented — — 97h — Unimplemented — — 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -01 99h SPBRG Baud Rate Generator Register 0000 0000 0000 000 9Ah — Unimplemented — — 9Bh — Unimplemented — — 9Ch — Unimplemented — — 9Dh — Unimplemented — — 9Eh — Unimplemented — — 9Fh ADCON1(4) — — — — — PCFG2 PCFG1 PCFG0 - -000 - -00 Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as '0', Shaded locations are unimplemented, read as '0'. Note 1: These registers can be addressed from either bank. 2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for PC<12:8> whose contents are transferred to the upper byte of the program counter. 3: PORTD and PORTE are not implemented on the PIC16C63A/73B, maintain as ’0’. 4: A/D not implemented on the PIC16C63A/65B, maintain as ’0’. 5: Other (non power-up) resets include: external reset through MCLR and the Watchdog Timer Reset. 6: The IRP and RP1 bits are reserved. Always maintain these bits clear. 7: On any device reset, these pins are configured as inputs. 8: This is the value that will be in the port output latch. DS30605A-page 14 1998 Microchip Technology Inc., 2.2.2.1 STATUS REGISTER It is recommended, therefore, that only BCF, BSF, SWAPF and MOVWF instructions are used to alter the The STATUS register, shown in Figure 2-3, contains STATUS register because these instructions do not the arithmetic status of the ALU, the RESET status and affect the Z, C or DC bits from the STATUS register. For the bank select bits for data memory. other instructions, not affecting any status bits, see the The STATUS register can be the destination for any "Instruction Set Summary." instruction, as with any other register. If the STATUS Note 1: These devices do not use bits IRP and register is the destination for an instruction that affects RP1 (STATUS<7:6>). Maintain these bits the Z, DC or C bits, then the write to these three bits is clear to ensure upward compatibility with disabled. These bits are set or cleared according to the future products. device logic. Furthermore, the TO and PD bits are not writable. Therefore, the result of an instruction with the Note 2: The C and DC bits operate as a borrow STATUS register as destination may be different than and digit borrow bit, respectively, in sub- intended. traction. See the SUBLW and SUBWF instructions for examples. For example, CLRF STATUS will clear the upper-three bits and set the Z bit. This leaves the STATUS register as 000u u1uu (where u = unchanged). FIGURE 2-3: STATUS REGISTER (ADDRESS 03h, 83h) R/W-0 R/W-0 R/W-0 R-1 R-1 R/W-x R/W-x R/W-x IRP RP1 RP0 TO PD Z DCCR= Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: IRP: Register Bank Select bit (used for indirect addressing) 1 = Bank 2, 3 (100h - 1FFh) - not implemented, maintain clear 0 = Bank 0, 1 (00h - FFh) - not implemented, maintain clear bit 6-5: RP1:RP0: Register Bank Select bits (used for direct addressing) 11 = Bank 3 (180h - 1FFh) - not implemented, maintain clear 10 = Bank 2 (100h - 17Fh) - not implemented, maintain clear 01 = Bank 1 (80h - FFh) 00 = Bank 0 (00h - 7Fh) Each bank is 128 bytes bit 4: TO: Time-out bit 1 = After power-up, CLRWDT instruction, or SLEEP instruction 0 = A WDT time-out occurred bit 3: PD: Power-down bit 1 = After power-up or by the CLRWDT instruction 0 = By execution of the SLEEP instruction bit 2: Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero bit 1: DC: Digit carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) (for borrow the polarity is reversed) 1 = A carry-out from the 4th low order bit of the result occurred 0 = No carry-out from the 4th low order bit of the result bit 0: C: Carry/borrow bit (ADDWF, ADDLW,SUBLW,SUBWF instructions) 1 = A carry-out from the most significant bit of the result occurred 0 = No carry-out from the most significant bit of the result occurred Note: For borrow the polarity is reversed. A subtraction is executed by adding the two’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low order bit of the source register. 1998 Microchip Technology Inc. DS30605A-page 15, 2.2.2.2 OPTION_REG REGISTER Note: To achieve a 1:1 prescaler assignment for The OPTION_REG register is a readable and writable the TMR0 register, assign the prescaler to register which contains various control bits to configure the Watchdog Timer. the TMR0 prescaler/WDT postscaler (single assign- able register known also as the prescaler), the External INT Interrupt, TMR0, and the weak pull-ups on PORTB.

FIGURE 2-4: OPTION_REG REGISTER (ADDRESS 81h)

R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: RBPU: PORTB Pull-up Enable bit 1 = PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6: INTEDG: Interrupt Edge Select bit 1 = Interrupt on rising edge of RB0/INT pin 0 = Interrupt on falling edge of RB0/INT pin bit 5: T0CS: TMR0 Clock Source Select bit 1 = Transition on RA4/T0CKI pin 0 = Internal instruction cycle clock (CLKOUT) bit 4: T0SE: TMR0 Source Edge Select bit 1 = Increment on high-to-low transition on RA4/T0CKI pin 0 = Increment on low-to-high transition on RA4/T0CKI pin bit 3: PSA: Prescaler Assignment bit 1 = Prescaler is assigned to the WDT 0 = Prescaler is assigned to the Timer0 module bit 2-0: PS2:PS0: Prescaler Rate Select bits Bit Value TMR0 Rate WDT Rate 000 1 : 2 1 : 1 001 1 : 4 1 : 2 010 1 : 8 1 : 4 011 1 : 16 1 : 8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 DS30605A-page 16 1998 Microchip Technology Inc., 2.2.2.3 INTCON REGISTER Note: Interrupt flag bits get set when an interrupt The INTCON Register is a readable and writable regis- condition occurs regardless of the state of ter which contains various enable and flag bits for the its corresponding enable bit or the global TMR0 register overflow, RB Port change and External enable bit, GIE (INTCON<7>). User soft- RB0/INT pin interrupts. ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. FIGURE 2-5: INTCON REGISTER (ADDRESS 0Bh, 8Bh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-x GIE PEIE T0IE INTE RBIE T0IF INTF RBIF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: GIE: Global Interrupt Enable bit 1 = Enables all un-masked interrupts 0 = Disables all interrupts bit 6: PEIE: Peripheral Interrupt Enable bit 1 = Enables all un-masked peripheral interrupts 0 = Disables all peripheral interrupts bit 5: T0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 interrupt 0 = Disables the TMR0 interrupt bit 4: IINTE: RB0/INT External Interrupt Enable bit 1 = Enables the RB0/INT external interrupt 0 = Disables the RB0/INT external interrupt bit 3: RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt bit 2: T0IF: TMR0 Overflow Interrupt Flag bit 1 = TMR0 register has overflowed (must be cleared in software) 0 = TMR0 register did not overflow bit 1: INTF: RB0/INT External Interrupt Flag bit 1 = The RB0/INT external interrupt occurred (must be cleared in software) 0 = The RB0/INT external interrupt did not occur bit 0: RBIF: RB Port Change Interrupt Flag bit 1 = At least one of the RB7:RB4 pins changed state (must be cleared in software) 0 = None of the RB7:RB4 pins have changed state 1998 Microchip Technology Inc. DS30605A-page 17, 2.2.2.4 PIE1 REGISTER This register contains the individual enable bits for the Note: Bit PEIE (INTCON<6>) must be set to peripheral interrupts. enable any peripheral interrupt.

FIGURE 2-6: PIE1 REGISTER (ADDRESS 8Ch)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: PSPIE(1): Parallel Slave Port Read/Write Interrupt Enable bit 1 = Enables the PSP read/write interrupt 0 = Disables the PSP read/write interrupt bit 6: ADIE(2): A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt bit 5: RCIE: USART Receive Interrupt Enable bit 1 = Enables the USART receive interrupt 0 = Disables the USART receive interrupt bit 4: TXIE: USART Transmit Interrupt Enable bit 1 = Enables the USART transmit interrupt 0 = Disables the USART transmit interrupt bit 3: SSPIE: Synchronous Serial Port Interrupt Enable bit 1 = Enables the SSP interrupt 0 = Disables the SSP interrupt bit 2: CCP1IE: CCP1 Interrupt Enable bit 1 = Enables the CCP1 interrupt 0 = Disables the CCP1 interrupt bit 1: TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0: TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt Note 1: PIC16C63A/73B devices do not have a Parallel Slave Port implemented. This bit location is reserved on these devices. Always maintain this bit clear. 2: PIC16C63A/65B devices do not have an A/D module. This bit location is reserved on these devices. Always maintain this bit clear. DS30605A-page 18 1998 Microchip Technology Inc., 2.2.2.5 PIR1 REGISTER Note: Interrupt flag bits get set when an interrupt This register contains the individual flag bits for the condition occurs regardless of the state of peripheral interrupts. its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt.

FIGURE 2-7: PIR1 REGISTER (ADDRESS 0Ch)

R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: PSPIF(1): Parallel Slave Port Read/Write Interrupt Flag bit 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred bit 6: ADIF(2): A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete bit 5: RCIF: USART Receive Interrupt Flag bit 1 = The USART receive buffer is full (cleared by reading RCREG) 0 = The USART receive buffer is empty bit 4: TXIF: USART Transmit Interrupt Flag bit 1 = The USART transmit buffer is empty (cleared by writing to TXREG) 0 = The USART transmit buffer is full bit 3: SSPIF: Synchronous Serial Port Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive bit 2: CCP1IF: CCP1 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused in this mode bit 1: TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred bit 0: TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow Note 1: PIC16C63A/73B devices do not have a Parallel Slave Port implemented. This bit location is reserved on these devices. Always maintain this bit clear. 2: PIC16C63A/65B devices do not have an A/D module. This bit location is reserved on these devices. Always maintain this bit clear. 1998 Microchip Technology Inc. DS30605A-page 19, 2.2.2.6 PIE2 REGISTER This register contains the individual enable bit for the CCP2 peripheral interrupt. FIGURE 2-8: PIE2 REGISTER (ADDRESS 8Dh) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CCP2IE R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IE: CCP2 Interrupt Enable bit 1 = Enables the CCP2 interrupt 0 = Disables the CCP2 interrupt DS30605A-page 20 1998 Microchip Technology Inc., 2.2.2.7 PIR2 REGISTER . Note: Interrupt flag bits get set when an interrupt This register contains the CCP2 interrupt flag bit. condition occurs regardless of the state of its corresponding enable bit or the global enable bit, GIE (INTCON<7>). User soft- ware should ensure the appropriate inter- rupt flag bits are clear prior to enabling an interrupt. FIGURE 2-9: PIR2 REGISTER (ADDRESS 0Dh) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 — — — — — — — CCP2IF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-1: Unimplemented: Read as '0' bit 0: CCP2IF: CCP2 Interrupt Flag bit Capture Mode 1 = A TMR1 register capture occurred (must be cleared in software) 0 = No TMR1 register capture occurred Compare Mode 1 = A TMR1 register compare match occurred (must be cleared in software) 0 = No TMR1 register compare match occurred PWM Mode Unused 1998 Microchip Technology Inc. DS30605A-page 21, 2.2.2.8 PCON REGISTER Note: If the BODEN configuration bit is set, BOR The Power Control (PCON) register contains a flag bit is ’1’ on Power-on Reset. If the BODEN to allow differentiation between a Power-on Reset configuration bit is clear, BOR is unknown (POR) to an external MCLR Reset or WDT Reset. on Power-on Reset. Those devices with brown-out detection circuitry con- The BOR status bit is a "don't care" and is tain an additional bit to differentiate a Brown-out Reset not necessarily predictable if the brown-out condition from a Power-on Reset condition. circuit is disabled (the BODEN configura- tion bit is clear). BOR must then be set by the user and checked on subsequent resets to see if it is clear, indicating a brown-out has occurred. FIGURE 2-10: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-q — — — — — — POR BOR R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-2: Unimplemented: Read as '0' bit 1: POR: Power-on Reset Status bit 1 = No Power-on Reset occurred 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) bit 0: BOR: Brown-out Reset Status bit 1 = No Brown-out Reset occurred 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) DS30605A-page 22 1998 Microchip Technology Inc., 2.3 PCL and PCLATH 2.4 Program Memory Paging The program counter (PC) specifies the address of the The CALL and GOTO instructions provide 11 bits of instruction to fetch for execution. The PC is 13 bits address to allow branching within any 2K program wide. The low byte is called the PCL register. This reg- memory page. When doing a CALL or GOTO instruction ister is readable and writable. The high byte is called the upper bit of the address is provided by the PCH register. This register contains the PC<12:8> PCLATH<3>. When doing a CALL or GOTO instruction, bits and is not directly readable or writable. All updates the user must ensure that the page select bit is pro- to the PCH register go through the PCLATH register. grammed so that the desired program memory page is addressed. If a return from a CALL instruction (or inter- 2.3.1 STACK rupt) is executed, the entire 13-bit PC is pushed onto The stack allows a combination of up to 8 program calls the stack. Therefore, manipulation of the PCLATH<3> and interrupts to occur. The stack contains the return bit is not required for the return instructions (which address from this branch in program execution. POPs the address from the stack). Mid-Range devices have an 8 level deep x 13-bit wide hardware stack. The stack space is not part of either program or data space and the stack pointer is not readable or writable. The PC is PUSHed onto the stack when a CALL instruction is executed or an interrupt causes a branch. The stack is POPed in the event of a RETURN, RETLW or a RETFIE instruction execution. PCLATH is not modified when the stack is PUSHed or POPed. After the stack has been PUSHed eight times, the ninth push overwrites the value that was stored from the first push. The tenth push overwrites the second push (and so on). 1998 Microchip Technology Inc. DS30605A-page 23, 2.5 Indirect Addressing, INDF and FSR A simple program to clear RAM locations 20h-2Fh Registers using indirect addressing is shown in Example 2-2. The INDF register is not a physical register. Address- EXAMPLE 2-2: HOW TO CLEAR RAM ing INDF actually addresses the register whose USING INDIRECT address is contained in the FSR register (FSR is a ADDRESSING pointer). This is indirect addressing. movlw 0x20 ;initialize pointer EXAMPLE 2-1: INDIRECT ADDRESSING movwf FSR ; to RAM • Register file 05 contains the value 10h NEXT clrf INDF ;clear INDF register incf FSR ;inc pointer • Register file 06 contains the value 0Ah btfss FSR,4 ;all done? • Load the value 05 into the FSR register goto NEXT ;NO, clear next • A read of the INDF register will return the value of CONTINUE 10h : ;YES, continue • Increment the value of the FSR register by one An effective 9-bit address is obtained by concatenating (FSR = 06) the 8-bit FSR register and the IRP bit (STATUS<7>), as • A read of the INDR register now will return the shown in Figure 2-11. However, IRP is not used in the value of 0Ah. PIC16C63A/65B/73B/74B. Reading INDF itself indirectly (FSR = 0) will produce 00h. Writing to the INDF register indirectly results in a no-operation (although STATUS bits may be affected). FIGURE 2-11: DIRECT/INDIRECT ADDRESSING Direct Addressing Indirect Addressing RP1:RP0 6 from opcode 0 IRP 7 FSR register 0 (2) (2) bank select location select bank select location select 00 01 10 11 00h 80h 100h 180h not used Data (3) (3) Memory(1) 7Fh FFh 17Fh 1FFh Bank 0 Bank 1 Bank 2 Bank 3 Note 1: For register file map detail see Figure 2-2. 2: Maintain RP1 and IRP as clear for upward compatibility with future products. 3: Not implemented. DS30605A-page 24 1998 Microchip Technology Inc., 3.0 I/O PORTS FIGURE 3-1: BLOCK DIAGRAM OF

RA3:RA0 AND RA5 PINS

Some pins for these I/O ports are multiplexed with an alternate function for the peripheral features on the Data device. In general, when a peripheral is enabled, that busDQpin may not be used as a general purpose I/O pin.

VDD

Additional information on I/O ports may be found in the WRPort PICmicro Mid-Range Reference Manual, (DS33023). CKQP3.1 PORTA and the TRISA Register Data LatchDQN(1) PORTA is a 6-bit wide bi-directional port. The corre- I/O pin sponding data direction register is TRISA. Setting a WR TRISA bit (=1) will make the corresponding PORTA pin TRIS VSS an input, i.e., put the corresponding output driver in a CK Q Analog hi-impedance mode. Clearing a TRISA bit (=0) will input TRIS Latch make the corresponding PORTA pin an output, i.e., put mode (73B/74B the contents of the output latch on the selected pin. only) Note: On a Power-on Reset, these pins are con- RD TRIS TTL figured as inputs and read as '0'. input buffer Reading the PORTA register reads the status of theQDpins, whereas writing to it will write to the port latch. All write operations are read-modify-write operations. Therefore, a write to a port implies that the port pins are EN read. This value is modified and then written to the port data latch. RD PORT Pin RA4 is multiplexed with the Timer0 module clock input to become the RA4/T0CKI pin. The RA4/T0CKI To A/D Converter (73B/74B only) pin is a Schmitt Trigger input and an open drain output. All other RA port pins have TTL input levels and full Note 1: I/O pins have protection diodes to VDD and CMOS output drivers. VSS. On PIC16C73B/74B devices, other PORTA pins are multiplexed with analog inputs and analog VREF input. FIGURE 3-2: BLOCK DIAGRAM OF The operation of each pin is selected by clearing/set- RA4/T0CKI PIN ting the control bits in the ADCON1 register (A/D Con- trol Register1). DatabusDQNote: On a Power-on Reset, these pins are con- WR figured as analog inputs and read as '0'. PORT CK Q I/O pin(1) The TRISA register controls the direction of the RA N pins, even when they are being used as analog inputs. Data Latch The user must ensure the bits in the TRISA register areDQVSS maintained set when using them as analog inputs. WR TRIS CK Q Schmitt Trigger

EXAMPLE 3-1: INITIALIZING PORTA TRIS Latch input

BCF STATUS, RP0 ; buffer CLRF PORTA ; Initialize PORTA by ; clearing output RD TRIS ; data latches BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used toQD; initialize data ; direction ENEN MOVWF TRISA ; Set RA<3:0> as inputs RD PORT ; RA<5:4> as outputs ; TRISA<7:6> are always ; read as '0'. TMR0 clock input Note 1: I/O pin has protection diodes to VSS only. 1998 Microchip Technology Inc. DS30605A-page 25, TABLE 3-1: PORTA FUNCTIONS Name Bit# Buffer Function RA0/AN0 bit0 TTL Input/output or analog input(1) RA1/AN1 bit1 TTL Input/output or analog input(1) RA2/AN2 bit2 TTL Input/output or analog input(1) RA3/AN3/VREF bit3 TTL Input/output or analog input(1) or VREF(1) RA4/T0CKI bit4 ST Input/output or external clock input for Timer0 Output is open drain type RA5/SS/AN4 bit5 TTL Input/output or slave select input for synchronous serial port or analog input(1) Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: On PIC16C73B/74B devices only. TABLE 3-2: SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets

BOR

05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 -0x 0000 -0u 0000 85h TRISA — — PORTA Data Direction Register -11 1111 -11 1111 9Fh ADCON1(1) — — — — — PCFG2 PCFG1 PCFG0 - -000 - -000 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by PORTA. Note 1: On PIC16C73B/74B devices only. DS30605A-page 26 1998 Microchip Technology Inc., 3.2 PORTB and the TRISB Register Four of PORTB’s pins, RB7:RB4, have an interrupt on change feature. Only pins configured as inputs can PORTB is an 8-bit wide bi-directional port. The corre- cause this interrupt to occur (i.e. any RB7:RB4 pin con- sponding data direction register is TRISB. Setting a figured as an output is excluded from the interrupt on TRISB bit (=1) will make the corresponding PORTB pin change comparison). The input pins (of RB7:RB4) are an input, i.e., put the corresponding output driver in a compared with the old value latched on the last read of hi-impedance mode. Clearing a TRISB bit (=0) will PORTB. The “mismatch” outputs of RB7:RB4 are make the corresponding PORTB pin an output, i.e., put OR’ed together to generate the RB Port Change Inter- the contents of the output latch on the selected pin. rupt with flag bit RBIF (INTCON<0>). This interrupt can wake the device from SLEEP. The

EXAMPLE 3-1: INITIALIZING PORTB user, in the interrupt service routine, can clear the inter-

BCF STATUS, RP0 ; rupt in the following manner: CLRF PORTB ; Initialize PORTB by ; clearing output a) Any read or write of PORTB. This will end the ; data latches mismatch condition. BSF STATUS, RP0 ; Select Bank 1 b) Clear flag bit RBIF. MOVLW 0xCF ; Value used to ; initialize data A mismatch condition will continue to set flag bit RBIF. ; direction Reading PORTB will end the mismatch condition, and MOVWF TRISB ; Set RB<3:0> as inputs allow flag bit RBIF to be cleared. ; RB<5:4> as outputs The interrupt on change feature is recommended for ; RB<7:6> as inputs wake-up on key depression operation and operations Each of the PORTB pins has a weak internal pull-up. A where PORTB is only used for the interrupt on change single control bit can turn on all the pull-ups. This is per- feature. Polling of PORTB is not recommended while formed by clearing bit RBPU (OPTION_REG<7>). The using the interrupt on change feature. weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are dis- FIGURE 3-4: BLOCK DIAGRAM OF abled on a Power-on Reset. RB7:RB4 PINS

FIGURE 3-3: BLOCK DIAGRAM OF VDD

RBPU(2)

RB3:RB0 PINS P weakpull-up

VDD Data Latch (2) Data busRBPU P weakDQpull-up I/O Data Latch WR Port CK pin(1)Data busDQTRIS Latch WR Port I/O D QCK pin(1) TRIS Latch WR TRIS CK TTLInputDQBuffer ST TTL Buffer WR TRIS InputCK Buffer RD TRIS LatchQDRD TRIS RD Port EN Q1QDSet RBIF RD Port EN From otherQDRB7:RB4 pins RD Port RB0/INT EN Q3 Schmitt Trigger RD Port RB7:RB6 in serial programming mode Buffer Note 1: I/O pins have diode protection to VDD and VSS. Note 1: I/O pins have diode protection to VDD and VSS. 2: To enable weak pull-ups, set the appropriate TRIS bit(s) 2: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>). and clear the RBPU bit (OPTION_REG<7>). 1998 Microchip Technology Inc. DS30605A-page 27, TABLE 3-3: PORTB FUNCTIONS Name Bit# Buffer Function RB0/INT bit0 TTL/ST(1) Input/output pin or external interrupt input. Internal software programmable weak pull-up. RB1 bit1 TTL Input/output pin. Internal software programmable weak pull-up. RB2 bit2 TTL Input/output pin. Internal software programmable weak pull-up. RB3 bit3 TTL Input/output pin. Internal software programmable weak pull-up. RB4 bit4 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB5 bit5 TTL Input/output pin (with interrupt on change). Internal software programmable weak pull-up. RB6 bit6 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming clock. RB7 bit7 TTL/ST(2) Input/output pin (with interrupt on change). Internal software programmable weak pull-up. Serial programming data. Legend: TTL = TTL input, ST = Schmitt Trigger input Note 1: This buffer is a Schmitt Trigger input when configured as the external interrupt. 2: This buffer is a Schmitt Trigger input when used in serial programming mode. TABLE 3-4: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets

BOR

06h PORTB RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx xxxx uuuu uuuu 86h TRISB PORTB Data Direction Register 1111 1111 1111 1111 81h OPTION_ RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111

REG

Legend: x = unknown, u = unchanged. Shaded cells are not used by PORTB. DS30605A-page 28 1998 Microchip Technology Inc., 3.3 PORTC and the TRISC Register FIGURE 3-5: PORTC BLOCK DIAGRAM (PERIPHERAL OUTPUT PORTC is an 8-bit wide bi-directional port. The corre- OVERRIDE) sponding data direction register is TRISC. Setting a TRISC bit (=1) will make the corresponding PORTC pin PORT/PERIPHERAL Select(2) an input, i.e., put the corresponding output driver in a hi-impedance mode. Clearing a TRISC bit (=0) will Peripheral Data Out VDD make the corresponding PORTC pin an output, i.e., put 0Data busDQthe contents of the output latch on the selected pin. WR P1

PORT

PORTC is multiplexed with several peripheral functions CK Q (Table 3-5). PORTC pins have Schmitt Trigger input Data Latch buffers. D Q I/O WR (1) When enabling peripheral functions, care should be pinTRIS CK Q taken in defining TRIS bits for each PORTC pin. Some N peripherals override the TRIS bit to make a pin an out- TRIS Latch put, while other peripherals override the TRIS bit to VSS make a pin an input. Since the TRIS bit override is in Schmitt effect while the peripheral is enabled, read-modify- RD TRIS Trigger write instructions (BSF, BCF, XORWF) with TRISC as Peripheral (3) destination should be avoided. The user should refer to OEQDthe corresponding peripheral section for the correct EN TRIS bit settings. RD PORT Peripheral input

EXAMPLE 3-1: INITIALIZING PORTC

Note 1: I/O pins have diode protection to VDD and VSS. BCF STATUS, RP0 ; Select Bank 0 2: Port/Peripheral select signal selects between port CLRF PORTC ; Initialize PORTC by data and peripheral output. ; clearing output 3: Peripheral OE (output enable) is only activated if ; data latches peripheral select is active. BSF STATUS, RP0 ; Select Bank 1 MOVLW 0xCF ; Value used to ; initialize data ; direction MOVWF TRISC ; Set RC<3:0> as inputs ; RC<5:4> as outputs ; RC<7:6> as inputs 1998 Microchip Technology Inc. DS30605A-page 29, TABLE 3-5: PORTC FUNCTIONS Name Bit# Buffer Type Function RC0/T1OSO/T1CKI bit0 ST Input/output port pin or Timer1 oscillator output/Timer1 clock input RC1/T1OSI bit1 ST Input/output port pin or Timer1 oscillator input RC2/CCP1 bit2 ST Input/output port pin or Capture1 input/Compare1 output/PWM1 output RC3/SCK/SCL bit3 ST RC3 can also be the synchronous serial clock for both SPI and I2C modes. RC4/SDI/SDA bit4 ST RC4 can also be the SPI Data In (SPI mode) or data I/O (I2C mode). RC5/SDO bit5 ST Input/output port pin or Synchronous Serial Port data output RC6 bit6 ST Input/output port pin RC7 bit7 ST Input/output port pin Legend: ST = Schmitt Trigger input TABLE 3-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets

BOR

07h PORTC RC7 RC6 RC5 RC4 RC3 RC2 RC1 RC0 xxxx xxxx uuuu uuuu 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged. DS30605A-page 30 1998 Microchip Technology Inc., 3.4 PORTD and TRISD Registers This section is applicable to the PIC16C65B/PIC16C74B devices only. PORTD is an 8-bit port with Schmitt Trigger input buff- ers. Each pin is individually configurable as an input or output. PORTD can be configured as an 8-bit wide micropro- cessor port (parallel slave port) by setting control bit PSPMODE (TRISE<4>). In this mode, the input buffers are TTL. FIGURE 3-6: PORTD BLOCK DIAGRAM (IN I/O PORT MODE) Data busDQWR (1) PORT I/O pin

CK

Data LatchDQ

WR

TRIS CK Schmitt Trigger TRIS Latch inputbuffer RD TRISQD

ENEN

RD PORT Note 1: I/O pins have protection diodes to VDD and VSS. 1998 Microchip Technology Inc. DS30605A-page 31,

TABLE 3-7: PORTD FUNCTIONS

Name Bit# Buffer Type Function RD0/PSP0 bit0 ST/TTL(1) Input/output port pin or parallel slave port bit0 RD1/PSP1 bit1 ST/TTL(1) Input/output port pin or parallel slave port bit1 RD2/PSP2 bit2 ST/TTL(1) Input/output port pin or parallel slave port bit2 RD3/PSP3 bit3 ST/TTL(1) Input/output port pin or parallel slave port bit3 RD4/PSP4 bit4 ST/TTL(1) Input/output port pin or parallel slave port bit4 RD5/PSP5 bit5 ST/TTL(1) Input/output port pin or parallel slave port bit5 RD6/PSP6 bit6 ST/TTL(1) Input/output port pin or parallel slave port bit6 RD7/PSP7 bit7 ST/TTL(1) Input/output port pin or parallel slave port bit7 Legend: ST = Schmitt Trigger input TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffer when in Parallel Slave Port Mode.

TABLE 3-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD

Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets

BOR

08h PORTD RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx xxxx uuuu uuuu 88h TRISD PORTD Data Direction Register 1111 1111 1111 1111 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTD. DS30605A-page 32 1998 Microchip Technology Inc., 3.5 PORTE and TRISE Register Note: On a Power-on Reset these pins are con- This section is applicable to the figured as analog inputs. PIC16C65B/PIC16C74B devices only. The A/D multi- FIGURE 3-7: PORTE BLOCK DIAGRAM plexed functions are available on the PIC16C74B only. (IN I/O PORT MODE) PORTE has three pins RE0/RD/AN5, RE1/WR/AN6 Data and RE2/CS/AN7, which are individually configurable busDQas inputs or outputs. These pins have Schmitt Trigger WR (1) input buffers. PORT I/O pin

CK

I/O PORTE becomes control inputs for the micropro- Data Latch cessor port when bit PSPMODE (TRISE<4>) is set. InDQthis mode, the user must make sure that the TRISE<2:0> bits are set (pins are configured as digital WRTRIS Schmitt inputs). For the PIC16C74B ensure ADCON1 is config- CK Trigger ured for digital I/O. In this mode, the input buffers are TRIS Latch input TTL. buffer Figure 3-8 shows the TRISE register, which also con- trols the parallel slave port operation. RD TRIS PORTE pins for the PIC16C74B only are multiplexedQDwith analog inputs. When selected as an analog input, these pins will read as '0's. ENEN TRISE controls the direction of the RE pins, even when RD PORT they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when Note 1: I/O pins have protection diodes to VDD and VSS. using them as analog inputs.

FIGURE 3-8: TRISE REGISTER (ADDRESS 89h)

R-0 R-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1 IBF OBF IBOV PSPMODE — TRISE2 TRISE1 TRISE0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: IBF: Input Buffer Full Status bit 1 = A word has been received and is waiting to be read by the CPU 0 = No word has been received bit 6: OBF: Output Buffer Full Status bit 1 = The output buffer still holds a previously written word 0 = The output buffer has been read bit 5: IBOV: Input Buffer Overflow Detect bit (in microprocessor mode) 1 = A write occurred when a previously input word has not been read (must be cleared in software) 0 = No overflow occurred bit 4: PSPMODE: Parallel Slave Port Mode Select bit 1 = Parallel slave port mode 0 = General purpose I/O mode bit 3: Unimplemented: Read as '0' bit 2: TRISE2: RE2 Direction Control bit 1 = Input 0 = Output bit 1: TRISE1: RE2 Direction Control bit 1 = Input 0 = Output bit 0: TRISE0: RE2 Direction Control bit 1 = Input 0 = Output 1998 Microchip Technology Inc. DS30605A-page 33, TABLE 3-9: PORTE FUNCTIONS Name Bit# Buffer Type Function RE0/RD/AN5(2) bit0 ST/TTL(1) Input/output port pin or read control input in parallel slave port mode or analog input:

RD

1 = Not a read operation 0 = Read operation. Reads PORTD register (if chip selected) RE1/WR/AN6(2) bit1 ST/TTL(1) Input/output port pin or write control input in parallel slave port mode or analog input:

WR

1 = Not a write operation 0 = Write operation. Writes PORTD register (if chip selected) RE2/CS/AN7(2) bit2 ST/TTL(1) Input/output port pin or chip select control input in parallel slave port mode or analog input:

CS

1 = Device is not selected 0 = Device is selected Legend: ST = Schmitt Trigger input TTL = TTL input Note 1: Input buffers are Schmitt Triggers when in I/O mode and TTL buffers when in Parallel Slave Port Mode. 2: A/D Converter module multiplexing is implemented on the PIC16C74B only. TABLE 3-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Value on Value on all Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets

BOR

09h PORTE — — — — — RE2 RE1 RE0 - -xxx - -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 9Fh ADCON1(1) — — — — — PCFG2 PCFG1 PCFG0 - -000 - -000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PORTE. Note 1: A/D Converter module multiplexing is implemented on the PIC16C74B only. DS30605A-page 34 1998 Microchip Technology Inc., 3.6 Parallel Slave Port FIGURE 3-9: PORTD AND PORTE BLOCK DIAGRAM (PARALLEL The Parallel Slave Port is implemented on the 40-pin SLAVE PORT) devices only (PIC16C65B and PIC16C74B). PORTD operates as an 8-bit wide Parallel Slave Port, or microprocessor port when control bit PSPMODE Data busDQ(TRISE<4>) is set. In slave mode it is asynchronously WR readable and writable by the external world through RD PORT RDx control input pin RE0/RD and WR control input pin CK pin RE1/WR. TTL It can directly interface to an 8-bit microprocessor dataQDbus. The external microprocessor can read or write the PORTD latch as an 8-bit latch. Setting bit PSPMODE RD ENEN enables port pin RE0/RD to be the RD input, RE1/WR PORT to be the WR input and RE2/CS to be the CS (chip One bit of PORTD select) input. For this functionality, the corresponding data direction bits of the TRISE register (TRISE<2:0>) Set interrupt flag must be configured as inputs (set). For the PSPIF (PIR1<7>) PIC16C74B, the A/D port configuration bits PCFG2:PCFG0 (ADCON1<2:0>) must be set, which will configure pins RE2:RE0 as digital I/O. A write to the PSP occurs when both the CS and WR Read TTL RD lines are first detected low. A read from the PSP occurs when both the CS and RD lines are first detected low. Chip Select TTL CS Write TTL WR Note: I/O pin has protection diodes to VDD and VSS. FIGURE 3-10: PARALLEL SLAVE PORT WRITE WAVEFORMS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CS WR RD

PORTD<7:0>

IBF OBF PSPIF

1998 Microchip Technology Inc. DS30605A-page 35,

FIGURE 3-11: PARALLEL SLAVE PORT READ WAVEFORMS

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4

CS WR RD

PORTD<7:0>

IBF OBF PSPIF TABLE 3-11: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT

Value on Value on all Add. Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets

BOR

08h PORTD Port data latch when written: Port pins when read xxxx xxxx uuuu uuuu 09h PORTE — — — — — RE2 RE1 RE0 - -xxx - -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 0Ch PIR1 PSPIF ADIF(1) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE ADIE(1) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 9Fh ADCON1(1) — — — — — PCFG2 PCFG1 PCFG0 - -000 - -000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Parallel Slave Port. Note 1: On PIC16C74B only. DS30605A-page 36 1998 Microchip Technology Inc., 4.0 TIMER0 MODULE Additional information on external clock requirements is available in the PICMicro Mid-Range Reference The Timer0 module timer/counter has the following fea- Manual, (DS33023). tures: • 8-bit timer/counter 4.2 Prescaler • Readable and writable An 8-bit counter is available as a prescaler for the • Internal or external clock select Timer0 module, or as a postscaler for the Watchdog • Edge select for external clock Timer, respectively (Figure 4-2). For simplicity, this • 8-bit software programmable prescaler counter is being referred to as “prescaler” throughout • Interrupt on overflow from FFh to 00h this data sheet. Note that there is only one prescaler available, which is mutually exclusively shared between Figure 4-1 is a simplified block diagram of the Timer0 the Timer0 module and the Watchdog Timer. Thus, a module. prescaler assignment for the Timer0 module means Additional information on timer modules is available in that there is no prescaler for the Watchdog Timer and the PICmicro Mid-Range Reference Manual, vice-versa. (DS33023). The prescaler is not readable or writable. 4.1 Timer0 Operation The PSA and PS2:PS0 bits (OPTION_REG<3:0>) determine the prescaler assignment and prescale ratio. Timer0 can operate as a timer or as a counter. Clearing bit PSA will assign the prescaler to the Timer0 Timer mode is selected by clearing bit T0CS module. When the prescaler is assigned to the Timer0 (OPTION_REG<5>). In timer mode, the Timer0 mod- module, prescale values of 1:2, 1:4, ..., 1:256 are ule will increment every instruction cycle (without pres- selectable. caler). If the TMR0 register is written, the increment is Setting bit PSA will assign the prescaler to the Watch- inhibited for the following two instruction cycles. The dog Timer (WDT). When the prescaler is assigned to user can work around this by writing an adjusted value the WDT, prescale values of 1:1, 1:2, ..., 1:128 are to the TMR0 register. selectable. Counter mode is selected by setting bit T0CS When assigned to the Timer0 module, all instructions (OPTION_REG<5>). In counter mode, Timer0 will writing to the TMR0 register (e.g. CLRF 1, MOVWF 1, increment either on every rising or falling edge of pin BSF 1,x...etc.) will clear the prescaler. When assigned RA4/T0CKI. The incrementing edge is determined by to WDT, a CLRWDT instruction will clear the prescaler the Timer0 Source Edge Select bit T0SE along with the WDT. (OPTION_REG<4>). Clearing bit T0SE selects the ris- ing edge. Restrictions on the external clock input are Note: Writing to TMR0 when the prescaler is discussed below. assigned to Timer0 will clear the prescaler When an external clock input is used for Timer0, it must count, but will not change the prescaler meet certain requirements. The requirements ensure assignment. the external clock can be synchronized with the internal phase clock (TOSC). There is a delay in the actual incre- menting of Timer0 after synchronization. FIGURE 4-1: TIMER0 BLOCK DIAGRAM Data bus FOSC/4 0 PSout 8 Sync with 1 Internal TMR0 clocks RA4/T0CKI Programmable 0 PSout pin Prescaler T0SE (2 cycle delay) Set interrupt PS2, PS1, PS0 PSA flag bit T0IF T0CS on overflow Note 1: T0CS, T0SE, PSA, PS2:PS0 (OPTION_REG<5:0>). 2: The prescaler is shared with Watchdog Timer (refer to Figure 4-2 for detailed block diagram). 1998 Microchip Technology Inc. DS30605A-page 37, 4.2.1 SWITCHING PRESCALER ASSIGNMENT 4.3 Timer0 Interrupt The prescaler assignment is fully under software con- The TMR0 interrupt is generated when the TMR0 reg- trol, i.e., it can be changed “on the fly” during program ister overflows from FFh to 00h. This overflow sets bit execution. T0IF (INTCON<2>). The interrupt can be masked by Note: To avoid an unintended device RESET, a clearing bit T0IE (INTCON<5>). Bit T0IF must be specific instruction sequence (shown in the cleared in software by the Timer0 module interrupt ser- PICmicro Mid-Range Reference Manual, vice routine before re-enabling this interrupt. The TMR0 (DS33023). must be executed when interrupt cannot awaken the processor from SLEEP changing the prescaler assignment from since the timer is shut off during SLEEP. Timer0 to the WDT. This sequence must be followed even if the WDT is disabled.

FIGURE 4-2: BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER

CLKOUT (=Fosc/4) Data Bus0M1RA4/T0CKIUMXSYNCpin 0 U1 2 TMR0 regX Cycles T0SE T0CS PSA Set flag bit T0IF on Overflow M 8-bit Prescaler

U

Watchdog1X8Timer 8 - to - 1MUX PS2:PS0

PSA

0 1 WDT Enable bitMUXPSA

WDT

Time-out Note: T0CS, T0SE, PSA, PS2:PS0 are (OPTION_REG<5:0>).

TABLE 4-1: REGISTERS ASSOCIATED WITH TIMER0

Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets

BOR

01h TMR0 Timer0 module’s register xxxx xxxx uuuu uuuu 0Bh, 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 1111 1111 1111 1111 85h TRISA — — PORTA Data Direction Register -11 1111 -11 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by Timer0. DS30605A-page 38 1998 Microchip Technology Inc., 5.0 TIMER1 MODULE 5.1 Timer1 Operation The Timer1 module timer/counter has the following fea- Timer1 can operate in one of these modes: tures: • As a timer • 16-bit timer/counter • As a synchronous counter (Two 8-bit registers; TMR1H and TMR1L) • As an asynchronous counter • Readable and writable (Both registers) • Internal or external clock select The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). • Interrupt on overflow from FFFFh to 0000h • Reset from CCP module trigger In timer mode, Timer1 increments every instruction cycle. In counter mode, it increments on every rising Timer1 has a control register, shown in Figure 5-1. edge of the external clock input. Timer1 can be enabled/disabled by setting/clearing control bit TMR1ON (T1CON<0>). When the Timer1 oscillator is enabled (T1OSCEN is set), the RC1/T1OSI and RC0/T1OSO/T1CKI pins Figure 5-2 is a simplified block diagram of the Timer1 become inputs. That is, the TRISC<1:0> value is module. ignored. Additional information on timer modules is available in Timer1 also has an internal “reset input”. This reset can the PICmicro Mid-Range Reference Manual, be generated by the CCP module (Section 7.0). (DS33023). FIGURE 5-1: T1CON: TIMER1 CONTROL REGISTER (ADDRESS 10h) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: T1CKPS1:T1CKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value bit 3: T1OSCEN: Timer1 Oscillator Enable Control bit 1 = Oscillator is enabled 0 = Oscillator is shut off Note: The oscillator inverter and feedback resistor are turned off to eliminate power drain bit 2: T1SYNC: Timer1 External Clock Input Synchronization Control bit TMR1CS = 1 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0 This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0. bit 1: TMR1CS: Timer1 Clock Source Select bit 1 = External clock from pin RC0/T1OSO/T1CKI (on the rising edge) 0 = Internal clock (FOSC/4) bit 0: TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 1998 Microchip Technology Inc. DS30605A-page 39,

FIGURE 5-2: TIMER1 BLOCK DIAGRAM

Set flag bit TMR1IF on Overflow Synchronized TMR1 0 clock input TMR1H TMR1L TMR1ON on/off T1SYNC T1OSC RC0/T1OSO/T1CKI 1 Prescaler Synchronize T1OSCEN FOSC/4 1, 2, 4, 8 det Enable Internal 0 RC1/T1OSI Oscillator(1) Clock 2 SLEEP input T1CKPS1:T1CKPS0 TMR1CS Note 1: When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain. DS30605A-page 40 1998 Microchip Technology Inc., 5.2 Timer1 Oscillator 5.3 Timer1 Interrupt A crystal oscillator circuit is built-in between pins T1OSI The TMR1 Register pair (TMR1H:TMR1L) increments (input) and T1OSO (amplifier output). It is enabled by from 0000h to FFFFh and rolls over to 0000h. The setting control bit T1OSCEN (T1CON<3>). The oscilla- TMR1 Interrupt, if enabled, is generated on overflow tor is a low power oscillator rated up to 200 kHz. It will which is latched in interrupt flag bit TMR1IF (PIR1<0>). continue to run during SLEEP. It is primarily intended This interrupt can be enabled/disabled by setting/clear- for a 32 kHz crystal. Table 5-1 shows the capacitor ing TMR1 interrupt enable bit TMR1IE (PIE1<0>). selection for the Timer1 oscillator. 5.4 Resetting Timer1 using a CCP Trigger The Timer1 oscillator is identical to the LP oscillator. Output The user must provide a software time delay to ensure proper oscillator start-up. If the CCP module is configured in compare mode to

TABLE 5-1: CAPACITOR SELECTION generate a “special event trigger" (CCP1M3:CCP1M0 FOR THE TIMER1 = 1011), this signal will reset Timer1 and start an A/D OSCILLATOR conversion (if the A/D module is enabled).

Note: The special event triggers from the CCP1 Osc Type Freq C1 C2 module will not set interrupt flag bit LP 32 kHz 33 pF 33 pF TMR1IF (PIR1<0>). 100 kHz 15 pF 15 pF Timer1 must be configured for either timer or synchro- 200 kHz 15 pF 15 pF nized counter mode to take advantage of this feature. If These values are for design guidance only. Timer1 is running in asynchronous counter mode, this reset operation may not work. Crystals Tested: In the event that a write to Timer1 coincides with a spe- 32.768 kHz Epson C-001R32.768K-A ± 20 PPM cial event trigger from CCP1, the write will take prece- 100 kHz Epson C-2 100.00 KC-P ± 20 PPM dence. 200 kHz STD XTL 200.000 kHz ± 20 PPM In this mode of operation, the CCPR1H:CCPR1L regis- Note 1: Higher capacitance increases the stability ters pair effectively becomes the period register for of the oscillator but also increases the start- Timer1. up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components.

TABLE 5-2: REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER

Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -00 0000 -uu uuuu Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer1 module. Note 1: These bits are reserved, maintain as '0'. 1998 Microchip Technology Inc. DS30605A-page 41, NOTES: DS30605A-page 42 1998 Microchip Technology Inc., 6.0 TIMER2 MODULE 6.1 Timer2 Operation The Timer2 module timer has the following features: Timer2 can be used as the PWM time-base for PWM • 8-bit timer (TMR2 register) mode of the CCP module. • 8-bit period register (PR2) The TMR2 register is readable and writable, and is • Readable and writable (Both registers) cleared on any device reset. • Software programmable prescaler (1:1, 1:4, 1:16) The input clock (FOSC/4) has a prescale option of 1:1, • Software programmable postscaler (1:1 to 1:16) 1:4 or 1:16, selected by control bits • Interrupt on TMR2 match of PR2 T2CKPS1:T2CKPS0 (T2CON<1:0>). • SSP module optional use of TMR2 output to gen- The match output of TMR2 goes through a 4-bit erate clock shift postscaler (which gives a 1:1 to 1:16 scaling inclusive) to generate a TMR2 interrupt (latched in flag bit Timer2 has a control register, shown in Figure 6-1. TMR2IF, (PIR1<1>)). Timer2 can be shut off by clearing control bit TMR2ON (T2CON<2>) to minimize power consumption. The prescaler and postscaler counters are cleared when any of the following occurs: Figure 6-2 is a simplified block diagram of the Timer2 module. • a write to the TMR2 register Additional information on timer modules is available in • a write to the T2CON register the PICmicro Mid-Range Reference Manual, • any device reset (Power-on Reset, MCLR reset, (DS33023). Watchdog Timer reset, or Brown-out Reset) TMR2 is not cleared when T2CON is written. FIGURE 6-1: T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h) U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7: Unimplemented: Read as '0' bit 6-3: TOUTPS3:TOUTPS0: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale bit 2: TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off bit 1-0: T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 1998 Microchip Technology Inc. DS30605A-page 43, 6.2 Timer2 Interrupt FIGURE 6-2: TIMER2 BLOCK DIAGRAM The Timer2 module has an 8-bit period register PR2. Sets flag TMR2 Timer2 increments from 00h until it matches PR2 and bit TMR2IF output (1) then resets to 00h on the next increment cycle. PR2 is a readable and writable register. The PR2 register is ini- Reset TMR2 reg Prescaler FOSC/4 tialized to FFh upon reset. 1:1, 1:4, 1:16 Postscaler 2 6.3 Output of TMR2 Comparator1:1 to 1:16 EQ The output of TMR2 (before the postscaler) is fed to the 4 PR2 reg Synchronous Serial Port module, which optionally uses it to generate shift clock. Note 1: TMR2 register output can be software selected by the SSP Module as a baud clock.

TABLE 6-1: REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER

Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 11h TMR2 Timer2 module’s register 0000 0000 0000 0000 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 92h PR2 Timer2 Period Register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the Timer2 module. Note 1: These bits are reserved, maintain as '0'. DS30605A-page 44 1998 Microchip Technology Inc., 7.0 CAPTURE/COMPARE/PWM CCP2 Module (CCP) MODULE(S) Capture/Compare/PWM Register2 (CCPR2) is com- prised of two 8-bit registers: CCPR2L (low byte) and Each CCP (Capture/Compare/PWM) module contains CCPR2H (high byte). The CCP2CON register controls a 16-bit register which can operate as a 16-bit capture the operation of CCP2. All are readable and writable. register, as a 16-bit compare register or as a PWM master/slave Duty Cycle register. Table 7-1 shows the Additional information on the CCP module is available timer resources of the CCP module modes. in the PICmicro Mid-Range Reference Manual, (DS33023). The operation of CCP1 is identical to that of CCP2, with the exception of the special trigger. Therefore, opera- TABLE 7-1: CCP MODE - TIMER tion of a CCP module in the following sections is RESOURCE described with respect to CCP1. Table 7-2 shows the interaction of the CCP modules. CCP Mode Timer Resource CCP1 Module Capture Timer1 Capture/Compare/PWM Register1 (CCPR1) is com- Compare Timer1 prised of two 8-bit registers: CCPR1L (low byte) and PWM Timer2 CCPR1H (high byte). The CCP1CON register controls the operation of CCP1. All are readable and writable. TABLE 7-2: INTERACTION OF TWO CCP MODULES CCPx Mode CCPy Mode Interaction Capture Capture Same TMR1 time-base. Capture Compare The compare should be configured for the special event trigger, which clears TMR1. Compare Compare The compare(s) should be configured for the special event trigger, which clears TMR1. PWM PWM The PWMs will have the same frequency, and update rate (TMR2 interrupt). PWM Capture None PWM Compare None FIGURE 7-1: CCP1CON REGISTER (ADDRESS 17h) / CCP2CON REGISTER (ADDRESS 1Dh) U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — CCPxX CCPxY CCPxM3 CCPxM2 CCPxM1 CCPxM0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7-6: Unimplemented: Read as '0' bit 5-4: CCPxX:CCPxY: PWM Least Significant bits Capture Mode: Unused Compare Mode: Unused PWM Mode: These bits are the two LSbs of the PWM duty cycle. The eight MSbs are found in CCPRxL. bit 3-0: CCPxM3:CCPxM0: CCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets CCPx module) 0100 = Capture mode, every falling edge 0101 = Capture mode, every rising edge 0110 = Capture mode, every 4th rising edge 0111 = Capture mode, every 16th rising edge 1000 = Compare mode, set output on match (CCPxIF bit is set) 1001 = Compare mode, clear output on match (CCPxIF bit is set) 1010 = Compare mode, generate software interrupt on match (CCPxIF bit is set, CCPx pin is unaffected) 1011 = Compare mode, trigger special event (CCPxIF bit is set; CCP1 resets TMR1; CCP2 resets TMR1 and starts an A/D conversion (if A/D module is enabled)) 11xx = PWM mode 1998 Microchip Technology Inc. DS30605A-page 45, 7.1 Capture Mode 7.1.4 CCP PRESCALER In Capture mode, CCPR1H:CCPR1L captures the There are four prescaler settings, specified by bits 16-bit value of the TMR1 register when an event occurs CCP1M3:CCP1M0. Whenever the CCP module is on pin RC2/CCP1. An event is defined as: turned off, or the CCP module is not in capture mode, • every falling edge the prescaler counter is cleared. This means that any reset will clear the prescaler counter. • every rising edge • every 4th rising edge Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will • every 16th rising edge not be cleared, therefore the first capture may be from An event is selected by control bits CCP1M3:CCP1M0 a non-zero prescaler. Example 7-1 shows the recom- (CCP1CON<3:0>). When a capture is made, the inter- mended method for switching between capture pres- rupt request flag bit CCP1IF (PIR1<2>) is set. It must calers. This example also clears the prescaler counter be cleared in software. If another capture occurs before and will not generate the “false” interrupt. the value in register CCPR1 is read, the old captured value will be lost. EXAMPLE 7-1: CHANGING BETWEEN

CAPTURE PRESCALERS

7.1.1 CCP PIN CONFIGURATION CLRF CCP1CON ;Turn CCP module off In Capture mode, the RC2/CCP1 pin should be config- MOVLW NEW_CAPT_PS ;Load the W reg with ured as an input by setting the TRISC<2> bit. ; the new prescaler Note: If the RC2/CCP1 is configured as an out- ; mode value and CCP ON put, a write to the port can cause a capture MOVWF CCP1CON ;Load CCP1CON with this ; value condition.

FIGURE 7-2: CAPTURE MODE OPERATION BLOCK DIAGRAM

Set flag bit CCP1IF Prescaler (PIR1<2>) ÷ 1, 4, 16 RC2/CCP1 CCPR1H CCPR1L Pin and Capture edge detect Enable TMR1H TMR1L CCP1CON<3:0> Q’s 7.1.2 TIMER1 MODE SELECTION Timer1 must be running in timer mode or synchronized counter mode for the CCP module to use the capture feature. In asynchronous counter mode, the capture operation may not work. 7.1.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep bit CCP1IE (PIE1<2>) clear to avoid false interrupts and should clear the flag bit CCP1IF following any such change in operating mode. DS30605A-page 46 1998 Microchip Technology Inc., 7.2 Compare Mode 7.2.1 CCP PIN CONFIGURATION In Compare mode, the 16-bit CCPR1 register value is The user must configure the RC2/CCP1 pin as an out- constantly compared against the TMR1 register pair put by clearing the TRISC<2> bit. value. When a match occurs, the RC2/CCP1 pin is: Note: Clearing the CCP1CON register will force • driven High the RC2/CCP1 compare output latch to the • driven Low default low level. This is not the data latch. • remains Unchanged 7.2.2 TIMER1 MODE SELECTION The action on the pin is based on the value of control bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the Timer1 must be running in Timer mode or Synchro- same time, interrupt flag bit CCP1IF is set. nized Counter mode if the CCP module is using the compare feature. In Asynchronous Counter mode, the

FIGURE 7-3: COMPARE MODE compare operation may not work. OPERATION BLOCK 7.2.3 SOFTWARE INTERRUPT MODE DIAGRAM

When generate software interrupt is chosen the CCP1 Special event trigger will pin is not affected. Only a CCP interrupt is generated (if reset Timer1, but not set interrupt flag bit TMR1IF (PIR1<0>), enabled). and set bit GO/DONE (ADCON0<2>), which starts an A/D conversion 7.2.4 SPECIAL EVENT TRIGGER Special Event Trigger (CCP2 only) In this mode, an internal hardware trigger is generated which may be used to initiate an action. Set flag bit CCP1IF (PIR1<2>) The special event trigger output of CCP1 resets the CCPR1H CCPR1L TMR1 register pair. This allows the CCPR1 register to effectively be a 16-bit programmable period register forQSOutput Logic Comparator Timer1.RC2/CCP1 R match Pin The special trigger output of CCP2 resets the TMR1 TRISC<2> TMR1H TMR1L Output Enable CCP1CON<3:0> register pair, and starts an A/D conversion (if the A/D Mode Select module is enabled). Note: The special event trigger from the CCP2 module will not set interrupt flag bit TMR1IF (PIR1<0>).

TABLE 7-3: REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, AND TIMER1

Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 0Eh TMR1L Holding register for the Least Significant Byte of the 16-bit TMR1 register xxxx xxxx uuuu uuuu 0Fh TMR1H Holding register for the Most Significant Byte of the 16-bit TMR1register xxxx xxxx uuuu uuuu 10h T1CON — — T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON -00 0000 -uu uuuu 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 -00 0000 -00 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by Capture and Timer1. Note 1: These bits/registers are reserved, maintain as '0'. 1998 Microchip Technology Inc. DS30605A-page 47, 7.3 PWM Mode 7.3.1 PWM PERIOD In Pulse Width Modulation (PWM) mode, the CCP1 pin The PWM period is specified by writing to the PR2 reg- produces up to a 10-bit resolution PWM output. Since ister. The PWM period can be calculated using the fol- the CCP1 pin is multiplexed with the PORTC data latch, lowing formula: the TRISC<2> bit must be cleared to make the CCP1 PWM period = [(PR2) + 1] ¥ 4 ¥ TOSC ¥ pin an output. (TMR2 prescale value) Note: Clearing the CCP1CON register will force PWM frequency is defined as 1 / [PWM period]. the CCP1 PWM output latch to the default When TMR2 is equal to PR2, the following three events low level. This is not the PORTC I/O data occur on the next increment cycle: latch. • TMR2 is cleared Figure 7-4 shows a simplified block diagram of the CCP module in PWM mode. • The CCP1 pin is set (exception: if PWM duty cycle = 0%, the CCP1 pin will not be set) For a step by step procedure on how to set up the CCP • The PWM duty cycle is latched from CCPR1L into module for PWM operation, see Section 7.3.3. CCPR1H

FIGURE 7-4: SIMPLIFIED PWM BLOCK Note: The Timer2 postscaler (see Section 6.0) is DIAGRAM not used in the determination of the PWM

frequency. The postscaler could be used to Duty cycle registers CCP1CON<5:4> have a servo update rate at a different fre- CCPR1L quency than the PWM output. 7.3.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1H (Slave) CCPR1L register and to the CCP1CON<5:4> bits. Up to 10-bit resolution is available: the CCPR1L contains ComparatorRQthe eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by RC2/CCP1 CCPR1L:CCP1CON<5:4>. The following equation is TMR2 (Note 1) S used to calculate the PWM duty cycle in time: PWM DUTY CYCLE = (CCPR1L:CCP1CON<5:4>) • Comparator TRISC<2> TOSC • (TMR2 PRESCALE VALUE) Clear Timer, CCP1 pin and latch D.C. CCPR1L and CCP1CON<5:4> can be written to at any PR2 time, but the duty cycle value is not latched into CCPR1H until after a match between PR2 and TMR2 Note 1: 8-bit timer is concatenated with 2-bit internal Q clock occurs (i.e., the period is complete). In PWM mode, or 2 bits of the prescaler to create 10-bit time-base. CCPR1H is a read-only register. A PWM output (Figure 7-5) has a time base (period) The CCPR1H register and a 2-bit internal latch are and a time that the output stays high (duty cycle). The used to double buffer the PWM duty cycle. This double frequency of the PWM is the inverse of the period (1/ buffering is essential for glitchless PWM operation. period). When the CCPR1H and 2-bit latch match TMR2 con- catenated with an internal 2-bit Q clock or 2 bits of the

FIGURE 7-5: PWM OUTPUT TMR2 prescaler, the CCP1 pin is cleared.=

Maximum PWM resolution (bits) for a given PWM fre- Period quency:

FOSC

log- FPWM = - bits log(2) Duty Cycle Note: If the PWM duty cycle value is longer than TMR2 = PR2 the PWM period, the CCP1 pin will not be cleared. TMR2 = Duty Cycle TMR2 = PR2 For an example PWM period and duty cycle calcula- tion, see the PICmicro Mid-Range Reference Manual (DS33023). DS30605A-page 48 1998 Microchip Technology Inc., uuu7.3.3 SET-UP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Set the PWM period by writing to the PR2 regis- ter. 2. Set the PWM duty cycle by writing to the CCPR1L register and CCP1CON<5:4> bits. 3. Make the CCP1 pin an output by clearing the TRISC<2> bit. 4. Set the TMR2 prescale value and enable Timer2 by writing to T2CON. 5. Configure the CCP1 module for PWM operation.

TABLE 7-4: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 20 MHz

PWM Frequency 1.22 kHz 4.88 kHz 19.53 kHz 78.12 kHz 156.3 kHz 208.3 kHz Timer Prescaler (1, 4, 16) 1641111PR2 Value 0xFF 0xFF 0xFF 0x3F 0x1F 0x17 Maximum Resolution (bits) 10 10 10875.5

TABLE 7-5: REGISTERS ASSOCIATED WITH PWM AND TIMER2

Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000 0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 000 8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 000 87h TRISC PORTC Data Direction Register 1111 1111 1111 111 11h TMR2 Timer2 module’s register 0000 0000 0000 000 92h PR2 Timer2 module’s period register 1111 1111 1111 111 12h T2CON — TOUTPS3 TOUTPS2 TOUTPS1 TOUTPS0 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 000 15h CCPR1L Capture/Compare/PWM register1 (LSB) xxxx xxxx uuuu uuu 16h CCPR1H Capture/Compare/PWM register1 (MSB) xxxx xxxx uuuu uuu 17h CCP1CON — — CCP1X CCP1Y CCP1M3 CCP1M2 CCP1M1 CCP1M0 -00 0000 -00 000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by PWM and Timer2. Note 1: These bits/registers are reserved, maintain as '0'. 1998 Microchip Technology Inc. DS30605A-page 49, NOTES: DS30605A-page 50 1998 Microchip Technology Inc., 8.0 SYNCHRONOUS SERIAL

PORT (SSP) MODULE

8.1 SSP Module Overview The Synchronous Serial Port (SSP) module is a serial interface useful for communicating with other periph- eral or microcontroller devices. These peripheral devices may be Serial EEPROMs, shift registers, dis- play drivers, A/D converters, etc. The SSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C) For more information on SSP operation (including an I2C Overview), refer to the PICmicro Mid-Range Ref- erence Manual (DS33023). Also, refer to Application Note AN578, “Use of the SSP Module in the I 2C Multi- Master Environment.” 1998 Microchip Technology Inc. DS30605A-page 51, FIGURE 8-1: SSPSTAT: SYNC SERIAL PORT STATUS REGISTER (ADDRESS 94h) R/W-0 R/W-0 R-0 R-0 R-0 R-0 R-0 R-0 SMP CKE D/APSR/W UA BF R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: SMP: SPI data input sample phase SPI Master Operation 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time SPI Slave Mode SMP must be cleared when SPI is used in slave mode bit 6: CKE: SPI Clock Edge Select CKP = 0 1 = Data transmitted on rising edge of SCK 0 = Data transmitted on falling edge of SCK CKP = 1 1 = Data transmitted on falling edge of SCK 0 = Data transmitted on rising edge of SCK bit 5: D/A: Data/Address bit (I2C mode only) 1 = Indicates that the last byte received or transmitted was data 0 = Indicates that the last byte received or transmitted was address bit 4: P: Stop bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Start bit is detected last, SSPEN is cleared) 1 = Indicates that a stop bit has been detected last (this bit is '0' on RESET) 0 = Stop bit was not detected last bit 3: S: Start bit (I2C mode only. This bit is cleared when the SSP module is disabled, or when the Stop bit is detected last, SSPEN is cleared) 1 = Indicates that a start bit has been detected last (this bit is '0' on RESET) 0 = Start bit was not detected last bit 2: R/W: Read/Write bit information (I2C mode only) This bit holds the R/W bit information following the last address match. This bit is only valid from the address match to the next start bit, stop bit, or ACK bit. 1 = Read 0 = Write bit 1: UA: Update Address (10-bit I2C mode only) 1 = Indicates that the user needs to update the address in the SSPADD register 0 = Address does not need to be updated bit 0: BF: Buffer Full Status bit Receive (SPI and I2C modes) 1 = Receive complete, SSPBUF is full 0 = Receive not complete, SSPBUF is empty Transmit (I2C mode only) 1 = Transmit in progress, SSPBUF is full 0 = Transmit complete, SSPBUF is empty DS30605A-page 52 1998 Microchip Technology Inc., FIGURE 8-2: SSPCON: SYNC SERIAL PORT CONTROL REGISTER (ADDRESS 14h) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: WCOL: Write Collision Detect bit 1 = The SSPBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision bit 6: SSPOV: Receive Overflow Indicator bit In SPI mode 1 = A new byte is received while the SSPBUF register is still holding the previous data. In case of overflow, the data in SSPSR is lost. Overflow can only occur in slave mode. The user must read the SSPBUF, even if only transmitting data, to avoid setting overflow. In master operation, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPBUF register. 0 = No overflow In I2C mode 1 = A byte is received while the SSPBUF register is still holding the previous byte. SSPOV is a "don’t care" in transmit mode. SSPOV must be cleared in software in either mode. 0 = No overflow bit 5: SSPEN: Synchronous Serial Port Enable bit In SPI mode 1 = Enables serial port and configures SCK, SDO, and SDI as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In I2C mode 1 = Enables the serial port and configures the SDA and SCL pins as serial port pins 0 = Disables serial port and configures these pins as I/O port pins In both modes, when enabled, these pins must be properly configured as input or output. bit 4: CKP: Clock Polarity Select bit In SPI mode 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level In I2C mode SCK release control 1 = Enable clock 0 = Holds clock low (clock stretch) (Used to ensure data setup time) bit 3-0: SSPM3:SSPM0: Synchronous Serial Port Mode Select bits 0000 = SPI master operation, clock = FOSC/4 0001 = SPI master operation, clock = FOSC/16 0010 = SPI master operation, clock = FOSC/64 0011 = SPI master operation, clock = TMR2 output/2 0100 = SPI slave mode, clock = SCK pin. SS pin control enabled. 0101 = SPI slave mode, clock = SCK pin. SS pin control disabled. SS can be used as I/O pin 0110 = I2C slave mode, 7-bit address 0111 = I2C slave mode, 10-bit address 1011 = I2C firmware controlled master operation (slave idle) 1110 = I2C slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = I2C slave mode, 10-bit address with start and stop bit interrupts enabled 1998 Microchip Technology Inc. DS30605A-page 53, 8.2 SPI Mode Note: When the SPI is in Slave Mode with SS pin This section contains register definitions and opera- control enabled, (SSPCON<3:0> = 0100) tional characteristics of the SPI module. the SPI module will reset if the SS pin is set Additional information on SPI operation may be found to VDD. in the PICmicro Mid-Range Reference Manual Note: If the SPI is used in Slave Mode with (DS33023). CKE = '1', then the SS pin control must be 8.2.1 OPERATION OF SSP MODULE IN SPI enabled.

MODE

FIGURE 8-3: SSP BLOCK DIAGRAM A block diagram of the SSP Module in SPI Mode is (SPI MODE) shown in Figure 8-3. Internal The SPI mode allows 8-bits of data to be synchro- data bus nously transmitted and received simultaneously. To Read Write accomplish communication, typically three pins are used: SSPBUF reg • Serial Data Out (SDO) RC5/SDO • Serial Data In (SDI) RC4/SDI/SDA • Serial Clock (SCK) RC3/SCK/SCL SSPSR reg Additionally a fourth pin may be used when in a slave RC4/SDI/SDA bit0 shift mode of operation: clock • Slave Select (SS) RA5/SS/AN4 RC5/SDO When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits in the SSPCON register (SSPCON<5:0>) SS Control and SSPSTAT<7:6>. These control bits allow the fol- Enable lowing to be specified: RA5/SS/AN4 Edge • Master Operation (SCK is the clock output) Select • Slave Mode (SCK is the clock input) • Clock Polarity (Idle state of SCK) Clock Select • Clock Edge (Output data on rising/falling edge of SCK) SSPM3:SSPM0 TMR2 output • Clock Rate (master operation only) 4 2 • Slave Select Mode (Slave mode only) Edge To enable the serial port, SSP Enable bit, SSPEN Select Prescaler TCY (SSPCON<5>) must be set. To reset or reconfigure SPI RC3/SCK/ 4, 16, 64 mode, clear bit SSPEN, re-initialize the SSPCON reg- SCL ister and then set bit SSPEN. This configures the SDI, TRISC<3> SDO, SCK and SS pins as serial port pins. For the pins to behave as the serial port function, they must have their data direction bits (in the TRISC register) appro- priately programmed. That is: • SDI must have TRISC<4> set • SDO must have TRISC<5> cleared • SCK (master operation) must have TRISC<3> cleared • SCK (Slave mode) must have TRISC<3> set • SS must have TRISA<5> set DS30605A-page 54 1998 Microchip Technology Inc.,

TABLE 8-1: REGISTERS ASSOCIATED WITH SPI OPERATION

Value on: Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 (1) ADIF (1) (1) SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 (1) ADIE (1) (1) SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 87h TRISC PORTC Data Direction Register 1111 1111 1111 1111 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 85h TRISA — — PORTA Data Direction Register -11 1111 -11 1111 94h SSPSTAT SMP CKE D/APSR/W UA BF 0000 0000 0000 0000 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used by the SSP in SPI mode. Note 1: Always maintain these bits clear. 1998 Microchip Technology Inc. DS30605A-page 55, 8.3 SSP I2C Operation The SSPCON register allows control of the I2C opera- tion. Four mode selection bits (SSPCON<3:0>) allow The SSP module in I2C mode fully implements all slave one of the following I2C modes to be selected: functions, except general call support, and provides 2 interrupts on start and stop bits in hardware to facilitate • I C Slave mode (7-bit address) firmware implementations of the master functions. The • I C Slave mode (10-bit address) SSP module implements the standard mode specifica- • I2C Slave mode (7-bit address), with start and tions as well as 7-bit and 10-bit addressing. stop bit interrupts enabled Two pins are used for data transfer. These are the RC3/ • I C Slave mode (10-bit address), with start and SCK/SCL pin, which is the clock (SCL), and the RC4/ stop bit interrupts enabled SDI/SDA pin, which is the data (SDA). The user must • I2C Firmware controlled master operation, slave configure these pins as inputs or outputs through the is idle TRISC<4:3> bits. Selection of any I2C mode, with the SSPEN bit set, The SSP module functions are enabled by setting SSP forces the SCL and SDA pins to be open drain, pro- Enable bit SSPEN (SSPCON<5>). vided these pins are programmed to inputs by setting the appropriate TRISC bits. FIGURE 8-4: SSP BLOCK DIAGRAM Additional information on SSP I2C operation may be (I2C MODE) found in the PICMicro Mid-Range Reference Manual (DS33023). Internal 8.3.1 SLAVE MODE data bus In slave mode, the SCL and SDA pins must be config- Read Write ured as inputs (TRISC<4:3> set). The SSP module will override the input state with the output data when RC3/SCK/SCL SSPBUF reg required (slave-transmitter). shift When an address is matched or the data transfer after clock an address match is received, the hardware automati- SSPSR reg cally will generate the acknowledge (ACK) pulse, and then load the SSPBUF register with the received value RC4/ MSb LSb SDI/ currently in the SSPSR register. SDA There are certain conditions that will cause the SSP Match detect Addr Match module not to give this ACK pulse. These are if either (or both): SSPADD reg a) The buffer full bit BF (SSPSTAT<0>) was set before the transfer was received. Start and Set, Reset b) The overflow bit SSPOV (SSPCON<6>) was set Stop bit detect S, P bits (SSPSTAT reg) before the transfer was received. In this case, the SSPSR register value is not loaded The SSP module has five registers for I2C operation. into the SSPBUF, but bit SSPIF (PIR1<3>) is set. These are the: Table 8-2 shows what happens when a data transfer • SSP Control Register (SSPCON) byte is received, given the status of bits BF and SSPOV. The shaded cells show the condition where • SSP Status Register (SSPSTAT) user software did not properly clear the overflow condi- • Serial Receive/Transmit Buffer (SSPBUF) tion. Flag bit BF is cleared by reading the SSPBUF reg- • SSP Shift Register (SSPSR) - Not directly acces- ister while bit SSPOV is cleared through software. sible The SCL clock input must have a minimum high and • SSP Address Register (SSPADD) low for proper operation. The high and low times of the I2C specification as well as the requirement of the SSP module is shown in timing parameter #100 and param- eter #101. DS30605A-page 56 1998 Microchip Technology Inc., 8.3.1.1 ADDRESSING ‘1111 0 A9 A8 0’, where A9 and A8 are the two MSbs of the address. The sequence of events for 10-bit Once the SSP module has been enabled, it waits for a address is as follows with steps 7- 9 for slave-transmit- START condition to occur. Following the START condi- ter: tion, the 8-bits are shifted into the SSPSR register. All incoming bits are sampled with the rising edge of the 1. Receive first (high) byte of Address (bits SSPIF, clock (SCL) line. The value of register SSPSR<7:1> is BF, and bit UA (SSPSTAT<1>) are set). compared to the value of the SSPADD register. The 2. Update the SSPADD register with second (low) address is compared on the falling edge of the eighth byte of Address (clears bit UA and releases the clock (SCL) pulse. If the addresses match, and the BF SCL line). and SSPOV bits are clear, the following events occur: 3. Read the SSPBUF register (clears bit BF) and a) The SSPSR register value is loaded into the clear flag bit SSPIF. SSPBUF register. 4. Receive second (low) byte of Address (bits b) The buffer full bit, BF is set. SSPIF, BF, and UA are set). c) An ACK pulse is generated. 5. Update the SSPADD register with the first (high) byte of Address. If match releases SCL line, this d) SSP interrupt flag bit, SSPIF (PIR1<3>) is set will clear bit UA. (interrupt is generated if enabled) - on the falling edge of the ninth SCL pulse. 6. Read the SSPBUF register (clears bit BF) and clear flag bit SSPIF. In 10-bit address mode, two address bytes need to be 7. Receive repeated START condition. received by the slave. The five Most Significant bits (MSbs) of the first address byte specify if this is a 10-bit 8. Receive first (high) byte of Address (bits SSPIF address. Bit R/W (SSPSTAT<2>) must specify a write and BF are set). so the slave device will receive the second address 9. Read the SSPBUF register (clears bit BF) and byte. For a 10-bit address the first byte would equal clear flag bit SSPIF. TABLE 8-2: DATA TRANSFER RECEIVED BYTE ACTIONS Status Bits as Data Transfer is Received Set bit SSPIF Generate ACK (SSP Interrupt occurs BF SSPOV SSPSR → SSPBUF Pulse if enabled) 0 0 Yes Yes Yes10No No Yes11No No Yes01Yes No Yes Note: Shaded cells show the conditions where the user software did not properly clear the overflow condition. 1998 Microchip Technology Inc. DS30605A-page 57, 8.3.1.2 RECEPTION When the address byte overflow condition exists, then no acknowledge (ACK) pulse is given. An overflow con- When the R/W bit of the address byte is clear and an dition is defined as either bit BF (SSPSTAT<0>) is set address match occurs, the R/W bit of the SSPSTAT or bit SSPOV (SSPCON<6>) is set. register is cleared. The received address is loaded into the SSPBUF register. An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF (PIR1<3>) must be cleared in soft- ware. The SSPSTAT register is used to determine the status of the byte.

FIGURE 8-5: I2C WAVEFORMS FOR RECEPTION (7-BIT ADDRESS)

Receiving Address R/W=0 Receiving Data ACK Receiving Data ACK SDA A7 A6 A5 A4 A3 A2 A1 ACKD7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 SCLS123456789123456789123456789PSSPIF (PIR1<3>) Cleared in software Bus Master terminates transfer BF (SSPSTAT<0>) SSPBUF register is read SSPOV (SSPCON<6>) Bit SSPOV is set because the SSPBUF register is still full. ACK is not sent. DS30605A-page 58 1998 Microchip Technology Inc., 8.3.1.3 TRANSMISSION An SSP interrupt is generated for each data transfer byte. Flag bit SSPIF must be cleared in software, and When the R/W bit of the incoming address byte is set the SSPSTAT register is used to determine the status and an address match occurs, the R/W bit of the of the byte. Flag bit SSPIF is set on the falling edge of SSPSTAT register is set. The received address is the ninth clock pulse. loaded into the SSPBUF register. The ACK pulse will be sent on the ninth bit, and pin RC3/SCK/SCL is held As a slave-transmitter, the ACK pulse from the master- low. The transmit data must be loaded into the SSP- receiver is latched on the rising edge of the ninth SCL BUF register, which also loads the SSPSR register. input pulse. If the SDA line was high (not ACK), then the Then pin RC3/SCK/SCL should be enabled by setting data transfer is complete. When the ACK is latched by bit CKP (SSPCON<4>). The master must monitor the the slave, the slave logic is reset (resets SSPSTAT reg- SCL pin prior to asserting another clock pulse. The ister) and the slave then monitors for another occur- slave devices may be holding off the master by stretch- rence of the START bit. If the SDA line was low (ACK), ing the clock. The eight data bits are shifted out on the the transmit data must be loaded into the SSPBUF reg- falling edge of the SCL input. This ensures that the SDA ister, which also loads the SSPSR register. Then pin signal is valid during the SCL high time (Figure 8-6). RC3/SCK/SCL should be enabled by setting bit CKP.

FIGURE 8-6: I2C WAVEFORMS FOR TRANSMISSION (7-BIT ADDRESS)

Receiving Address R/W = 1 Transmitting Data ACK SDA A7 A6 A5 A4 A3 A2 A1 ACK D7 D6 D5 D4 D3 D2 D1 D0

SCL

S123456789123456789PData in SCL held low sampled while CPUresponds to SSPIF SSPIF (PIR1<3>) cleared in software BF (SSPSTAT<0>) From SSP interrupt SSPBUF is written in software service routine CKP (SSPCON<4>) Set bit after writing to SSPBUF (the SSPBUF must be written-to before the CKP bit can be set) 1998 Microchip Technology Inc. DS30605A-page 59, 8.3.2 MASTER OPERATION 8.3.3 MULTI-MASTER OPERATION Master operation is supported in firmware using inter- In multi-master operation, the interrupt generation on rupt generation on the detection of the START and the detection of the START and STOP conditions STOP conditions. The STOP (P) and START (S) bits allows the determination of when the bus is free. The are cleared from a reset or when the SSP module is STOP (P) and START (S) bits are cleared from a reset disabled. The STOP (P) and START (S) bits will toggle or when the SSP module is disabled. The STOP (P) based on the START and STOP conditions. Control of and START (S) bits will toggle based on the START and the I2C bus may be taken when the P bit is set, or the STOP conditions. Control of the I2C bus may be taken bus is idle and both the S and P bits are clear. when bit P (SSPSTAT<4>) is set, or the bus is idle and In master operation, the SCL and SDA lines are manip- both the S and P bits clear. When the bus is busy, ulated in firmware by clearing the corresponding enabling the SSP Interrupt will generate the interrupt TRISC<4:3> bit(s). The output level is always low, irre- when the STOP condition occurs. spective of the value(s) in PORTC<4:3>. So when In multi-master operation, the SDA line must be moni- transmitting data, a '1' data bit must have the tored to see if the signal level is the expected output TRISC<4> bit set (input) and a '0' data bit must have level. This check only needs to be done when a high the TRISC<4> bit cleared (output). The same scenario level is output. If a high level is expected and a low level is true for the SCL line with the TRISC<3> bit. is present, the device needs to release the SDA and The following events will cause SSP Interrupt Flag bit, SCL lines (set TRISC<4:3>). There are two stages SSPIF, to be set (SSP Interrupt if enabled): where this arbitration can be lost, these are: • START condition • Address Transfer • STOP condition • Data Transfer • Data transfer byte transmitted/received When the slave logic is enabled, the slave continues to receive. If arbitration was lost during the address trans- Master operation can be done with either the slave fer stage, communication to the device may be in mode idle (SSPM3:SSPM0 = 1011) or with the slave progress. If addressed, an ACK pulse will be gener- active. When both master operation and slave modes ated. If arbitration was lost during the data transfer are used, the software needs to differentiate the stage, the device will need to re-transfer the data at a source(s) of the interrupt. later time. For more information on master operation, see AN554 2 For more information on master operation, see AN578- Software Implementation ofICBus Master. - Use of the SSP Module in the of I2C Multi-Master Environment.

TABLE 8-3: REGISTERS ASSOCIATED WITH I2C OPERATION

Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR resets 0Bh, 8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u PIR1 (1) ADIF (1) (1)0Ch SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 PIE1 (1) ADIE (1) (1)8Ch SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 13h SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register xxxx xxxx uuuu uuuu 93h SSPADD Synchronous Serial Port (I2C mode) Address Register 0000 0000 0000 0000 14h SSPCON WCOL SSPOV SSPEN CKP SSPM3 SSPM2 SSPM1 SSPM0 0000 0000 0000 0000 94h SSPSTAT SMP CKE D/APSR/W UA BF 0000 0000 0000 0000 87h TRISC PORTC Data Direction register 1111 1111 1111 1111 Legend: x = unknown, u = unchanged, - = unimplemented locations read as '0'. Shaded cells are not used by SSP module in SPI mode. Note 1: These bits are unimplemented, read as '0'. DS30605A-page 60 1998 Microchip Technology Inc., 9.0 UNIVERSAL SYNCHRONOUS The USART can be configured in the following modes:

ASYNCHRONOUS RECEIVER • Asynchronous (full duplex) TRANSMITTER (USART) • Synchronous - Master (half duplex)

The Universal Synchronous Asynchronous Receiver • Synchronous - Slave (half duplex) Transmitter (USART) module is one of the two serial Bit SPEN (RCSTA<7>), and bits TRISC<7:6>, have to I/O modules. (USART is also known as a Serial Com- be set in order to configure pins RC6/TX/CK and RC7/ munications Interface or SCI). The USART can be con- RX/DT as the Universal Synchronous Asynchronous figured as a full duplex asynchronous system that can Receiver Transmitter. communicate with peripheral devices such as CRT ter- minals and personal computers, or it can be configured as a half duplex synchronous system that can commu- nicate with peripheral devices such as A/D or D/A inte- grated circuits, Serial EEPROMs etc. FIGURE 9-1: TXSTA: TRANSMIT STATUS AND CONTROL REGISTER (ADDRESS 98h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R-1 R/W-0 CSRC TX9 TXEN SYNC — BRGH TRMT TX9D R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: CSRC: Clock Source Select bit Asynchronous mode Don’t care Synchronous mode 1 = Master mode (Clock generated internally from BRG) 0 = Slave mode (Clock from external source) bit 6: TX9: 9-bit Transmit Enable bit 1 = Selects 9-bit transmission 0 = Selects 8-bit transmission bit 5: TXEN: Transmit Enable bit 1 = Transmit enabled 0 = Transmit disabled Note: SREN/CREN overrides TXEN in SYNC mode. bit 4: SYNC: USART Mode Select bit 1 = Synchronous mode 0 = Asynchronous mode bit 3: Unimplemented: Read as '0' bit 2: BRGH: High Baud Rate Select bit Asynchronous mode 1 = High speed 0 = Low speed Synchronous mode Unused in this mode bit 1: TRMT: Transmit Shift Register Status bit 1 = TSR empty 0 = TSR full bit 0: TX9D: 9th bit of transmit data. Can be parity bit. 1998 Microchip Technology Inc. DS30605A-page 61, FIGURE 9-2: RCSTA: RECEIVE STATUS AND CONTROL REGISTER (ADDRESS 18h) R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R-0 R-x SPEN RX9 SREN CREN — FERR OERR RX9D R = Readable bit bit7 bit0 W = Writable bit U = Unimplemented bit, read as ‘0’ - n =Value at POR reset bit 7: SPEN: Serial Port Enable bit 1 = Serial port enabled (Configures RC7/RX/DT and RC6/TX/CK pins as serial port pins) 0 = Serial port disabled bit 6: RX9: 9-bit Receive Enable bit 1 = Selects 9-bit reception 0 = Selects 8-bit reception bit 5: SREN: Single Receive Enable bit Asynchronous mode Don’t care Synchronous mode - master 1 = Enables single receive 0 = Disables single receive This bit is cleared after reception is complete. Synchronous mode - slave Unused in this mode bit 4: CREN: Continuous Receive Enable bit Asynchronous mode 1 = Enables continuous receive 0 = Disables continuous receive Synchronous mode 1 = Enables continuous receive until enable bit CREN is cleared (CREN overrides SREN) 0 = Disables continuous receive bit 3: Unimplemented: Read as '0' bit 2: FERR: Framing Error bit 1 = Framing error (Can be updated by reading RCREG register and receive next valid byte) 0 = No framing error bit 1: OERR: Overrun Error bit 1 = Overrun error (Can be cleared by clearing bit CREN) 0 = No overrun error bit 0: RX9D: 9th bit of received data (Can be parity bit) DS30605A-page 62 1998 Microchip Technology Inc., 9.1 USART Baud Rate Generator (BRG) EXAMPLE 9-1: CALCULATING BAUD RATE ERROR The BRG supports both the Asynchronous and Syn- chronous modes of the USART. It is a dedicated 8-bit Desired Baud rate =Fosc / (64 (X + 1)) baud rate generator. The SPBRG register controls the 9600 =16000000 /(64 (X + 1)) period of a free running 8-bit timer. In asynchronous X =25.042 = 25 mode bit BRGH (TXSTA<2>) also controls the baud rate. In synchronous mode bit BRGH is ignored. Calculated Baud Rate =16000000 / (64 (25 + 1)) Table 9-1 shows the formula for computation of the = 9615 baud rate for different USART modes which only apply Error = (Calculated Baud Rate-Desired Baud Rate) in master mode (internal clock). Desired Baud Rate Given the desired baud rate and Fosc, the nearest inte- = (9615 - 9600) / 9600 ger value for the SPBRG register can be calculated = 0.16% using the formula in Table 9-1. From this, the error in baud rate can be determined. Example 9-1 shows the calculation of the baud rate It may be advantageous to use the high baud rate error for the following conditions: (BRGH = 1) even for slower baud clocks. This is because the FOSC/(16(X + 1)) equation can reduce the FOSC = 16 MHz baud rate error in some cases. Desired Baud Rate = 9600 BRGH = 0 Writing a new value to the SPBRG register causes the SYNC = 0 BRG timer to be reset (or cleared). This ensures the BRG does not wait for a timer overflow before output- ting the new baud rate. 9.1.1 SAMPLING The data on the RC7/RX/DT pin is sampled three times by a majority detect circuit to determine if a high or a low level is present at the RX pin. TABLE 9-1: BAUD RATE FORMULA SYNC BRGH = 0 (Low Speed) BRGH = 1 (High Speed) 0 (Asynchronous) Baud Rate = FOSC/(64(X+1)) Baud Rate= FOSC/(16(X+1)) 1 (Synchronous) Baud Rate = FOSC/(4(X+1)) NA X = value in SPBRG (0 to 255) TABLE 9-2: REGISTERS ASSOCIATED WITH BAUD RATE GENERATOR Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other resets

BOR

98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used by the BRG. 1998 Microchip Technology Inc. DS30605A-page 63,

TABLE 9-3: BAUD RATES FOR SYNCHRONOUS MODE

BAUD FOSC = 20 MHz SPBRG 16 MHz SPBRG 10 MHz SPBRG 7.15909 MHz SPBRG RATE value value value value (K) KBAUD % (decimal) KBAUD % (decimal) KBAUD % (decimal) KBAUD % (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 NA - - NA - - NA - - NA - - 2.4 NA - - NA - - NA - - NA - - 9.6 NA - - NA - - 9.766 +1.73 255 9.622 +0.23 185 19.2 19.53 +1.73 255 19.23 +0.16 207 19.23 +0.16 129 19.24 +0.23 92 76.8 76.92 +0.16 64 76.92 +0.16 51 75.76 -1.36 32 77.82 +1.32 22 96 96.15 +0.16 51 95.24 -0.79 41 96.15 +0.16 25 94.20 -1.88 18 300 294.1 -1.96 16 307.69 +2.56 12 312.5 +4.17 7 298.3 -0.57 5 500 500095000750004NA - - HIGH 5000 - 0 4000 - 0 2500 - 0 1789.8 - 0 LOW 19.53 - 255 15.625 - 255 9.766 - 255 6.991 - 255 BAUD FOSC = 5.0688 MHz 4 MHz SPBRG 3.579545 MHz SPBRG 1 MHz SPBRG 32.768 kHz SPBRG RATE value value value value (K) KBAUD % SPBRG KBAUD % (decimal) KBAUD % (decimal) KBAUD % (decimal) KBAUD % (decimal) 0.3 NA - - NA - - NA - - NA - - 0.303 +1.14 26 1.2 NA - - NA - - NA - - 1.202 +0.16 207 1.170 -2.48 6 2.4 NA - - NA - - NA - - 2.404 +0.16 103 NA - - 9.6 9.6 0 131 9.615 +0.16 103 9.622 +0.23 92 9.615 +0.16 25 NA - - 19.2 19.2 0 65 19.231 +0.16 51 19.04 -0.83 46 19.24 +0.16 12 NA - - 76.8 79.2 +3.13 15 76.923 +0.16 12 74.57 -2.90 11 83.34 +8.51 2 NA - - 96 97.48 +1.54 12 1000 +4.17 9 99.43 +3.57 8 NA - - NA - - 300 316.8 +5.60 3 NA - - 298.3 -0.57 2 NA - - NA - - 500 NA - - NA - - NA - - NA - - NA - - HIGH 1267 - 0 100 - 0 894.9 - 0 250 - 0 8.192 - 0 LOW 4.950 - 255 3.906 - 255 3.496 - 255 0.9766 - 255 0.032 - 255

TABLE 9-4: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 0)

BAUD FOSC = 20 MHz SPBRG 16 MHz SPBRG 10 MHz SPBRG 7.15909 MHz SPBRG RATE value value value value (K) % (decimal) % (decimal) % (decimal) % (decimal) 0.3 NA - - NA - - NA - - NA - - 1.2 1.221 +1.73 255 1.202 +0.16 207 1.202 +0.16 129 1.203 +0.23 92 2.4 2.404 +0.16 129 2.404 +0.16 103 2.404 +0.16 64 2.380 -0.83 46 9.6 9.469 -1.36 32 9.615 +0.16 25 9.766 +1.73 15 9.322 -2.90 11 19.2 19.53 +1.73 15 19.23 +0.16 12 19.53 +1.73 7 18.64 -2.90 5 76.8 78.13 +1.73 3 83.33 +8.51 2 78.13 +1.73 1 NA - - 96 104.2 +8.51 2 NA - - NA - - NA - - 300 312.5 +4.17 0 NA - - NA - - NA - - 500 NA - - NA - - NA - - NA - - HIGH 312.5 - 0 250 - 0 156.3 - 0 111.9 - 0 LOW 1.221 - 255 0.977 - 255 0.6104 - 255 0.437 - 255 BAUD FOSC = 5.0688 MHz 4 MHz SPBRG 3.579545 MHz SPBRG 1 MHz SPBRG 32.768 kHz SPBRG RATE value value value value (K) % SPBRG % (decimal) % (decimal) % (decimal) % (decimal) 0.3 0.31 +3.13 255 0.3005 -0.17 207 0.301 +0.23 185 0.300 +0.16 51 0.256 -14.67 1 1.2 1.2 0 65 1.202 +1.67 51 1.190 -0.83 46 1.202 +0.16 12 NA - - 2.4 2.4 0 32 2.404 +1.67 25 2.432 +1.32 22 2.232 -6.99 6 NA - - 9.6 9.9 +3.13 7 NA - - 9.322 -2.90 5 NA - - NA - - 19.2 19.8 +3.13 3 NA - - 18.64 -2.90 2 NA - - NA - - 76.8 79.2 +3.13 0 NA - - NA - - NA - - NA - - 96 NA - - NA - - NA - - NA - - NA - - 300 NA - - NA - - NA - - NA - - NA - - 500 NA - - NA - - NA - - NA - - NA - - HIGH 79.2 - 0 62.500 - 0 55.93 - 0 15.63 - 0 0.512 - 0 LOW 0.3094 - 255 3.906 - 255 0.2185 - 255 0.0610 - 255 0.0020 - 255 DS30605A-page 64 1998 Microchip Technology Inc.,

TABLE 9-5: BAUD RATES FOR ASYNCHRONOUS MODE (BRGH = 1)

BAUD FOSC = 20 MHz SPBRG 16 MHz SPBRG 10 MHz SPBRG 7.16 MHz SPBRG RATE value value value value (K) % (decimal) % (deci- % (decimal) % (deci- 9.6 9.615 +0.16 129 9.615 +0.16 103 9.615 +0.16 64 9.520 -0.83 46 19.2 19.230 +0.16 64 19.230 +0.16 51 18.939 -1.36 32 19.454 +1.32 22 38.4 37.878 -1.36 32 38.461 +0.16 25 39.062 +1.7 15 37.286 -2.90 11 57.6 56.818 -1.36 21 58.823 +2.12 16 56.818 -1.36 10 55.930 -2.90 7 115.2 113.636 -1.36 10 111.111 -3.55 8 125 +8.51 4 111.860 -2.90 3 250 2500425003NA - - NA - - 625 62501NA - - 62500NA - - 1250 125000NA - - NA - - NA - - BAUD FOSC = 5.068 SPBRG 4 MHz SPBRG 3.579 MHz SPBRG 1 MHz SPBRG 32.768 kHz SPBRG RATE value value value value value (K) % (decimal) % (decimal) % (decimal) % (decimal) % (decimal) 9.6 9.6 0 32 NA - - 9.727 +1.32 22 8.928 -6.99 6 NA - - 19.2 18.645 -2.94 16 1.202 +0.17 207 18.643 -2.90 11 20.833 +8.51 2 NA - - 38.4 39.6 +3.12 7 2.403 +0.13 103 37.286 -2.90 5 31.25 -18.61 1 NA - - 57.6 52.8 -8.33 5 9.615 +0.16 25 55.930 -2.90 3 62.5 +8.51 0 NA - - 115.2 105.6 -8.33 2 19.231 +0.16 12 111.860 -2.90 1 NA - - NA - - 250 NA - - NA - - 223.721 -10.51 0 NA - - NA - - 625 NA - - NA - - NA - - NA - - NA - - 1250 NA - - NA - - NA - - NA - - NA - - 1998 Microchip Technology Inc. DS30605A-page 65, 9.2 USART Asynchronous Mode (occurs in one TCY), the TXREG register is empty and flag bit TXIF (PIR1<4>) is set. This interrupt can be In this mode, the USART uses standard non-return-to- enabled/disabled by setting/clearing enable bit TXIE zero (NRZ) format (one start bit, eight or nine data bits ( PIE1<4>). Flag bit TXIF will be set regardless of the and one stop bit). The most common data format is state of enable bit TXIE and cannot be cleared in soft- 8-bits. An on-chip dedicated 8-bit baud rate generator ware. It will reset only when new data is loaded into the can be used to derive standard baud rate frequencies TXREG register. While flag bit TXIF indicated the status from the oscillator. The USART transmits and receives of the TXREG register, another bit TRMT (TXSTA<1>) the LSb first. The USART’s transmitter and receiver are shows the status of the TSR register. Status bit TRMT functionally independent, but use the same data format is a read only bit which is set when the TSR register is and baud rate. The baud rate generator produces a empty. No interrupt logic is tied to this bit, so the user clock, either x16 or x64 of the bit shift rate, depending has to poll this bit in order to determine if the TSR reg- on bit BRGH (TXSTA<2>). Parity is not supported by ister is empty. the hardware, but can be implemented in software (and stored as the ninth data bit). Asynchronous mode is Note 1: The TSR register is not mapped in data stopped during SLEEP. memory so it is not available to the user. Asynchronous mode is selected by clearing bit SYNC Note 2: Flag bit TXIF is set when enable bit TXEN (TXSTA<4>). is set. The USART Asynchronous module consists of the fol- Steps to follow when setting up an asynchronous trans- lowing important elements: mission: • Baud Rate Generator 1. Initialize the SPBRG register for the appropriate • Sampling Circuit baud rate. If a high speed baud rate is desired, set bit BRGH. (Section 9.1) • Asynchronous Transmitter 2. Enable the asynchronous serial port by clearing • Asynchronous Receiver bit SYNC and setting bit SPEN. 9.2.1 USART ASYNCHRONOUS TRANSMITTER 3. If interrupts are desired, then set enable bit TXIE. The USART transmitter block diagram is shown in 4. If 9-bit transmission is desired, then set transmit Figure 9-3. The heart of the transmitter is the transmit bit TX9. (serial) shift register (TSR). The shift register obtains its 5. Enable the transmission by setting bit TXEN, data from the read/write transmit buffer, TXREG. The which will also set bit TXIF. TXREG register is loaded with data in software. The TSR register is not loaded until the STOP bit has been 6. If 9-bit transmission is selected, the ninth bit transmitted from the previous load. As soon as the should be loaded in bit TX9D. STOP bit is transmitted, the TSR is loaded with new 7. Load data to the TXREG register (starts trans- data from the TXREG register (if available). Once the mission). TXREG register transfers the data to the TSR register

FIGURE 9-3: USART TRANSMIT BLOCK DIAGRAM

Data Bus TXIF TXREG register

TXIE

MSb LSb (8) • • • 0 Pin Bufferand Control TSR register RC6/TX/CK pin Interrupt TXEN Baud Rate CLK TRMT SPEN

SPBRG

Baud Rate Generator TX9 TX9D DS30605A-page 66 1998 Microchip Technology Inc.,

FIGURE 9-4: ASYNCHRONOUS TRANSMISSION

Write to TXREG Word 1 BRG output (shift clock) RC6/TX/CK (pin) Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit WORD 1 TXIF bit (Transmit buffer reg. empty flag) TRMT bit WORD 1 (Transmit shift Transmit Shift Reg reg. empty flag)

FIGURE 9-5: ASYNCHRONOUS TRANSMISSION (BACK TO BACK)

Write to TXREG Word 1 Word 2 BRG output (shift clock) RC6/TX/CK (pin) Start Bit Bit 0 Bit 1 Bit 7/8 Stop Bit Start Bit Bit 0TXIF bit (interrupt reg. flag) WORD 1 WORD 2 TRMT bit WORD 1 (Transmit shift WORD 2Transmit Shift Reg. reg. empty flag) Transmit Shift Reg. Note: This timing diagram shows two consecutive transmissions.

TABLE 9-6: REGISTERS ASSOCIATED WITH ASYNCHRONOUS TRANSMISSION

Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Transmission. Note 1: PORTD and PORTE not implemented on the PIC16C63A/73B, maintain as ’0’. 2: A/D not implemented on the PIC16C63A/65B, maintain as ’0’. 1998 Microchip Technology Inc. DS30605A-page 67, 9.2.2 USART ASYNCHRONOUS RECEIVER 3. If interrupts are desired, then set enable bit RCIE. The receiver block diagram is shown in Figure 9-6. The 4. If 9-bit reception is desired, then set bit RX9. data is received on the RC7/RX/DT pin and drives the data recovery block. The data recovery block is actually 5. Enable the reception by setting bit CREN. a high speed shifter operating at x16 times the baud 6. Flag bit RCIF will be set when reception is com- rate, whereas the main receive serial shifter operates plete and an interrupt will be generated if enable at the bit rate or at FOSC. bit RCIE was set. Steps to follow when setting up an Asynchronous 7. Read the RCSTA register to get the ninth bit (if Reception: enabled) and determine if any error occurred during reception. 1. Initialize the SPBRG register for the appropriate 8. Read the 8-bit received data by reading the baud rate. If a high speed baud rate is desired, RCREG register. set bit BRGH. (Section 9.1). 9. If any error occurred, clear the error by clearing 2. Enable the asynchronous serial port by clearing enable bit CREN. bit SYNC, and setting bit SPEN.

FIGURE 9-6: USART RECEIVE BLOCK DIAGRAM

x64 Baud Rate CLK OERR FERR

CREN SPBRG

÷ 64 MSb RSR registeror LSb Baud Rate Generator ÷ 16 Stop (8) 7 • • • 1 0 Start RC7/RX/DT Pin Buffer Data and Control Recovery RX9 SPEN RX9D RCREG register

FIFO

Interrupt RCIF Data Bus

RCIE FIGURE 9-7: ASYNCHRONOUS RECEPTION

RX (pin) Start Start Start bit bit0 bit1 bit7/8 Stop bit bit0 bit7/8 Stop bit bit7/8 Stop bit bit bit Rcv shift reg Rcv buffer reg WORD 1 WORD 2

RCREG

Read Rcv RCREG buffer reg

RCREG RCIF

(interrupt flag) OERR bit

CREN

Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word, causing the OERR (overrun) bit to be set. DS30605A-page 68 1998 Microchip Technology Inc.,

TABLE 9-7: REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION

Value on Value on Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, all other BOR Resets 0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented locations read as '0'. Shaded cells are not used for Asynchronous Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B, always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B, always maintain these bits clear. 1998 Microchip Technology Inc. DS30605A-page 69, 9.3 USART Synchronous Master Mode enabled/disabled by setting/clearing enable bit TXIE (PIE1<4>). Flag bit TXIF will be set regardless of the In Synchronous Master mode, the data is transmitted in state of enable bit TXIE and cannot be cleared in soft- a half-duplex manner, i.e. transmission and reception ware. It will reset only when new data is loaded into the do not occur at the same time. When transmitting data, TXREG register. While flag bit TXIF indicates the status the reception is inhibited and vice versa. Synchronous of the TXREG register, another bit TRMT (TXSTA<1>) mode is entered by setting bit SYNC (TXSTA<4>). In shows the status of the TSR register. TRMT is a read addition, enable bit SPEN (RCSTA<7>) is set in order only bit which is set when the TSR is empty. No inter- to configure the RC6/TX/CK and RC7/RX/DT I/O pins rupt logic is tied to this bit, so the user has to poll this to CK (clock) and DT (data) lines respectively. The bit in order to determine if the TSR register is empty. Master mode indicates that the processor transmits the The TSR is not mapped in data memory so it is not master clock on the CK line. The Master mode is available to the user. entered by setting bit CSRC (TXSTA<7>). Steps to follow when setting up a Synchronous Master 9.3.1 USART SYNCHRONOUS MASTER Transmission: TRANSMISSION 1. Initialize the SPBRG register for the appropriate baud rate (Section 9.1). The USART transmitter block diagram is shown in Figure 9-3. The heart of the transmitter is the transmit 2. Enable the synchronous master serial port by (serial) shift register (TSR). The shift register obtains its setting bits SYNC, SPEN, and CSRC. data from the read/write transmit buffer register 3. If interrupts are desired, then set enable bit TXREG. The TXREG register is loaded with data in TXIE. software. The TSR register is not loaded until the last 4. If 9-bit transmission is desired, then set bit TX9. bit has been transmitted from the previous load. As 5. Enable the transmission by setting bit TXEN. soon as the last bit is transmitted, the TSR is loaded 6. If 9-bit transmission is selected, the ninth bit with new data from the TXREG (if available). Once the should be loaded in bit TX9D. TXREG register transfers the data to the TSR register (occurs in one Tcycle), the TXREG is empty and inter- 7. Start transmission by loading data to the rupt bit TXIF (PIR1<4>) is set. The interrupt can be TXREG register.

TABLE 9-8: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER TRANSMISSION

Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other Resets

BOR

0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented, read as '0'. Shaded cells are not used for Synchronous Master Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B, always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B, always maintain these bits clear. DS30605A-page 70 1998 Microchip Technology Inc.,

FIGURE 9-8: SYNCHRONOUS TRANSMISSION

Q1Q2 Q3Q4 Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2 Q3Q4 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3Q4 Q1Q2 Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4Q1 Q2Q3 Q4 RC7/RX/DT pin Bit 0 Bit 1 Bit 2 Bit 7 Bit 0 Bit 1 Bit 7 WORD 1 WORD 2 RC6/TX/CK pin Write to TXREG reg Write word1 Write word2 TXIF bit (Interrupt flag) TRMT bTiRt MT '1' '1' TXEN bit Note: Sync master mode; SPBRG = '0'. Continuous transmission of two 8-bit words

FIGURE 9-9: SYNCHRONOUS TRANSMISSION (THROUGH TXEN)

RC7/RX/DT pin bit0 bit1 bit2 bit6 bit7 RC6/TX/CK pin Write to TXREG reg TXIF bit TRMT bit TXEN bit 1998 Microchip Technology Inc. DS30605A-page 71, 9.3.2 USART SYNCHRONOUS MASTER 3. Ensure bits CREN and SREN are clear. RECEPTION 4. If interrupts are desired, then set enable bit RCIE. Once synchronous mode is selected, reception is enabled by setting either enable bit SREN (RCSTA<5>) 5. If 9-bit reception is desired, then set bit RX9. or enable bit CREN (RCSTA<4>). Data is sampled on 6. If a single reception is required, set bit SREN. the RC7/RX/DT pin on the falling edge of the clock. If For continuous reception, set bit CREN. enable bit SREN is set, then only a single word is 7. Interrupt flag bit RCIF will be set when reception received. If enable bit CREN is set, the reception is is complete and an interrupt will be generated if continuous until CREN is cleared. If both bits are set, enable bit RCIE was set. then CREN takes precedence. 8. Read the RCSTA register to get the ninth bit (if Steps to follow when setting up a Synchronous Master enabled) and determine if any error occurred Reception: during reception. 1. Initialize the SPBRG register for the appropriate 9. Read the 8-bit received data by reading the baud rate. (Section 9.1) RCREG register. 2. Enable the synchronous master serial port by 10. If any error occurred, clear the error by clearing setting bits SYNC, SPEN, and CSRC. bit CREN.

TABLE 9-9: REGISTERS ASSOCIATED WITH SYNCHRONOUS MASTER RECEPTION

Value on: Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other Resets

BOR

0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Master Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B. Always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B. Allways maintain these bits clear.

FIGURE 9-10: SYNCHRONOUS RECEPTION (MASTER MODE, SREN)

Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 RC7/RX/DT pin bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 RC6/TX/CK pin Write to bit SREN SREN bit CREN bit '0' '0' RCIF bit (interrupt) Read

RXREG

Note: Timing diagram demonstrates SYNC master mode with bit SREN = '1' and bit BRGH = '0'. DS30605A-page 72 1998 Microchip Technology Inc., 9.4 USART Synchronous Slave Mode 9.4.2 USART SYNCHRONOUS SLAVE

RECEPTION

Synchronous slave mode differs from the Master mode in the fact that the shift clock is supplied externally at The operation of the synchronous master and slave the RC6/TX/CK pin (instead of being supplied internally modes is identical except in the case of the SLEEP in master mode). This allows the device to transfer or mode and bit SREN, which is a "don't care" in slave receive data while in SLEEP mode. Slave mode is mode. entered by clearing bit CSRC (TXSTA<7>). If receive is enabled by setting bit CREN prior to the 9.4.1 USART SYNCHRONOUS SLAVE SLEEP instruction, then a word may be received during TRANSMIT SLEEP. On completely receiving the word, the RSR register will transfer the data to the RCREG register The operation of the synchronous master and slave and if enable bit RCIE bit is set, the interrupt generated modes are identical, except in the case of the SLEEP will wake the chip from SLEEP. If the global interrupt is mode. enabled, the program will branch to the interrupt vector (0004h). If two words are written to the TXREG and then the SLEEP instruction is executed, the following will occur: Steps to follow when setting up a Synchronous Slave Reception: a) The first word will immediately transfer to the TSR register and transmit. 1. Enable the synchronous master serial port by b) The second word will remain in TXREG register. setting bits SYNC and SPEN and clearing bit CSRC. c) Flag bit TXIF will not be set. 2. If interrupts are desired, then set enable bit d) When the first word has been shifted out of TSR, RCIE. the TXREG register will transfer the second word to the TSR and flag bit TXIF will now be 3. If 9-bit reception is desired, then set bit RX9. set. 4. To enable reception, set enable bit CREN. e) If enable bit TXIE is set, the interrupt will wake 5. Flag bit RCIF will be set when reception is com- the chip from SLEEP. If the global interrupt is plete. An interrupt will be generated if enable bit enabled, the program will branch to the interrupt RCIE was set. vector (0004h). 6. Read the RCSTA register to get the ninth bit (if Steps to follow when setting up a Synchronous Slave enabled) and determine if any error occurred Transmission: during reception. 7. Read the 8-bit received data by reading the 1. Enable the synchronous slave serial port by set- RCREG register. ting bits SYNC and SPEN and clearing bit CSRC. 8. If any error occurred, clear the error by clearing bit CREN. 2. Clear bits CREN and SREN. 3. If interrupts are desired, then set enable bit TXIE. 4. If 9-bit transmission is desired, then set bit TX9. 5. Enable the transmission by setting enable bit TXEN. 6. If 9-bit transmission is selected, the ninth bit should be loaded in bit TX9D. 7. Start transmission by loading data to the TXREG register. 1998 Microchip Technology Inc. DS30605A-page 73,

TABLE 9-10: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION

Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other Resets

BOR

0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 19h TXREG USART Transmit Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Transmission. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B. Always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B. Always maintain these bits clear.

TABLE 9-11: REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE RECEPTION

Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other Resets

BOR

0Ch PIR1 PSPIF(1) ADIF(2) RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 18h RCSTA SPEN RX9 SREN CREN — FERR OERR RX9D 0000 -00x 0000 -00x 1Ah RCREG USART Receive Register 0000 0000 0000 0000 8Ch PIE1 PSPIE(1) ADIE(2) RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 98h TXSTA CSRC TX9 TXEN SYNC — BRGH TRMT TX9D 0000 -010 0000 -010 99h SPBRG Baud Rate Generator Register 0000 0000 0000 0000 Legend: x = unknown, - = unimplemented read as '0'. Shaded cells are not used for Synchronous Slave Reception. Note 1: Bits PSPIE and PSPIF are reserved on the PIC16C63A/73B. Always maintain these bits clear. 2: Bits ADIE and ADIF are reserved on the PIC16C63A/65B. Always maintain these bits clear. DS30605A-page 74 1998 Microchip Technology Inc., 10.0 ANALOG-TO-DIGITAL Additional information on the A/D module is available in

CONVERTER (A/D) MODULE the PICmicro Mid-Range Reference Manual,

(DS33023). This section applies to the PIC16C73B and The A/D module has three registers. These registers PIC16C74B only. The analog-to-digital (A/D) converter are: module has five inputs for the PIC16C73B, and eight for the PIC16C74B. • A/D Result Register (ADRES) The A/D allows conversion of an analog input signal to • A/D Control Register 0 (ADCON0) a corresponding 8-bit digital number (refer to Applica- • A/D Control Register 1 (ADCON1) tion Note AN546 for use of A/D Converter). The output A device reset forces all registers to their reset state. of the sample and hold is the input into the converter, This forces the A/D module to be turned off and any which generates the result via successive approxima- conversion is aborted. tion. The analog reference voltage is software select- able to either the device’s positive supply voltage (V ) The ADCON0 register, shown in Figure 10-1, controlsDD or the voltage level on the RA3/AN3/V pin. the operation of the A/D module. The ADCON1 regis-REF ter, shown in Figure 10-2, configures the functions of The A/D converter has a unique feature of being able the port pins. The port pins can be configured as ana- to operate while the device is in SLEEP mode. To oper- log inputs (RA3 can also be a voltage reference) or as ate in sleep, the A/D conversion clock must be derived digital I/O. from the A/D’s internal RC oscillator. FIGURE 10-1: ADCON0 REGISTER (ADDRESS 1Fh) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DONE — ADON R =Readable bit bit7 bit0 W = Writable bit U =Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-6: ADCS1:ADCS0: A/D Conversion Clock Select bits 00 = FOSC/2 01 = FOSC/8 10 = FOSC/32 11 = FRC (clock derived from an internal RC oscillator) bit 5-3: CHS2:CHS0: Analog Channel Select bits 000 = channel 0, (RA0/AN0) 001 = channel 1, (RA1/AN1) 010 = channel 2, (RA2/AN2) 011 = channel 3, (RA3/AN3) 100 = channel 4, (RA5/AN4) bit 2: GO/DONE: A/D Conversion Status bit If ADON = 1 1 = A/D conversion in progress (setting this bit starts the A/D conversion) 0 = A/D conversion not in progress (This bit is automatically cleared by hardware when the A/D conversion is complete) bit 1: Unimplemented: Read as '0' bit 0: ADON: A/D On bit 1 = A/D converter module is operating 0 = A/D converter module is shutoff and consumes no operating current 1998 Microchip Technology Inc. DS30605A-page 75, FIGURE 10-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 — — — — — PCFG2 PCFG1 PCFG0 R =Readable bit bit7 bit0 W = Writable bit U =Unimplemented bit, read as ‘0’ - n = Value at POR reset bit 7-3: Unimplemented: Read as '0' bit 2-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 RA0 RA1 RA2 RA5 RA3 VREF 000AAAAAVDD 001AAAAVREF RA3 010AAAAAVDD 011AAAAVREF RA3 100AADDAVDD 101AADDVREF RA3 11xDDDDDVDD A = Analog input D = Digital I/O DS30605A-page 76 1998 Microchip Technology Inc., The ADRES register contains the result of the A/D con- 2. Configure A/D interrupt (if desired): version. When the A/D conversion is complete, the • Clear ADIF bit result is loaded into the ADRES register, the GO/DONE • Set ADIE bit bit (ADCON0<2>) is cleared, and A/D interrupt flag bit ADIF is set. The block diagram of the A/D module is • Set GIE bit shown in Figure 10-3. 3. Wait the required acquisition time. The value that is in the ADRES register is not modified 4. Start conversion: for a Power-on Reset. The ADRES register will contain • Set GO/DONE bit (ADCON0) unknown data after a Power-on Reset. 5. Wait for A/D conversion to complete, by either: After the A/D module has been configured as desired, • Polling for the GO/DONE bit to be cleared the selected channel must be acquired before the con- OR version is started. The analog input channels must • Waiting for the A/D interrupt have their corresponding TRIS bits selected as an input. To determine acquisition time, see Section 10.1. 6. Read A/D Result register (ADRES), clear bit After this acquisition time has elapsed the A/D conver- ADIF if required. sion can be started. The following steps should be fol- 7. For next conversion, go to step 1 or step 2 as lowed for doing an A/D conversion: required. The A/D conversion time per bit is defined as TAD. A minimum wait of 2TAD is 1. Configure the A/D module: required before next acquisition starts. • Configure analog pins / voltage reference / and digital I/O (ADCON1) • Select A/D input channel (ADCON0) • Select A/D conversion clock (ADCON0) • Turn on A/D module (ADCON0)

FIGURE 10-3: A/D BLOCK DIAGRAM

CHS2:CHS0 RE2/AN7(1) RE1/AN6(1) RE0/AN5(1) RA5/AN4

VIN

(Input voltage) 011 RA3/AN3/VREF A/D RA2/AN2 Converter RA1/AN1 VDD 000 RA0/AN0 000 or VREF 010 or (Reference voltage) 001 or 011 or PCFG2:PCFG0 Note 1: Available on the PIC16C74B only. 1998 Microchip Technology Inc. DS30605A-page 77, 10.1 A/D Acquisition Requirements To calculate the minimum acquisition time, TACQ, see the PICmicro Mid-Range Reference Manual, For the A/D converter to meet its specified accuracy, (DS33023). This equation calculates the acquisition the charge holding capacitor (CHOLD) must be allowed time to within 1/2 LSb error (512 steps for the A/D). The to fully charge to the input channel voltage level. The 1/2 LSb error is the maximum error allowed for the A/D analog input model is shown in Figure 10-4. The source to meet its specified accuracy. impedance (RS) and the internal sampling switch (RSS) impedance directly affect the time required to charge Note: When the conversion is started, the hold- the capacitor CHOLD. The sampling switch (RSS) ing capacitor is disconnected from the impedance varies over the device voltage (VDD). The input pin. source impedance affects the offset voltage at the ana- log input (due to pin leakage current). The maximum recommended impedance for analog sources is 10 kΩ. After the analog input channel is selected (changed) this acquisition must be done before the conversion can be started.

FIGURE 10-4: ANALOG INPUT MODEL VDD

Sampling Switch VT = 0.6V Rs ANx RIC ≤ 1k SS RSS

CHOLD

VA CPIN I leakage = DAC capacitance 5 pF VT = 0.6V ± 500 nA = 51.2 pF

VSS

Legend CPIN = input capacitance VT = threshold voltage 6V5V I leakage = leakage current at the pin due to VDD 4V various junctions 3V RIC = interconnect resistance 2V SS = sampling switch CHOLD = sample/hold capacitance (from DAC) 5678910 11 Sampling Switch ( kΩ ) DS30605A-page 78 1998 Microchip Technology Inc., 10.2 Selecting the A/D Conversion Clock 10.3 Configuring Analog Port Pins The A/D conversion time per bit is defined as TAD. The The ADCON1, TRISA, and TRISE registers control the A/D conversion requires 9.5TAD per 8-bit conversion. operation of the A/D port pins. The port pins that are The source of the A/D conversion clock is software desired as analog inputs must have their correspond- selectable. The four possible options for TAD are: ing TRIS bits set (input). If the TRIS bit is cleared (out- • 2TOSC put), the digital output level (VOH or VOL) will be converted. • 8TOSC • 32TOSC The A/D operation is independent of the state of the CHS2:CHS0 bits and the TRIS bits. • Internal RC oscillator For correct A/D conversions, the A/D conversion clock Note 1: When reading the port register, all pins (TAD) must be selected to ensure a minimum TAD time configured as analog input channels will of 1.6 µs. read as cleared (a low level). Pins config- ured as digital inputs, will convert an ana- Table 10-1 shows the resultant TAD times derived from log input. Analog levels on a digitally the device operating frequencies and the A/D clock configured input will not affect the conver- source selected. sion accuracy. Note 2: Analog levels on any pin that is defined as a digital input (including the AN4:AN0 pins) may cause the input buffer to con- sume current that is out of the devices specification. TABLE 10-1: TAD vs. DEVICE OPERATING FREQUENCIES AD Clock Source (TAD) Device Frequency Operation ADCS1:ADCS0 20 MHz 5 MHz 1.25 MHz 333.33 kHz 2TOSC 00 100 ns(2) 400 ns(2) 1.6 µs 6 µs 8TOSC 01 400 ns(2) 1.6 µs 6.4 µs 24 µs(3) 32TOSC 10 1.6 µs 6.4 µs 25.6 µs(3) 96 µs(3) RC(5) 11 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1,4) 2 - 6 µs(1) Legend: Shaded cells are outside of recommended range. Note 1: The RC source has a typical TAD time of 4 µs. 2: These values violate the minimum required TAD time. 3: For faster conversion times, the selection of another clock source is recommended. 4: When device frequency is greater than 1 MHz, the RC A/D conversion clock source is recommended for sleep operation only. 5: For extended voltage devices (LC), please refer to Electrical Specifications section. 1998 Microchip Technology Inc. DS30605A-page 79, 10.4 A/D Conversions GO/DONE bit will be set, starting the A/D conversion, and the Timer1 counter will be reset to zero. Timer1 is Note: The GO/DONE bit should NOT be set in reset to automatically repeat the A/D acquisition period the same instruction that turns on the A/D. with minimal software overhead (moving the ADRES to the desired location). The appropriate analog input 10.5 Use of the CCP Trigger channel must be selected and the minimum acquisition done before the “special event trigger” sets the An A/D conversion can be started by the “special event GO/DONE bit (starts a conversion). trigger” of the CCP2 module. This requires that the CCP2M3:CCP2M0 bits (CCP2CON<3:0>) be pro- If the A/D module is not enabled (ADON is cleared), grammed as 1011 and that the A/D module is enabled then the “special event trigger” will be ignored by the (ADON bit is set). When the trigger occurs, the A/D module, but will still reset the Timer1 counter.

TABLE 10-2: SUMMARY OF A/D REGISTERS

Value on Value on all Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 POR, other BOR Resets 0Bh,8Bh INTCON GIE PEIE T0IE INTE RBIE T0IF INTF RBIF 0000 000x 0000 000u 0Ch PIR1 PSPIF (1) ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 0000 0000 0000 0000 8Ch PIE1 PSPIE (1) ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 0000 0000 0000 0000 0Dh PIR2 — — — — — — — CCP2IF - -0 - -0 8Dh PIE2 — — — — — — — CCP2IE - -0 - -0 1Eh ADRES A/D Result Register xxxx xxxx uuuu uuuu 1Fh ADCON0 ADCS1 ADCS0 CHS2 CHS1 CHS0 GO/DON — ADON 0000 00-0 0000 00-0

E

9Fh ADCON1 — — — — — PCFG2 PCFG1 PCFG0 - -000 - -000 05h PORTA — — RA5 RA4 RA3 RA2 RA1 RA0 -0x 0000 -0u 0000 85h TRISA — — PORTA Data Direction Register -11 1111 -11 1111 09h PORTE — — — — — RE2 RE1 RE0 - -xxx - -uuu 89h TRISE IBF OBF IBOV PSPMODE — PORTE Data Direction Bits 0000 -111 0000 -111 Legend: x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are not used for A/D conversion. Note 1: Bits PSPIE and PSPIF are reserved on the PIC6C73B. Always maintain these bits clear. DS30605A-page 80 1998 Microchip Technology Inc., 11.0 SPECIAL FEATURES OF THE other is the Power-up Timer (PWRT), which provides a

CPU fixed delay on power-up only, designed to keep the part

in reset while the power supply stabilizes. With these The PIC16C63A/65B/73B/74B devices have a host of two timers on-chip, most applications need no external features intended to maximize system reliability, mini- reset circuitry. mize cost through elimination of external components, SLEEP mode is designed to offer a very low current provide power saving operating modes and offer code power-down mode. The user can wake-up from SLEEP protection. These are: through external reset, Watchdog Timer Wake-up or • OSC Selection through an interrupt. Several oscillator options are also • Reset made available to allow the part to fit the application. - Power-on Reset (POR) The RC oscillator option saves system cost, while the - Power-up Timer (PWRT) LP crystal option saves power. A set of configuration bits are used to select various options. - Oscillator Start-up Timer (OST) - Brown-out Reset (BOR) Additional information on special features is available in the PICmicro Mid-Range Reference Manual, • Interrupts (DS33023). • Watchdog Timer (WDT) • SLEEP 11.1 Configuration Bits • Code protection The configuration bits can be programmed (read as '0') • ID locations or left unprogrammed (read as '1') to select various • In-circuit serial programming device configurations. These bits are mapped in pro- These devices have a Watchdog Timer which can be gram memory location 2007h. shut off only through configuration bits. It runs off its The user will note that address 2007h is beyond the own RC oscillator for added reliability. There are two user program memory space. In fact, it belongs to the timers that offer necessary delays on power-up. One is special test/configuration memory space (2000h - the Oscillator Start-up Timer (OST), intended to keep 3FFFh), which can be accessed only during program- the chip in reset until the crystal oscillator is stable. The ming.

FIGURE 11-1: CONFIGURATION WORD

CP1 CP0 CP1 CP0 CP1 CP0 — BODEN CP1 CP0 PWRTE WDTE FOSC1 FOSC0 Register:CONFIG bit13 bit0 Address2007h bit 13-8 CP1:CP0: Code Protection bits (2) 5-4: 11 = Code protection off 10 = Upper half of program memory code protected 01 = Upper 3/4th of program memory code protected 00 = All memory is code protected bit 7: Unimplemented: Read as '1' bit 6: BODEN: Brown-out Reset Enable bit (1) 1 = BOR enabled 0 = BOR disabled bit 3: PWRTE: Power-up Timer Enable bit (1) 1 = PWRT disabled 0 = PWRT enabled bit 2: WDTE: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled bit 1-0: FOSC1:FOSC0: Oscillator Selection bits 11 = RC oscillator 10 = HS oscillator 01 = XT oscillator 00 = LP oscillator Note 1: Enabling Brown-out Reset automatically enables Power-up Timer (PWRT) regardless of the value of bit PWRTE. Ensure the Power-up Timer is enabled anytime Brown-out Reset is enabled. 2: All of the CP1:CP0 pairs have to be given the same value to enable the code protection scheme listed. 1998 Microchip Technology Inc. DS30605A-page 81, 11.2 Oscillator Configurations TABLE 11-1: CERAMIC RESONATORS 11.2.1 OSCILLATOR TYPES Ranges Tested: The PIC16CXXX can be operated in four different oscil- Mode Freq OSC1 OSC2 lator modes. The user can program two configuration XT 455 kHz 68 - 100 pF 68 - 100 pF bits (FOSC1 and FOSC0) to select one of these four 2.0 MHz 15 - 68 pF 15 - 68 pF modes: 4.0 MHz 15 - 68 pF 15 - 68 pF • LP Low Power Crystal HS 8.0 MHz 10 - 68 pF 10 - 68 pF • XT Crystal/Resonator 16.0 MHz 10 - 22 pF 10 - 22 pF • HS High Speed Crystal/Resonator These values are for design guidance only. See • RC Resistor/Capacitor notes at bottom of page. Resonators Used: 11.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS 455 kHz Panasonic EFO-A455K04B ± 0.3% 2.0 MHz Murata Erie CSA2.00MG ± 0.5% In XT, LP or HS modes a crystal or ceramic resonator 4.0 MHz Murata Erie CSA4.00MG ± 0.5% is connected to the OSC1/CLKIN and OSC2/CLKOUT 8.0 MHz Murata Erie CSA8.00MT ± 0.5% pins to establish oscillation (Figure 11-2). The PIC16CXXX oscillator design requires the use of a par- 16.0 MHz Murata Erie CSA16.00MX ± 0.5% allel cut crystal. Use of a series cut crystal may give a All resonators used did not have built-in capacitors. frequency out of the crystal manufacturers specifica- TABLE 11-2: CAPACITOR SELECTION tions. When in XT, LP or HS modes, the device can FOR CRYSTAL OSCILLATOR have an external clock source to drive the OSC1/ CLKIN pin (Figure 11-3). Crystal Cap. Range Cap. Range Osc Type Freq C1 C2

FIGURE 11-2: CRYSTAL/CERAMIC LP 32 kHz 33 pF 33 pF RESONATOR OPERATION

200 kHz 15 pF 15 pF (HS, XT OR LP XT 200 kHz 47-68 pF 47-68 pF

OSC CONFIGURATION)

1 MHz 15 pF 15 pF C1(1) OSC1 4 MHz 15 pF 15 pF To HS 4 MHz 15 pF 15 pF internal 8 MHz 15-33 pF 15-33 pF XTAL logicRF(3) 20 MHz 15-33 pF 15-33 pF OSC2 SLEEP These values are for design guidance only. See RS(2) notes at bottom of page. C2(1) PIC16CXXX Crystals Used Note1: See Table 11-1 and Table 11-2 for recom- 32 kHz Epson C-001R32.768K-A ± 20 PPM mended values of C1 and C2. 200 kHz STD XTL 200.000KHz ± 20 PPM 2: A series resistor (RS) may be required for 1 MHz ECS ECS-10-13-1 ± 50 PPM AT strip cut crystals. 4 MHz ECS ECS-40-20-1 ± 50 PPM 3: RF varies with the crystal chosen. 8 MHz EPSON CA-301 8.000M-C ± 30 PPM 20 MHz EPSON CA-301 20.000M-C ± 30 PPM

FIGURE 11-3: EXTERNAL CLOCK INPUT OPERATION (HS, XT OR LP OSC CONFIGURATION) Note 1: Recommended values of C1 and C2 are

identical to the ranges tested (Table 11-1). 2: Higher capacitance increases the stability Clock from OSC1 of oscillator but also increases the start-up ext. system PIC16CXXX time. Open OSC2 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropri- ate values of external components. 4: Rs may be required in HS mode, as well as XT mode, to avoid overdriving crystals with low drive level specification. DS30605A-page 82 1998 Microchip Technology Inc., 11.2.3 RC OSCILLATOR 11.3 Reset For timing insensitive applications, the “RC” device The PIC16CXXX differentiates between various kinds option offers additional cost savings. The RC oscillator of reset: frequency is a function of the supply voltage, the resis- • Power-on Reset (POR) tor (REXT) and capacitor (CEXT) values and the operat- ing temperature. In addition to this, the oscillator • MCLR reset during normal operation frequency will vary from unit to unit due to normal pro- • MCLR reset during SLEEP cess parameter variation. Furthermore, the difference • WDT Reset (during normal operation) in lead frame capacitance between package types will • WDT Wake-up (during SLEEP) also affect the oscillation frequency, especially for low • Brown-out Reset (BOR) CEXT values. The user also needs to take into account variation due to tolerance of external R and C compo- Some registers are not affected in any reset condition. nents used. Figure 11-4 shows how the R/C combina- Their status is unknown on POR and unchanged in any tion is connected to the PIC16CXXX. other reset. Most other registers are reset to a “reset state” on Power-on Reset (POR), on the MCLR and FIGURE 11-4: RC OSCILLATOR MODE WDT Reset, on MCLR reset during SLEEP and Brown- out Reset (BOR). They are not affected by a WDT V Wake-up, which is viewed as the resumption of normalDD operation. The TO and PD bits are set or cleared differ- Rext ently in different reset situations as indicated in Internal Table 11-4. These bits are used in software to deter-OSC1 clock mine the nature of the reset. See Table 11-6 for a full description of reset states of all registers. Cext PIC16CXXX A simplified block diagram of the on-chip reset circuit is VSS shown in Figure 11-5. OSC2/CLKOUT Fosc/4 The PICmicros have a MCLR noise filter in the MCLR Recommended values: 3 kΩ ≤ Rext ≤ 100 kΩ reset path. The filter will detect and ignore small pulses. Cext > 20pF It should be noted that a WDT Reset does not drive MCLR pin low. 1998 Microchip Technology Inc. DS30605A-page 83,

FIGURE 11-5: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT

External Reset

MCLR SLEEP

WDT WDT Module Time-out Reset VDD rise detect V Power-on ResetDD Brown-out Reset BODEN S OST/PWRT

OST

Chip_Reset 10-bit Ripple counterRQOSC1 (1) PWRT On-chip RC OSC 10-bit Ripple counter Enable PWRT Enable OST Note 1: This is a separate oscillator from the RC oscillator of the CLKIN pin. DS30605A-page 84 1998 Microchip Technology Inc., 11.4 Power-On Reset (POR) 11.5 Power-up Timer (PWRT) A Power-on Reset pulse is generated on-chip when The Power-up Timer provides a fixed nominal time-out VDD rise is detected (in the range of 1.5V - 2.1V). To (parameter #33) on power-up only, from the POR. The take advantage of the POR, just tie the MCLR pin Power-up Timer operates on an internal RC oscillator. directly (or through a resistor) to VDD. This will eliminate The chip is kept in reset as long as the PWRT is active. external RC components usually needed to create a The PWRT’s time delay allows VDD to rise to an accept- Power-on Reset. A maximum rise time for VDD is spec- able level. A configuration bit is provided to enable/dis- ified (parameter D004). For a slow rise time, see able the PWRT. Figure 11-6. The power-up time delay will vary from chip to chip due When the device starts normal operation (exits the to VDD, temperature and process variation. See DC reset condition), device operating parameters (voltage, parameters for details. frequency, temperature,...) must be met to ensure oper- ation. If these conditions are not met, the device must 11.6 Oscillator Start-up Timer (OST) be held in reset until the operating conditions are met. Brown-out Reset may be used to meet the start-up con- The Oscillator Start-up Timer (OST) provides 1024 ditions. oscillator cycle (from OSC1 input) delay after the PWRT delay is over (parameter #32). This ensures that the crystal oscillator or resonator has started and sta- FIGURE 11-6: EXTERNAL POWER-ON bilized. RESET CIRCUIT (FOR SLOW VDD POWER-UP) The OST time-out is invoked only for XT, LP and HS modes and only on Power-on Reset or wake-up from SLEEP.

VDD

11.7 Brown-Out Reset (BOR) DRAconfiguration bit, BODEN, can disable (if clear/pro- R1 grammed) or enable (if set) the Brown-out Reset cir-

MCLR

cuitry. If VDD falls below parameter D005 for greater C PIC16CXXX than parameter #35, the brown-out situation will reset the chip. A reset may not occur if VDD falls below parameter D005 for less than parameter #35. The chip Note 1: External Power-on Reset circuit is required will remain in Brown-out Reset until VDD rises above only if VDD power-up slope is too slow. The BVDD. The Power-up Timer will then be invoked and will diode D helps discharge the capacitor keep the chip in RESET an additional time delay quickly when VDD powers down. (parameter #33). If VDD drops below BVDD while the 2: R < 40 kΩ is recommended to make sure Power-up Timer is running, the chip will go back into a that voltage drop across R does not violate Brown-out Reset and the Power-up Timer will be initial- the device’s electrical specification. ized. Once VDD rises above BVDD, the Power-up Timer will execute the additional time delay. The Power-up 3: R1 = 100Ω to 1 kΩ will limit any current Timer should always be enabled when Brown-out flowing into MCLR from external capacitor Reset is enabled. C in the event of MCLR/VPP pin break- down due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). 1998 Microchip Technology Inc. DS30605A-page 85, 11.8 Time-out Sequence 11.9 Power Control/Status Register (PCON) On power-up, the time-out sequence is as follows: First PWRT time-out is invoked after the POR time delay has The Power Control/Status Register, PCON, has up to expired. Then OST is activated. The total time-out will two bits, depending upon the device. vary based on oscillator configuration and the status of Bit0 is Brown-out Reset Status bit, BOR. If the BODEN the PWRT. For example, in RC mode with the PWRT configuration bit is set, BOR is ’1’ on Power-on Reset. disabled, there will be no time-out at all. Figure 11-7, If the BODEN configuration bit is clear, BOR is Figure 11-8, Figure 11-9 and Figure 11-10 depict time- unknown on Power-on Reset. out sequences on power-up. The BOR status bit is a "don't care" and is not neces- Since the time-outs occur from the POR pulse, if MCLR sarily predictable if the brown-out circuit is disabled (the is kept low long enough, the time-outs will expire. Then BODEN configuration bit is clear). BOR must then be bringing MCLR high will begin execution immediately set by the user and checked on subsequent resets to (Figure 11-9). This is useful for testing purposes or to see if it is clear, indicating a brown-out has occurred. synchronize more than one PIC16CXXX device operat- ing in parallel. Bit1 is POR (Power-on Reset Status bit). It is cleared on a Power-on Reset and unaffected otherwise. The Table 11-5 shows the reset conditions for some special user must set this bit following a Power-on Reset. function registers, while Table 11-6 shows the reset conditions for all the registers. TABLE 11-3: TIME-OUT IN VARIOUS SITUATIONS Power-up Wake-up from Oscillator Configuration Brown-out PWRTE = 0 PWRTE = 1 SLEEP XT, HS, LP 72 ms + 1024TOSC 1024TOSC 72 ms + 1024TOSC 1024TOSC RC 72 ms — 72 ms — TABLE 11-4: STATUS BITS AND THEIR SIGNIFICANCE POR BOR TO PD0x11Power-on Reset0x0xIllegal, TO is set on POR0xx0Illegal, PD is set on POR1011Brown-out Reset1101WDT Reset1100WDT Wake-up11uuMCLR Reset during normal operation1110MCLR Reset during SLEEP or interrupt wake-up from SLEEP TABLE 11-5: RESET CONDITION FOR SPECIAL REGISTERS Condition Program STATUS PCON Counter Register Register Power-on Reset 000h 0001 1xxx - -0x MCLR Reset during normal operation 000h 000u uuuu - -uu MCLR Reset during SLEEP 000h 0001 0uuu - -uu WDT Reset 000h 0000 1uuu - -uu WDT Wake-up PC + 1 uuu0 0uuu - -uu Brown-out Reset 000h 0001 1uuu - -u0 Interrupt wake-up from SLEEP PC + 1(1) uuu1 0uuu - -uu Legend: u = unchanged, x = unknown, - = unimplemented bit read as '0'. Note 1: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). DS30605A-page 86 1998 Microchip Technology Inc., TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS Register Applicable Devices Power-on Reset, MCLR Resets Wake-up via WDT or Brown-out Reset WDT Reset Interrupt W 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu INDF 63A 65B 73B 74B N/A N/A N/A TMR0 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu PCL 63A 65B 73B 74B 0000h 0000h PC + 1(2) STATUS 63A 65B 73B 74B 0001 1xxx 000q quuu(3) uuuq quuu(3) FSR 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu PORTA(4) 63A 65B 73B 74B -0x 0000 -0u 0000 -uu uuuu PORTB(5) 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu PORTC(5) 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu PORTD(5) 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu PORTE(5) 63A 65B 73B 74B - -xxx - -uuu - -uuu PCLATH 63A 65B 73B 74B -0 0000 -0 0000 -u uuuu INTCON 63A 65B 73B 74B 0000 000x 0000 000u uuuu uuuu(1) 63A 65B 73B 74B -00 0000 -00 0000 -uu uuuu(1) 63A 65B 73B 74B -000 0000 -000 0000 -uuu uuuu(1) PIR1 63A 65B 73B 74B 0-00 0000 0-00 0000 u-uu uuuu(1) 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu(1) PIR2 63A 65B 73B 74B - -0 - -0 - -u(1) TMR1L 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu TMR1H 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu T1CON 63A 65B 73B 74B -00 0000 -uu uuuu -uu uuuu TMR2 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu T2CON 63A 65B 73B 74B -000 0000 -000 0000 -uuu uuuu SSPBUF 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu SSPCON 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu CCPR1L 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu CCPR1H 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu CCP1CON 63A 65B 73B 74B -00 0000 -00 0000 -uu uuuu RCSTA 63A 65B 73B 74B 0000 -00x 0000 -00x uuuu -uuu TXREG 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu RCREG 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu CCPR2L 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu CCPR2H 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu CCP2CON 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 11-5 for reset value for specific condition. 4: On any device reset, these pins are configured as inputs. 5: This is the value that will be in the port output latch. 1998 Microchip Technology Inc. DS30605A-page 87, TABLE 11-6: INITIALIZATION CONDITIONS FOR ALL REGISTERS (Cont.’d) Register Applicable Devices Power-on Reset, MCLR Resets Wake-up via WDT or Brown-out Reset WDT Reset Interrupt ADRES 63A 65B 73B 74B xxxx xxxx uuuu uuuu uuuu uuuu ADCON0 63A 65B 73B 74B 0000 00-0 0000 00-0 uuuu uu-u OPTION_REG 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu TRISA 63A 65B 73B 74B -11 1111 -11 1111 -uu uuuu TRISB 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu TRISC 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu TRISD 63A 65B 73B 74B 1111 1111 1111 1111 uuuu uuuu TRISE 63A 65B 73B 74B 0000 -111 0000 -111 uuuu -uuu 63A 65B 73B 74B 0000 -000 0000 -000 uuuu -uuu 63A 65B 73B 74B -00 0000 -00 0000 -uu uuuu 63A 65B 73B 74B 0-00 0000 0-00 0000 u-uu uuuu PIE1 63A 65B 73B 74B -000 0000 -000 0000 -uuu uuuu 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu PIE2 63A 65B 73B 74B - -0 - -0 - -u PCON 63A 65B 73B 74B - -0q - -uq - -uq PR2 63A 65B 73B 74B 1111 1111 1111 1111 1111 1111 SSPADD 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu SSPSTAT 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu TXSTA 63A 65B 73B 74B 0000 -010 0000 -010 uuuu -uuu SPBRG 63A 65B 73B 74B 0000 0000 0000 0000 uuuu uuuu ADCON1 63A 65B 73B 74B - -000 - -000 - -uuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as '0', q = value depends on condition Note 1: One or more bits in INTCON, PIR1 and/or PIR2 will be affected (to cause wake-up). 2: When the wake-up is due to an interrupt and the GIE bit is set, the PC is loaded with the interrupt vector (0004h). 3: See Table 11-5 for reset value for specific condition. 4: On any device reset, these pins are configured as inputs. 5: This is the value that will be in the port output latch. FIGURE 11-7: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD)

VDD MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET DS30605A-page 88 1998 Microchip Technology Inc., FIGURE 11-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1

VDD MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 11-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2

VDD MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT TOST OST TIME-OUT INTERNAL RESET FIGURE 11-10: SLOW RISE TIME (MCLR TIED TO VDD) 5V VDD 0V 1V

MCLR

INTERNAL POR

TPWRT

PWRT TIME-OUT

TOST

OST TIME-OUT INTERNAL RESET 1998 Microchip Technology Inc. DS30605A-page 89, 11.10 Interrupts The RB0/INT pin interrupt, the RB port change inter- rupt and the TMR0 overflow interrupt flags are con- The PIC16CXX family has up to 12 sources of interrupt. tained in the INTCON register. The interrupt control register (INTCON) records individ- ual interrupt requests in flag bits. It also has individual The peripheral interrupt flags are contained in the spe- and global interrupt enable bits. cial function registers PIR1 and PIR2. The correspond- ing interrupt enable bits are contained in special Note: Individual interrupt flag bits are set regard- function registers PIE1 and PIE2, and the peripheral less of the status of their corresponding interrupt enable bit is contained in special function reg- mask bit or the GIE bit. ister INTCON. A global interrupt enable bit, GIE (INTCON<7>) When an interrupt is responded to, the GIE bit is enables (if set) all un-masked interrupts or disables (if cleared to disable any further interrupt, the return cleared) all interrupts. When bit GIE is enabled, and an address is pushed onto the stack and the PC is loaded interrupt’s flag bit and mask bit are set, the interrupt will with 0004h. Once in the interrupt service routine, the vector immediately. Individual interrupts can be dis- source(s) of the interrupt can be determined by polling abled through their corresponding enable bits in vari- the interrupt flag bits. The interrupt flag bit(s) must be ous registers. Individual interrupt bits are set cleared in software before re-enabling interrupts to regardless of the status of the GIE bit. The GIE bit is avoid recursive interrupts. cleared on reset. For external interrupt events, such as the INT pin or The “return from interrupt” instruction, RETFIE, exits PORTB change interrupt, the interrupt latency will be the interrupt routine as well as sets the GIE bit, which three or four instruction cycles. The exact latency re-enables interrupts. depends when the interrupt event occurs. The latency is the same for one or two cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding mask bit or the GIE bit.

FIGURE 11-11: INTERRUPT LOGIC PSPIF PSPIE

ADIF Wake-up (If in SLEEP mode)T0IF ADIE T0IE RCIF INTF RCIE INTE Interrupt to CPU TXIF RBIF TXIE RBIE

SSPIF SSPIE PEIE

CCP1IF CCP1IE GIE TMR2IF TMR2IE TMR1IF TMR1IE CCP2IF CCP2IE The following table shows which devices have which interrupts. Device T0IF INTF RBIF PSPIF ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF CCP2IF PIC16C63A Yes Yes Yes - - Yes Yes Yes Yes Yes Yes Yes PIC16C65B Yes Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes PIC16C73B Yes Yes Yes - Yes Yes Yes Yes Yes Yes Yes Yes PIC16C74B Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes DS30605A-page 90 1998 Microchip Technology Inc., 11.10.1 INT INTERRUPT 11.11 Context Saving During Interrupts External interrupt on RB0/INT pin is edge triggered; During an interrupt, only the return PC value is saved either rising if bit INTEDG (OPTION_REG<6>) is set, on the stack. Typically, users may wish to save key reg- or falling, if the INTEDG bit is clear. When a valid edge isters during an interrupt, i.e., W register and STATUS appears on the RB0/INT pin, flag bit INTF register. This will have to be implemented in software. (INTCON<1>) is set. This interrupt can be disabled by Example 11-1 stores and restores the W and STATUS clearing enable bit INTE (INTCON<4>). Flag bit INTF registers. The register, W_TEMP, must be defined in must be cleared in software in the interrupt service rou- each bank and must be defined at the same offset from tine before re-enabling this interrupt. The INT interrupt the bank base address (i.e., if W_TEMP is defined at can wake-up the processor from SLEEP, if bit INTE was 0x20 in bank 0. It must also be defined at 0xA0 in bank set prior to going into SLEEP. The status of global inter- 1). rupt enable bit GIE decides whether or not the proces- sor branches to the interrupt vector following wake-up. The example: See Section 11.13 for details on SLEEP mode. a) Stores the W register. 11.10.2 TMR0 INTERRUPT b) Stores the STATUS register in bank 0. c) Stores the PCLATH register. An overflow (FFh → 00h) in the TMR0 register will set d) Executes the interrupt service routine code flag bit T0IF (INTCON<2>). The interrupt can be (User-generated). enabled/disabled by setting/clearing enable bit T0IE e) Restores the STATUS register (and bank select (INTCON<5>). (Section 4.0) bit). 11.10.3 PORTB INTCON CHANGE f) Restores the W and PCLATH registers. An input change on PORTB<7:4> sets flag bit RBIF (INTCON<0>). The interrupt can be enabled/disabled by setting/clearing enable bit RBIE (INTCON<4>). (Section 3.2)

EXAMPLE 11-1: SAVING STATUS, W, AND PCLATH REGISTERS IN RAM

MOVWF W_TEMP ;Copy W to TEMP register, could be bank one or zero SWAPF STATUS,W ;Swap status to be saved into W CLRF STATUS ;bank 0, regardless of current bank, Clears IRP,RP1,RP0 MOVWF STATUS_TEMP ;Save status to bank zero STATUS_TEMP register MOVF PCLATH, W ;Only required if using pages 1, 2 and/or 3 MOVWF PCLATH_TEMP ;Save PCLATH into W CLRF PCLATH ;Page zero, regardless of current page BCF STATUS, IRP ;Return to Bank 0 MOVF FSR, W ;Copy FSR to W MOVWF FSR_TEMP ;Copy FSR from W to FSR_TEMP : :(ISR) : MOVF PCLATH_TEMP, W ;Restore PCLATH MOVWF PCLATH ;Move W into PCLATH SWAPF STATUS_TEMP,W ;Swap STATUS_TEMP register into W ;(sets bank to original state) MOVWF STATUS ;Move W into STATUS register SWAPF W_TEMP,F ;Swap W_TEMP SWAPF W_TEMP,W ;Swap W_TEMP into W 1998 Microchip Technology Inc. DS30605A-page 91, 11.12 Watchdog Timer (WDT) WDT time-out period values may be found in the Elec- trical Specifications section under parameter #31. Val- The Watchdog Timer is a free running on-chip RC oscil- ues for the WDT prescaler (actually a postscaler, but lator, which does not require any external components. shared with the Timer0 prescaler) may be assigned This RC oscillator is separate from the RC oscillator of using the OPTION_REG register. the OSC1/CLKIN pin. That means that the WDT will run, even if the clock on the OSC1/CLKIN and OSC2/ Note: The CLRWDT and SLEEP instructions clear CLKOUT pins of the device has been stopped, for the WDT and the postscaler if assigned to example, by execution of a SLEEP instruction. the WDT, and prevent it from timing out and generating a device RESET condition. During normal operation, a WDT time-out generates a device RESET (Watchdog Timer Reset). If the device is . in SLEEP mode, a WDT time-out causes the device to Note: When a CLRWDT instruction is executed wake-up and continue with normal operation (Watch- and the prescaler is assigned to the WDT, dog Timer Wake-up). The TO bit in the STATUS register the prescaler count will be cleared, but the will be cleared upon a Watchdog Timer time-out. prescaler assignment is not changed. The WDT can be permanently disabled by clearing configuration bit WDTE (Section 11.1). FIGURE 11-12: WATCHDOG TIMER BLOCK DIAGRAM From TMR0 Clock Source (Figure 4-2) M Postscaler1 WDT TimerUX88- to - 1 MUX PS2:PS0

PSA WDT

Enable Bit To TMR0 (Figure 4-2) 0 1 MUX PSA Note: PSA and PS2:PS0 are bits in the OPTION_REG register. WDTTime-out FIGURE 11-13: SUMMARY OF WATCHDOG TIMER REGISTERS Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 2007h Config. bits (1) BODEN(1) CP1 CP0 PWRTE(1) WDTE FOSC1 FOSC0 81h OPTION_REG RBPU INTEDG T0CS T0SE PSA PS2 PS1 PS0 Legend: Shaded cells are not used by the Watchdog Timer. Note 1: See Figure 11-1 for operation of these bits. DS30605A-page 92 1998 Microchip Technology Inc., 11.13 Power-down Mode (SLEEP) Other peripherals cannot generate interrupts since dur- ing SLEEP, no on-chip clocks are present. Power-down mode is entered by executing a SLEEP instruction. When the SLEEP instruction is being executed, the next instruction (PC + 1) is pre-fetched. For the device to If enabled, the Watchdog Timer will be cleared but wake-up through an interrupt event, the corresponding keeps running, the PD bit (STATUS<3>) is cleared, the interrupt enable bit must be set (enabled). Wake-up is TO (STATUS<4>) bit is set, and the oscillator driver is regardless of the state of the GIE bit. If the GIE bit is turned off. The I/O ports maintain the status they had, clear (disabled), the device continues execution at the before the SLEEP instruction was executed (driving instruction after the SLEEP instruction. If the GIE bit is high, low, or hi-impedance). set (enabled), the device executes the instruction after For lowest current consumption in this mode, place all the SLEEP instruction and then branches to the inter- I/O pins at either VDD, or VSS, ensure no external cir- rupt address (0004h). In cases where the execution of cuitry is drawing current from the I/O pin, power-down the instruction following SLEEP is not desirable, the the A/D, disable external clocks. Pull all I/O pins, that user should have a NOP after the SLEEP instruction. are hi-impedance inputs, high or low externally to avoid switching currents caused by floating inputs. The 11.13.2 WAKE-UP USING INTERRUPTS T0CKI input should also be at VDD or VSS for lowest When global interrupts are disabled (GIE cleared) and current consumption. The contribution from on-chip any interrupt source has both its interrupt enable bit pull-ups on PORTB should be considered. and interrupt flag bit set, one of the following will occur: The MCLR pin must be at a logic high level (VIHMC). • If the interrupt occurs before the execution of a 11.13.1 WAKE-UP FROM SLEEP SLEEP instruction, the SLEEP instruction will com- plete as a NOP. Therefore, the WDT and WDT The device can wake up from SLEEP through one of postscaler will not be cleared, the TO bit will not the following events: be set and PD bits will not be cleared. 1. External reset input on MCLR pin. • If the interrupt occurs during or after the execu- tion of a SLEEP instruction, the device will immedi- 2. Watchdog Timer Wake-up (if WDT was ately wake up from sleep. The SLEEP instruction enabled). will be completely executed before the wake-up. 3. Interrupt from INT pin, RB port change, or some Therefore, the WDT and WDT postscaler will be Peripheral Interrupts. cleared, the TO bit will be set and the PD bit will External MCLR Reset will cause a device reset. All be cleared. other events are considered a continuation of program Even if the flag bits were checked before executing a execution and cause a "wake-up". The TO and PD bits SLEEP instruction, it may be possible for flag bits to in the STATUS register can be used to determine the become set before the SLEEP instruction completes. To cause of device reset. The PD bit, which is set on determine whether a SLEEP instruction executed, test power-up, is cleared when SLEEP is invoked. The TO bit the PD bit. If the PD bit is set, the SLEEP instruction was is cleared if a WDT time-out occurred (and caused executed as a NOP. wake-up). To ensure that the WDT is cleared, a CLRWDT instruc- The following peripheral interrupts can wake the device tion should be executed before a SLEEP instruction. from SLEEP: 1. PSP read or write. 2. TMR1 interrupt. Timer1 must be operating as an asynchronous counter. 3. CCP capture mode interrupt. 4. Special event trigger (Timer1 in asynchronous mode using an external clock). 5. SSP (Start/Stop) bit detect interrupt. 6. SSP transmit or receive in slave mode (SPI/I2C). 7. USART RX or TX (synchronous slave mode). 8. A/D conversion (when A/D clock source is RC). 1998 Microchip Technology Inc. DS30605A-page 93,

FIGURE 11-14: WAKE-UP FROM SLEEP THROUGH INTERRUPT

Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 CLKOUT(4) TOST(2) INT pin INTF flag (INTCON<1>) Interrupt Latency (Note 2) GIE bit (INTCON<7>) Processor in

SLEEP

INSTRUCTION FLOW PC PC PC+1 PC+2 PC+2 PC + 2 0004h 0005h Instruction fetched Inst(PC) = SLEEP Inst(PC + 1) Inst(PC + 2) Inst(0004h) Inst(0005h) Instruction executed Inst(PC - 1) SLEEP Inst(PC + 1) Dummy cycle Dummy cycle Inst(0004h) Note 1: XT, HS or LP oscillator mode assumed. 2: TOST = 1024TOSC (drawing not to scale) This delay will not be there for RC osc mode. 3: GIE = '1' assumed. In this case after wake- up, the processor jumps to the interrupt routine. If GIE = '0', execution will continue in-line. 4: CLKOUT is not available in these osc modes, but shown here for timing reference. 11.14 Program Verification/Code Protection If the code protection bit(s) have not been pro- grammed, the on-chip program memory can be read out for verification purposes. Note: Microchip Technology does not recom- mend code protecting windowed devices. 11.15 ID Locations Four memory locations (2000h - 2003h) are designated as ID locations where the user can store checksum or other code-identification numbers. These locations are not accessible during normal execution but are read- able and writable during program/verify. It is recom- mended that only the 4 least significant bits of the ID location are used. For ROM devices, these values are submitted along with the ROM code. 11.16 In-Circuit Serial Programming PIC16CXXX microcontrollers can be serially pro- grammed while in the end application circuit. This is simply done with two lines for clock and data, and three other lines for power, ground and the programming volt- age. This allows customers to manufacture boards with unprogrammed devices, and then program the micro- controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. For complete details of serial programming, please refer to the In-Circuit Serial Programming (ICSP™) Guide, (DS30277B). DS30605A-page 94 1998 Microchip Technology Inc., 12.0 INSTRUCTION SET SUMMARY Table 12-2 lists the instructions recognized by the MPASM assembler. Each PIC16CXXX instruction is a 14-bit word divided into an OPCODE which specifies the instruction type Figure 12-1 shows the general formats that the instruc- and one or more operands which further specify the tions can have. operation of the instruction. The PIC16CXX instruction Note: To maintain upward compatibility with set summary in Table 12-2 lists byte-oriented, bit-ori- future PIC16CXXX products, do not use ented, and literal and control operations. Table 12-1 the OPTION and TRIS instructions. shows the opcode field descriptions. All examples use the following format to represent a For byte-oriented instructions, 'f' represents a file reg- hexadecimal number: ister designator and 'd' represents a destination desig- nator. The file register designator specifies which file 0xhh register is to be used by the instruction. where h signifies a hexadecimal digit. The destination designator specifies where the result of the operation is to be placed. If 'd' is zero, the result is FIGURE 12-1: GENERAL FORMAT FOR placed in the W register. If 'd' is one, the result is placed INSTRUCTIONS in the file register specified in the instruction. Byte-oriented file register operations For bit-oriented instructions, 'b' represents a bit field 138760designator which selects the number of the bit affected OPCODEdf(FILE #) by the operation, while 'f' represents the number of the d = 0 for destination W file in which the bit is located. d = 1 for destination f For literal and control operations, 'k' represents an f = 7-bit file register address eight or eleven bit constant or literal value. Bit-oriented file register operations

TABLE 12-1: OPCODE FIELD 13 109760 DESCRIPTIONS OPCODE b (BIT #) f (FILE #)

Field Description b = 3-bit bit address f = 7-bit file register address f Register file address (0x00 to 0x7F) W Working register (accumulator) Literal and control operations b Bit address within an 8-bit file register k Literal field, constant data or label General x Don't care location (= 0 or 1) 13870The assembler will generate code with x = 0. It is the OPCODE k (literal) recommended form of use for compatibility with all Microchip Technology software tools. k = 8-bit immediate value d Destination select; d = 0: store result in W, d = 1: store result in file register f. Default is d = 1 CALL and GOTO instructions only PC Program Counter 13 11 10 0 TO Time-out bit OPCODE k (literal) PD Power-down bit k = 11-bit immediate value The instruction set is highly orthogonal and is grouped into three basic categories: A description of each instruction is available in the PICmicro Mid-Range Reference Manual, • Byte-oriented operations (DS33023). • Bit-oriented operations • Literal and control operations All instructions are executed within one single instruc- tion cycle, unless a conditional test is true or the pro- gram counter is changed as a result of an instruction. In this case, the execution takes two instruction cycles with the second cycle executed as a NOP. One instruc- tion cycle consists of four oscillator periods. Thus, for an oscillator frequency of 4 MHz, the normal instruction execution time is 1 µs. If a conditional test is true or the program counter is changed as a result of an instruc- tion, the instruction execution time is 2 µs. 1998 Microchip Technology Inc. DS30605A-page 95,

TABLE 12-2: PIC16CXXX INSTRUCTION SET

Mnemonic, Description Cycles 14-Bit Opcode Status Notes Operands MSb LSb Affected BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W andf100 0111 dfff ffff C,DC,Z 1,2 ANDWF f, d AND W withf100 0101 dfff ffff Z 1,2 CLRF f Clearf100 0001 lfff ffffZ2CLRW - ClearW100 0001 0xxx xxxx Z COMF f, d Complementf100 1001 dfff ffff Z 1,2 DECF f, d Decrementf100 0011 dfff ffff Z 1,2 DECFSZ f, d Decrement f, Skip if 0 1(2) 00 1011 dfff ffff 1,2,3 INCF f, d Incrementf100 1010 dfff ffff Z 1,2 INCFSZ f, d Increment f, Skip if 0 1(2) 00 1111 dfff ffff 1,2,3 IORWF f, d Inclusive OR W withf100 0100 dfff ffff Z 1,2 MOVF f, d Movef100 1000 dfff ffff Z 1,2 MOVWF f Move W tof100 0000 lfff ffff NOP - No Operation 1 00 0000 0xx0 0000 RLF f, d Rotate Left f through Carry 1 00 1101 dfff ffff C 1,2 RRF f, d Rotate Right f through Carry 1 00 1100 dfff ffff C 1,2 SUBWF f, d Subtract W fromf100 0010 dfff ffff C,DC,Z 1,2 SWAPF f, d Swap nibbles inf100 1110 dfff ffff 1,2 XORWF f, d Exclusive OR W withf100 0110 dfff ffff Z 1,2 BIT-ORIENTED FILE REGISTER OPERATIONS BCF f, b Bit Clearf101 00bb bfff ffff 1,2 BSF f, b Bit Setf101 01bb bfff ffff 1,2 BTFSC f, b Bit Test f, Skip if Clear 1 (2) 01 10bb bfff ffff 3 BTFSS f, b Bit Test f, Skip if Set 1 (2) 01 11bb bfff ffff 3 LITERAL AND CONTROL OPERATIONS ADDLW k Add literal andW111 111x kkkk kkkk C,DC,Z ANDLW k AND literal withW111 1001 kkkk kkkk Z CALL k Call subroutine 2 10 0kkk kkkk kkkk CLRWDT - Clear Watchdog Timer 1 00 0000 0110 0100 TO,PD GOTO k Go to address 2 10 1kkk kkkk kkkk IORLW k Inclusive OR literal withW111 1000 kkkk kkkk Z MOVLW k Move literal toW111 00xx kkkk kkkk RETFIE - Return from interrupt 2 00 0000 0000 1001 RETLW k Return with literal inW211 01xx kkkk kkkk RETURN - Return from Subroutine 2 00 0000 0000 1000 SLEEP - Go into standby mode 1 00 0000 0110 0011 TO,PD SUBLW k Subtract W from literal 1 11 110x kkkk kkkk C,DC,Z XORLW k Exclusive OR literal withW111 1010 kkkk kkkk Z Note 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value present on the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an external device, the data will be written back with a '0'. 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a NOP. DS30605A-page 96 1998 Microchip Technology Inc.,

PIC16C62X(A)

13.0 DEVELOPMENT SUPPORT 13.3 ICEPIC: Low-Cost PICmicro™ In-Circuit Emulator 13.1 Development Tools ICEPIC is a low-cost in-circuit emulator solution for the The PICmicrο microcontrollers are supported with a Microchip PIC12CXXX, PIC16C5X and PIC16CXXX full range of hardware and software development tools: families of 8-bit OTP microcontrollers. • PICMASTER/PICMASTER CE Real-Time ICEPIC is designed to operate on PC-compatible In-Circuit Emulator machines ranging from 286-AT through Pentium • ICEPIC Low-Cost PIC16C5X and PIC16CXXX based machines under Windows 3.x environment. In-Circuit Emulator ICEPIC features real time, non-intrusive emulation. • PRO MATE II Universal Programmer 13.4 PRO MATE II: Universal Programmer• PICSTART Plus Entry-Level Prototype Programmer The PRO MATE II Universal Programmer is a full-fea- • PICDEM-1 Low-Cost Demonstration Board tured programmer capable of operating in stand-alone • PICDEM-2 Low-Cost Demonstration Board mode as well as PC-hosted mode. PRO MATE II is CE • PICDEM-3 Low-Cost Demonstration Board compliant. • MPASM Assembler The PRO MATE II has programmable VDD and VPP • MPLAB SIM Software Simulator supplies which allows it to verify programmed memory at VDD min and VDD max for maximum reliability. It has • MPLAB-C17 (C Compiler) an LCD display for displaying error messages, keys to • Fuzzy Logic Development System enter commands and a modular detachable socket (fuzzyTECH−MP) assembly to support various package types. In stand- alone mode the PRO MATE II can read, verify or pro- 13.2 PICMASTER: High Performance gram PIC12CXXX, PIC14C000, PIC16C5X, Universal In-Circuit Emulator with PIC16CXXX and PIC17CXX devices. It can also set MPLAB IDE configuration and code-protect bits in this mode. The PICMASTER Universal In-Circuit Emulator is 13.5 PICSTART Plus Entry Level intended to provide the product development engineer Development System with a complete microcontroller design tool set for all microcontrollers in the PIC14C000, PIC12CXXX, The PICSTART programmer is an easy-to-use, PIC16C5X, PIC16CXXX and PIC17CXX families. low-cost prototype programmer. It connects to the PC PICMASTER is supplied with the MPLAB Integrated via one of the COM (RS-232) ports. MPLAB Integrated Development Environment (IDE), which allows editing, Development Environment software makes using the “make” and download, and source debugging from a programmer simple and efficient. PICSTART Plus is single environment. not recommended for production programming. Interchangeable target probes allow the system to be PICSTART Plus supports all PIC12CXXX, PIC14C000, easily reconfigured for emulation of different proces- PIC16C5X, PIC16CXXX and PIC17CXX devices with sors. The universal architecture of the PICMASTER up to 40 pins. Larger pin count devices such as the allows expansion to support all new Microchip micro- PIC16C923, PIC16C924 and PIC17C756 may be sup- controllers. ported with an adapter socket. PICSTART Plus is CE The PICMASTER Emulator System has been compliant. designed as a real-time emulation system with advanced features that are generally found on more expensive development tools. The PC compatible 386 (and higher) machine platform and Microsoft Windows 3.x environment were chosen to best make these fea- tures available to you, the end user. A CE compliant version of PICMASTER is available for European Union (EU) countries. 1998 Microchip Technology Inc. DS30605A-page 97,

PIC16C62X(A)

13.6 PICDEM-1 Low-Cost PICmicro an RS-232 interface, push-button switches, a potenti- Demonstration Board ometer for simulated analog input, a thermistor and separate headers for connection to an external LCD The PICDEM-1 is a simple board which demonstrates module and a keypad. Also provided on the PICDEM-3 the capabilities of several of Microchip’s microcontrol- board is an LCD panel, with 4 commons and 12 seg- lers. The microcontrollers supported are: PIC16C5X ments, that is capable of displaying time, temperature (PIC16C54 to PIC16C58A), PIC16C61, PIC16C62X, and day of the week. The PICDEM-3 provides an addi- PIC16C71, PIC16C8X, PIC17C42, PIC17C43 and tional RS-232 interface and Windows 3.1 software for PIC17C44. All necessary hardware and software is showing the demultiplexed LCD signals on a PC. A sim- included to run basic demo programs. The users can ple serial interface allows the user to construct a hard- program the sample microcontrollers provided with ware demultiplexer for the LCD signals. the PICDEM-1 board, on a PRO MATE II or PICSTART-Plus programmer, and easily test firm- 13.9 MPLAB™ Integrated Development ware. The user can also connect the PICDEM-1 Environment Software board to the PICMASTER emulator and download the firmware to the emulator for testing. Additional pro- The MPLAB IDE Software brings an ease of software totype area is available for the user to build some addi- development previously unseen in the 8-bit microcon- tional hardware and connect it to the microcontroller troller market. MPLAB is a windows based application socket(s). Some of the features include an RS-232 which contains: interface, a potentiometer for simulated analog input, • A full featured editor push-button switches and eight LEDs connected to • Three operating modes PORTB. - editor - emulator 13.7 PICDEM-2 Low-Cost PIC16CXXX - simulator Demonstration Board • A project manager • Customizable tool bar and key mapping The PICDEM-2 is a simple demonstration board that • A status bar with project information supports the PIC16C62, PIC16C64, PIC16C65, • Extensive on-line help PIC16C73 and PIC16C74 microcontrollers. All the necessary hardware and software is included to MPLAB allows you to: run the basic demonstration programs. The user • Edit your source files (either assembly or ‘C’) can program the sample microcontrollers provided • One touch assemble (or compile) and download with the PICDEM-2 board, on a PRO MATE II pro- to PICmicro tools (automatically updates all grammer or PICSTART-Plus, and easily test firmware. project information) The PICMASTER emulator may also be used with the • Debug using: PICDEM-2 board to test firmware. Additional prototype - source files area has been provided to the user for adding addi- - absolute listing file tional hardware and connecting it to the microcontroller • Transfer data dynamically via DDE (soon to be socket(s). Some of the features include a RS-232 inter- replaced by OLE) face, push-button switches, a potentiometer for simu- • Run up to four emulators on the same PC lated analog input, a Serial EEPROM to demonstrate usage of the I2C bus and separate headers for connec- The ability to use MPLAB with Microchip’s simulator tion to an LCD module and a keypad. allows a consistent platform and the ability to easily switch from the low cost simulator to the full featured 13.8 PICDEM-3 Low-Cost PIC16CXXX emulator with minimal retraining due to development Demonstration Board tools. The PICDEM-3 is a simple demonstration board that 13.10 Assembler (MPASM) supports the PIC16C923 and PIC16C924 in the PLCC The MPASM Universal Macro Assembler is a package. It will also support future 44-pin PLCC PC-hosted symbolic assembler. It supports all micro- microcontrollers with a LCD Module. All the neces- controller series including the PIC12C5XX, PIC14000, sary hardware and software is included to run the PIC16C5X, PIC16CXXX, and PIC17CXX families. basic demonstration programs. The user can pro- gram the sample microcontrollers provided with MPASM offers full featured Macro capabilities, condi- the PICDEM-3 board, on a PRO MATE II program- tional assembly, and several source and listing formats. mer or PICSTART Plus with an adapter socket, and It generates various object code formats to support easily test firmware. The PICMASTER emulator may Microchip's development tools as well as third party also be used with the PICDEM-3 board to test firm- programmers. ware. Additional prototype area has been provided to MPASM allows full symbolic debugging from the user for adding hardware and connecting it to the PICMASTER, Microchip’s Universal Emulator System. microcontroller socket(s). Some of the features include DS30605A-page 98 1998 Microchip Technology Inc.,

PIC16C62X(A)

MPASM has the following features to assist in develop- 13.14 MP-DriveWay – Application Code ing software for specific use applications. Generator • Provides translation of Assembler source code to object code for all Microchip microcontrollers. MP-DriveWay is an easy-to-use Windows-based Appli- cation Code Generator. With MP-DriveWay you can • Macro assembly capability. visually configure all the peripherals in a PICmicro • Produces all the files (Object, Listing, Symbol, device and, with a click of the mouse, generate all the and special) required for symbolic debug with initialization and many functional code modules in C Microchip’s emulator systems. language. The output is fully compatible with Micro- • Supports Hex (default), Decimal and Octal source chip’s MPLAB-C C compiler. The code produced is and listing formats. highly modular and allows easy integration of your own MPASM provides a rich directive language to support code. MP-DriveWay is intelligent enough to maintain programming of the PICmicro. Directives are helpful in your code through subsequent code generation. making the development of your assemble source code 13.15 SEEVAL Evaluation and shorter and more maintainable. Programming System 13.11 Software Simulator (MPLAB-SIM) The SEEVAL SEEPROM Designer’s Kit supports all The MPLAB-SIM Software Simulator allows code Microchip 2-wire and 3-wire Serial EEPROMs. The kit development in a PC host environment. It allows the includes everything necessary to read, write, erase or user to simulate the PICmicro series microcontrollers program special features of any Microchip SEEPROM on an instruction level. On any given instruction, the product including Smart Serials and secure serials. user may examine or modify any of the data areas or The Total Endurance Disk is included to aid in provide external stimulus to any of the pins. The trade-off analysis and reliability calculations. The total input/output radix can be set by the user and the exe- kit can significantly reduce time-to-market and result in cution can be performed in; single step, execute until an optimized system. break, or in a trace mode. 13.16 KEELOQ Evaluation and MPLAB-SIM fully supports symbolic debugging using Programming Tools MPLAB-C and MPASM. The Software Simulator offers the low cost flexibility to develop and debug code out- KEELOQ evaluation and programming tools support side of the laboratory environment making it an excel- Microchips HCS Secure Data Products. The HCS eval- lent multi-project software development tool. uation kit includes an LCD display to show changing codes, a decoder to decode transmissions, and a pro- 13.12 C Compiler (MPLAB-C17) gramming interface to program test transmitters. The MPLAB-C Code Development System is a complete ‘C’ compiler and integrated development environment for Microchip’s PIC17CXXX family of microcontrollers. The compiler provides powerful inte- gration capabilities and ease of use not found with other compilers. For easier source level debugging, the compiler pro- vides symbol information that is compatible with the MPLAB IDE memory display. 13.13 Fuzzy Logic Development System (fuzzyTECH-MP) fuzzyTECH-MP fuzzy logic development tool is avail- able in two versions - a low cost introductory version, MP Explorer, for designers to gain a comprehensive working knowledge of fuzzy logic system design; and a full-featured version, fuzzyTECH-MP, Edition for imple- menting more complex systems. Both versions include Microchip’s fuzzyLAB demon- stration board for hands-on experience with fuzzy logic systems implementation. 1998 Microchip Technology Inc. DS30605A-page 99,

PIC16C62X(A) TABLE 13-1 DEVELOPMENT TOOLS FROM MICROCHIP

DS30605A-page 100 1998 Microchip Technology Inc. 24CXX PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX 25CXX 93CXX HCSXXX

EMULATOR PRODUCTS

PICMASTER/ PICMASTER-CE (PIC17C75X only) In-Circuit EmulatorüüüüüüüüüüMPLAB™-ICE ü ICEPIC Low-Cost In-Circuit Emulatorüüüüüüü

SOFTWARE PRODUCTS

MPLAB Integrated Development EnvironmentüüüüüüüüüüMPLAB C17 CompilerüüfuzzyTECH-MP Explorer/Edition Fuzzy Logic Dev. ToolüüüüüüüüüMP-DriveWay Applications Code GeneratorüüüüüüüTotal Endurance Software Model ü

PROGRAMMERS

PICSTARTPlus Low-Cost Universal Dev. KitüüüüüüüüüüPRO MATE II Universal ProgrammerüüüüüüüüüüüüKEELOQ Programmer ü

DEMO BOARDS

SEEVAL Designers Kit ü PICDEM-1üüüüPICDEM-2üüPICDEM-3 ü, 14.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) Ambient temperature under bias... .-55˚C to +125˚C Storage temperature ... -65˚C to +150˚C Voltage on any pin with respect to VSS (except VDD, MCLR, and RA4)... -0.3V to (VDD + 0.3V) Voltage on VDD with respect to VSS ... -0.3V to +7.5V Voltage on MCLR with respect to VSS (Note 2)... 0V to +13.25V Voltage on RA4 with respect to Vss ... 0V to +8.5V Total power dissipation (Note 1)...1.0W Maximum current out of VSS pin ...300 mA Maximum current into VDD pin ...250 mA Input clamp current, IIK (VI < 0 or VI > VDD)...±20 mA Output clamp current, IOK (VO < 0 or VO > VDD) ...±20 mA Maximum output current sunk by any I/O pin...25 mA Maximum output current sourced by any I/O pin ...25 mA Maximum current sunk by PORTA, PORTB, and PORTE (Note 3) (combined)...200 mA Maximum current sourced by PORTA, PORTB, and PORTE (Note 3) (combined) ...200 mA Maximum current sunk by PORTC and PORTD (Note 3) (combined) ...200 mA Maximum current sourced by PORTC and PORTD (Note 3) (combined) ...200 mA Note 1: Power dissipation is calculated as follows: Pdis = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOl x IOL) Note 2: Voltage spikes below VSS at the MCLR/VPP pin, inducing currents greater than 80 mA, may cause latch-up. Thus, a series resistor of 50-100Ω should be used when applying a “low” level to the MCLR/VPP pin rather than pulling this pin directly to VSS. Note 3: PORTD and PORTE not available on the PIC16C63A/73B. † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

TABLE 14-1: CROSS REFERENCE OF DEVICE SPECS FOR OSCILLATOR MODES AND FREQUENCIES OF OPERATION (COMMERCIAL DEVICES)

PIC16C63A-04 PIC16C63A-20 PIC16LC63A-04 PIC16C65B-04 PIC16C65B-20 PIC16LC65B-04 OSC Windowed (JW) Devices PIC16C73B-04 PIC16C73B-20 PIC16LC73B-04 PIC16C74B-04 PIC16C74B-20 PIC16LC74B-04 RC VDD: 4.0V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 5.5V VDD: 2.5V to 5.5V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA max. at 3V IDD: 3.8 mA max. at 3V IPD: 16 µA max. at 4V IPD: 1.5 µA typ. at 4V IPD: 5 µA max. at 3V IPD: 5 µA max. at 3V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. XT VDD: 4.0V to 5.5V VDD: 4.5V to 5.5V VDD: 2.5V to 5.5V VDD: 2.5V to 5.5V IDD: 5 mA max. at 5.5V IDD: 2.7 mA typ. at 5.5V IDD: 3.8 mA max. at 3V IDD: 3.8 mA max. at 3V IPD: 16 µA max. at 4V IPD: 1.5 µA typ. at 4V IPD: 5 µA max. at 3V IPD: 5 µA max. at 3V Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. Freq: 4 MHz max. HS VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V VDD: 4.5V to 5.5V IDD: 13.5 mA typ. at 5.5V IDD: 20 mA max. at 5.5V Not recomm ended for use in IDD: 20 mA max. at 5.5V IPD: 1.5 µA typ. at 4.5V IPD: 1.5 µA typ. at 4.5V HS mode IPD: 1.5 µA typ. at 4.5V Freq: 4 MHz max. Freq: 20 MHz max. Freq: 20 MHz max. LP VDD: 4.0V to 5.5V VDD: 2.5V to 5.5V VDD: 2.5V to 5.5V IDD: 52.5 µA typ. Not recomm ended for use in IDD: 48 µA max. at 32 kHz, IDD: 48 µA max. at 32 kHz, at 32 kHz, 4.0V LP mode 3.0V 3.0V IPD: 0.9 µA typ. at 4.0V IPD: 5 µA max. at 3.0V IPD: 5 µA max. at 3.0V Freq: 200 kHz max. Freq: 200 kHz max. Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications. It is recom- mended that the user select the device type that ensures the specifications required. 1998 Microchip Technology Inc. Preliminary DS30605A-page 101, 14.1 DC Characteristics: PIC16C63A/65B/73B/74B-04 (Commercial, Industrial, Extended) PIC16C6A/65B/73B/74B-20 (Commercial, Industrial, Extended) Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C ≤ TA ≤ +70˚C for commercial DC CHARACTERISTICS -40˚C ≤ TA ≤ +85˚C for industrial -40˚C ≤ TA ≤ +125˚C for extended Param Sym Characteristic Min Typ† Max Units Conditions No. D001 VDD Supply Voltage 4.0 - 5.5 V XT, RC and LP osc mode D001A 4.5 - 5.5 V HS osc mode VBOR* - 5.5 V BOR enabled (Note 7) D002* VDR RAM Data Retention - 1.5 - V Voltage (Note 1) D003 VPOR VDD Start Voltage to - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* SVDD VDD Rise Rate to 0.05 - - V/ms PWRT enabled (PWRTE bit clear) D004A* ensure internal TBD - - PWRT disabled (PWRTE bit set) Power-on Reset signal See section on Power-on Reset for details D005 VBOR Brown-out Reset 3.65 - 4.35 V BODEN bit set voltage trip point D010 IDD Supply Current - 2.7 5 mA XT, RC osc modes (Note 2, 5) FOSC = 4 MHz, VDD = 5.5V (Note 4) D013 - 10 20 mA HS osc mode FOSC = 20 MHz, VDD = 5.5V D020 IPD Power-down Current - 10.5 42 µA VDD = 4.0V, WDT enabled,-40°C to +85°C (Note 3, 5) - 1.5 16 µA VDD = 4.0V, WDT disabled, 0°C to +70°C D021 - 1.5 19 µA VDD = 4.0V, WDT disabled,-40°C to +85°C D021B - 2.5 19 µA VDD = 4.0V, WDT disabled,-40°C to +125°C Module Differential Current (Note 6) D022* ∆IWDT Watchdog Timer - 6.0 20 µA WDTE bit set, VDD = 4.0V D022A* ∆IBOR Brown-out Reset - 350 425 µA BODEN bit set, VDD = 5.0V * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac- terization and is for design guidance only. This is not tested. 6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached. DS30605A-page 102 Preliminary 1998 Microchip Technology Inc., 14.2 DC Characteristics: PIC16LC63A/65B/73B/74B-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) DC CHARACTERISTICS Operating temperature 0˚C ≤ TA ≤ +70˚C for commercial -40˚C ≤ TA ≤ +85˚C for industrial Param Sym Characteristic Min Typ† Max Units Conditions No. D001 VDD Supply Voltage 2.5 - 5.5 V LP, XT, RC osc modes (DC - 4 MHz) VBOR* - 5.5 V BOR enabled (Note 7) D002* VDR RAM Data Retention - 1.5 - V Voltage (Note 1) D003 VPOR VDD Start Voltage to - VSS - V See section on Power-on Reset for details ensure internal Power-on Reset signal D004* SVDD VDD Rise Rate to 0.05 - - V/ms PWRT enabled (PWRTE bit clear) D004A* ensure internal TBD - - PWRT disabled (PWRTE bit set) Power-on Reset signal See section on Power-on Reset for details D005 VBOR Brown-out Reset 3.65 - 4.35 V BODEN bit set voltage trip point D010 IDD Supply Current - 2.0 3.8 mA XT, RC osc modes (Note 2, 5) FOSC = 4 MHz, VDD = 3.0V (Note 4) D010A - 22.5 48 µA LP osc mode FOSC = 32 kHz, VDD = 3.0V, WDT disabled D020 IPD Power-down Current - 7.5 30 µA VDD = 3.0V, WDT enabled, -40°C to +85°C D021 (Note 3, 5) - 0.9 5 µA VDD = 3.0V, WDT disabled, 0°C to +70°C D021A - 0.9 5 µA VDD = 3.0V, WDT disabled, -40°C to +85°C Module Differential Current (Note 6) D022* ∆IWDT Watchdog Timer - 6.0 20 µA WDTE bit set, VDD = 4.0V D022A* ∆IBOR Brown-out Reset - 350 425 µA BODEN bit set, VDD = 5.0V * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: This is the limit to which VDD can be lowered without losing RAM data. 2: The supply current is mainly a function of the operating voltage and frequency. Other factors such as I/O pin loading and switching rate, oscillator type, internal code execution pattern, and temperature also have an impact on the current consumption. The test conditions for all IDD measurements in active operation mode are: OSC1 = external square wave, from rail to rail; all I/O pins tristated, pulled to VDD, MCLR = VDD; WDT enabled/disabled as specified. 3: The power-down current in SLEEP mode does not depend on the oscillator type. Power-down current is measured with the part in SLEEP mode, with all I/O pins in hi-impedance state and tied to VDD and VSS. 4: For RC osc mode, current through Rext is not included. The current through the resistor can be estimated by the formula Ir = VDD/2Rext (mA) with Rext in kOhm. 5: Timer1 oscillator (when enabled) adds approximately 20 µA to the specification. This value is from charac- terization and is for design guidance only. This is not tested. 6: The ∆ current is the additional current consumed when this peripheral is enabled. This current should be added to the base IDD or IPD measurement. 7: When BOR is enabled, the device will operate correctly until the VBOR voltage trip point is reached.. 1998 Microchip Technology Inc. Preliminary DS30605A-page 103, 14.3 DC Characteristics: PIC16C63A/65B/73B/74B-04 (Commercial, Industrial, Extended) PIC16C63A/65B/73B/74B-20 (Commercial, Industrial, Extended) PIC16LC63A/65B/73B/74B-04 (Commercial, Industrial) Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C ≤ TA ≤ +70˚C for commercial -40˚C ≤ TA ≤ +85˚C for industrial DC CHARACTERISTICS -40˚C ≤ TA ≤ +125˚C for extended Operating voltage VDD range as described in DC spec Section 14.1 and Section 14.2 Param Sym Characteristic Min Typ† Max Units Conditions No. Input Low Voltage VIL I/O ports D030 with TTL buffer VSS - 0.15VDD V For entire VDD range D030A VSS - 0.8V V 4.5V ≤ VDD ≤ 5.5V D031 with Schmitt Trigger buffer VSS - 0.2VDD V D032 MCLR, OSC1 (in RC mode) Vss - 0.2VDD V D033 OSC1 (in XT, HS and LP Vss - 0.3VDD V Note1 modes) Input High Voltage VIH I/O ports - D040 with TTL buffer 2.0 - VDD V 4.5V ≤ VDD ≤ 5.5V D040A 0.25VDD - VDD V For entire VDD range + 0.8V D041 with Schmitt Trigger buffer 0.8VDD - VDD V For entire VDD range D042 MCLR 0.8VDD - VDD V D042A OSC1 (XT, HS and LP modes) 0.7VDD - VDD V Note1 D043 OSC1 (in RC mode) 0.9VDD - VDD V Input Leakage Current (Notes 2, 3) D060 IIL I/O ports - - ±1 µA Vss ≤ VPIN ≤ VDD, Pin at hi-impedance D061 MCLR, RA4/T0CKI - - ±5 µA Vss ≤ VPIN ≤ VDD D063 OSC1 - - ±5 µA Vss ≤ VPIN ≤ VDD, XT, HS and LP osc modes D070 IPURB PORTB weak pull-up current 50 250 400 µA VDD = 5V, VPIN = VSS Output Low Voltage D080 VOL I/O ports - - 0.6 V IOL = 8.5 mA, VDD = 4.5V, -40°C to +85°C - - 0.6 V IOL = 7.0 mA, VDD = 4.5V, -40°C to +125°C D083 OSC2/CLKOUT (RC osc - - 0.6 V IOL = 1.6 mA, VDD = 4.5V, mode) -40°C to +85°C - - 0.6 V IOL = 1.2 mA, VDD = 4.5V, -40°C to +125°C * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmi- cro be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin. DS30605A-page 104 Preliminary 1998 Microchip Technology Inc., Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C ≤ TA ≤ +70˚C for commercial -40˚C ≤ TA ≤ +85˚C for industrial DC CHARACTERISTICS -40˚C ≤ TA ≤ +125˚C for extended Operating voltage VDD range as described in DC spec Section 14.1 and Section 14.2 Param Sym Characteristic Min Typ† Max Units Conditions No. Output High Voltage D090 VOH I/O ports (Note 3) VDD-0.7 - - V IOH = -3.0 mA, VDD = 4.5V, -40°C to +85°C VDD-0.7 - - V IOH = -2.5 mA, VDD = 4.5V, -40°C to +125°C D092 OSC2/CLKOUT (RC osc VDD-0.7 - - V IOH = -1.3 mA, VDD = 4.5V, mode) -40°C to +85°C VDD-0.7 - - V IOH = -1.0 mA, VDD = 4.5V, -40°C to +125°C D150* VOD Open-Drain High Voltage - - 8.5 V RA4 pin Capacitive Loading Specs on Output Pins D100 COSC2 OSC2 pin - - 15 pF In XT, HS and LP modes when external clock is used to drive OSC1. D101 CIO All I/O pins and OSC2 (in RC - - 50 pF mode) D102 Cb SCL, SDA in I2C mode - - 400 pF * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: In RC oscillator mode, the OSC1/CLKIN pin is a Schmitt Trigger input. It is not recommended that the PICmi- cro be driven with external clock in RC mode. 2: The leakage current on the MCLR/VPP pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input volt- ages. 3: Negative current is defined as current sourced by the pin. 1998 Microchip Technology Inc. Preliminary DS30605A-page 105, 14.4 AC (Timing) Characteristics 14.4.1 TIMING PARAMETER SYMBOLOGY The timing parameter symbols have been created fol- lowing one of the following formats: 1. TppS2ppS 3. TCC:ST (I2C specifications only) 2. TppS 4. Ts (I2C specifications only)

T

F Frequency T Time Lowercase letters (pp) and their meanings: pp cc CCP1 osc OSC1 ck CLKOUT rd RD cs CS rw RD or WR di SDI sc SCK do SDO ss SS dt Data in t0 T0CKI io I/O port t1 T1CKI mc MCLR wr WR Uppercase letters and their meanings:

S

F Fall P Period H High R Rise I Invalid (Hi-impedance) V Valid L Low Z Hi-impedance I2C only AA output access High High BUF Bus free Low Low TCC:ST (I2C specifications only)

CC

HD Hold SU Setup

ST

DAT DATA input hold STO STOP condition STA START condition DS30605A-page 106 Preliminary 1998 Microchip Technology Inc., 14.4.2 TIMING CONDITIONS The temperature and voltages specified in Table 14-1 apply to all timing specifications unless otherwise noted. Figure 14-1 specifies the load conditions for the timing specifications.

TABLE 14-1: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC

Standard Operating Conditions (unless otherwise stated) Operating temperature 0˚C ≤ TA ≤ +70˚C for commercial -40˚C ≤ TA ≤ +85˚C for industrial AC CHARACTERISTICS -40˚C ≤ TA ≤ +125˚C for extended Operating voltage VDD range as described in DC spec Section 14.1 and Section 14.2. LC parts operate for commercial/industrial temp’s only.

FIGURE 14-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load condition 1 Load condition 2 VDD/2 RL Pin CL

VSS

Pin CL RL = 464Ω VSS CL = 50 pF for all pins except OSC2/CLKOUT Note1: PORTD and PORTE are not imple- but including D and E outputs as ports mented on the PIC16C63A/73B. 15 pF for OSC2 output 1998 Microchip Technology Inc. Preliminary DS30605A-page 107, 14.4.3 TIMING DIAGRAMS AND SPECIFICATIONS

FIGURE 14-2: EXTERNAL CLOCK TIMING

Q4 Q1 Q2 Q3 Q4 Q1 OSC113344

CLKOUT TABLE 14-2: EXTERNAL CLOCK TIMING REQUIREMENTS

Param Sym Characteristic Min Typ† Max Units Conditions No. 1A Fosc External CLKIN Frequency DC — 4 MHz RC and XT osc modes (Note 1) DC — 4 MHz HS osc mode (-04) DC — 20 MHz HS osc mode (-20) DC — 200 kHz LP osc mode Oscillator Frequency DC — 4 MHz RC osc mode (Note 1) 0.1 — 4 MHz XT osc mode 4 — 20 MHz HS osc mode 5 — 200 kHz LP osc mode 1 Tosc External CLKIN Period 250 — — ns RC and XT osc modes (Note 1) 250 — — ns HS osc mode (-04) 50 — — ns HS osc mode (-20) 5 — — µs LP osc mode Oscillator Period 250 — — ns RC osc mode (Note 1) 250 — 10,000 ns XT osc mode 250 — 250 ns HS osc mode (-04) 50 — 250 ns HS osc mode (-20) 5 — — µs LP osc mode 2 TCY Instruction Cycle Time (Note 1) 200 — DC ns TCY = 4/FOSC 3* TosL, External Clock in (OSC1) High or 100 — — ns XT oscillator TosH Low Time 2.5 — — µs LP oscillator 15 — — ns HS oscillator 4* TosR, External Clock in (OSC1) Rise or — — 25 ns XT oscillator TosF Fall Time — — 50 ns LP oscillator — — 15 ns HS oscillator * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Instruction cycle period (TCY) equals four times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "min." values with an external clock applied to the OSC1/CLKIN pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. DS30605A-page 108 Preliminary 1998 Microchip Technology Inc.,

FIGURE 14-3: CLKOUT AND I/O TIMING

Q4 Q1 Q2 Q3 OSC1 10 11

CLKOUT

13 12 14 19 18 I/O Pin (input) 17 15 I/O Pin old value new value(output) 20, 21 Note: Refer to Figure 14-1 for load conditions.

TABLE 14-3: CLKOUT AND I/O TIMING REQUIREMENTS

Param Sym Characteristic Min Typ† Max Units Conditions No. 10* TosH2ckL OSC1↑ to CLKOUT↓ — 75 200 ns Note 1 11* TosH2ckH OSC1↑ to CLKOUT↑ — 75 200 ns Note 1 12* TckR CLKOUT rise time — 35 100 ns Note 1 13* TckF CLKOUT fall time — 35 100 ns Note 1 14* TckL2ioV CLKOUT ↓ to Port out valid — — 0.5TCY + 20 ns Note 1 15* TioV2ckH Port in valid before CLKOUT ↑ Tosc + 200 — — ns Note 1 16* TckH2ioI Port in hold after CLKOUT ↑ 0 — — ns Note 1 17* TosH2ioV OSC1↑ (Q1 cycle) to Port out valid — 50 150 ns 18* TosH2ioI OSC1↑ (Q2 cycle) to Port input Standard 100 — — ns 18A* invalid (I/O in hold time) Extended (LC) 200 — — ns 19* TioV2osH Port input valid to OSC1↑ (I/O in setup time) 0 — — ns 20* TioR Port output rise time Standard — 10 40 ns 20A* Extended (LC) — — 80 ns 21* TioF Port output fall time Standard — 10 40 ns 21A* Extended (LC) — — 80 ns 22††* Tinp INT pin high or low time TCY — — ns 23††* Trbp RB7:RB4 change INT high or low time TCY — — ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. †† These parameters are asynchronous events not related to any internal clock edge. Note1: Measurements are taken in RC Mode where CLKOUT output is4xTOSC. 1998 Microchip Technology Inc. Preliminary DS30605A-page 109,

FIGURE 14-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING VDD MCLR

Internal

POR PWRT

Time-out 32

OSC

Time-out Internal

RESET

Watchdog Timer

RESET

34 34 I/O Pins Note: Refer to Figure 14-1 for load conditions.

FIGURE 14-5: BROWN-OUT RESET TIMING BVDD VDD TABLE 14-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER, AND BROWN-OUT RESET REQUIREMENTS

Parameter Sym Characteristic Min Typ† Max Units Conditions No. 30 TmcL MCLR Pulse Width (low) 2 — — µs VDD = 5V, -40˚C to +125˚C 31* Twdt Watchdog Timer Time-out Period 7 18 33 ms VDD = 5V, -40˚C to +125˚C (No Prescaler) 32 Tost Oscillation Start-up Timer Period — 1024 TOSC — — TOSC = OSC1 period 33* Tpwrt Power-up Timer Period 28 72 132 ms VDD = 5V, -40˚C to +125˚C 34 TIOZ I/O Hi-impedance from MCLR — — 2.1 µs Low or WDT reset 35 TBOR Brown-out Reset Pulse Width 100 — — µs VDD ≤ BVDD (D005) * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30605A-page 110 Preliminary 1998 Microchip Technology Inc.,

FIGURE 14-6: TIMER0 AND TIMER1 EXTERNAL CLOCK TIMINGS

T0CKI 40 41 T1OSO/T1CKI 45 46 47 48 TMR0 or TMR1 Note: Refer to Figure 14-1 for load conditions.

TABLE 14-5: TIMER0 AND TIMER1 EXTERNAL CLOCK REQUIREMENTS

Param Sym Characteristic Min Typ† Max Units Conditions No. 40* Tt0H T0CKI High Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 41* Tt0L T0CKI Low Pulse Width No Prescaler 0.5TCY + 20 — — ns Must also meet With Prescaler 10 — — ns parameter 42 42* Tt0P T0CKI Period No Prescaler TCY + 40 — — ns With Prescaler Greater of: — — ns N = prescale value 20 or TCY + 40 (2, 4,..., 256)

N

45* Tt1H T1CKI High Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, Standard 15 — — ns parameter 47 Prescaler = Extended (LC) 25 — — ns 2,4,8 Asynchronous Standard 30 — — ns Extended (LC) 50 — — ns 46* Tt1L T1CKI Low Time Synchronous, Prescaler = 1 0.5TCY + 20 — — ns Must also meet Synchronous, Standard 15 — — ns parameter 47 Prescaler = Extended (LC) 25 — — ns 2,4,8 Asynchronous Standard 30 — — ns Extended (LC) 50 — — ns 47* Tt1P T1CKI input period Synchronous Standard Greater of: — — ns N = prescale value 30 OR TCY + 40 (1, 2, 4, 8)

N

Extended (LC) Greater of: N = prescale value 50 OR TCY + 40 (1, 2, 4, 8)

N

Asynchronous Standard 60 — — ns Extended (LC) 100 — — ns Ft1 Timer1 oscillator input frequency range DC — 200 kHz (oscillator enabled by setting bit T1OSCEN) 48 TCKEZtmr1 Delay from external clock edge to timer increment 2Tosc — 7Tosc — * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1998 Microchip Technology Inc. Preliminary DS30605A-page 111,

FIGURE 14-7: CAPTURE/COMPARE/PWM TIMINGS (CCP1 AND CCP2)

CCPx (Capture Mode) 50 51 CCPx (Compare or PWM Mode) 53 54 Note: Refer to Figure 14-1 for load conditions.

TABLE 14-6: CAPTURE/COMPARE/PWM REQUIREMENTS (CCP1 AND CCP2)

Param Sym Characteristic Min Typ† Max Units Conditions No. 50* TccL CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input low time With Prescaler Standard 10 — — ns Extended (LC) 20 — — ns 51* TccH CCP1 and CCP2 No Prescaler 0.5TCY + 20 — — ns input high time With Prescaler Standard 10 — — ns Extended (LC) 20 — — ns 52* TccP CCP1 and CCP2 input period 3TCY + 40 — — ns N = prescale value N (1,4, or 16) 53* TccR CCP1 and CCP2 output rise time Standard — 10 25 ns Extended (LC) — 25 45 ns 54* TccF CCP1 and CCP2 output fall time Standard — 10 25 ns Extended (LC) — 25 45 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30605A-page 112 Preliminary 1998 Microchip Technology Inc.,

FIGURE 14-8: PARALLEL SLAVE PORT TIMING (PIC16C65B/74B)

RE2/CS RE0/RD RE1/WR RD7:RD0 Note: Refer to Figure 14-1 for load conditions.

TABLE 14-7: PARALLEL SLAVE PORT REQUIREMENTS (PIC16C65B/74B)

Parameter Sym Characteristic Min Typ† Max Units Conditions No. 62* TdtV2wrH Data in valid before WR↑ or CS↑ (setup time) 20 — — ns 63* TwrH2dtI WR↑ or CS↑ to data–in invalid Standard 20 — — ns (hold time) Extended (LC) 35 — — ns 64 TrdL2dtV RD↓ and CS↓ to data–out valid — — 80 ns 65* TrdH2dtI RD↑ or CS↑ to data–out invalid 10 — 30 ns * These parameters are characterized but not tested. † Data in "Typ" column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. 1998 Microchip Technology Inc. Preliminary DS30605A-page 113, FIGURE 14-9: EXAMPLE SPI MASTER MODE TIMING (CKE = 0)

SS SCK

(CKP = 0) 71 72 78 79

SCK

(CKP = 1) 79 7880 SDO MSb BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN Refer to Figure 14-1 for load conditions. TABLE 14-8: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 0) Param. Symbol Characteristic Min Typ† Max Units Conditions No. 70 TssL2scH, SS↓ to SCK↓ or SCK↑ input TCY — — ns TssL2scL 71 TscH SCK input high time Continuous 1.25TCY + 30 — — ns 71A (slave mode) Single Byte 40 — — ns Note 1 72 TscL SCK input low time Continuous 1.25TCY + 30 — — ns 72A (slave mode) Single Byte 40 — — ns Note 1 73 TdiV2scH, Setup time of SDI data input to SCK edge 100 — — ns TdiV2scL 73A TB2B Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 — — ns Note 1 edge of Byte2 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — — ns TscL2diL 75 TdoR SDO data output rise time Standard — 10 25 ns Extended (LC) — 20 45 ns 76 TdoF SDO data output fall time — 10 25 ns 78 TscR SCK output rise time Standard — 10 25 ns (master mode) Extended (LC) — 20 45 ns 79 TscF SCK output fall time (master mode) — 10 25 ns 80 TscH2doV, SDO data output valid Standard — — 50 ns TscL2doV after SCK edge Extended (LC) — — 100 ns † Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Specification 73A is only required if specifications 71A and 72A are used. DS30605A-page 114 Preliminary 1998 Microchip Technology Inc., FIGURE 14-10: EXAMPLE SPI MASTER MODE TIMING (CKE = 1)

SS SCK

(CKP = 0) 71 72

SCK

(CKP = 1) SDO MSb BIT6 - - - - - -1 LSb 75, 76 SDI MSb IN BIT6 - - - -1 LSb IN Refer to Figure 14-1 for load conditions. TABLE 14-9: EXAMPLE SPI MODE REQUIREMENTS (MASTER MODE, CKE = 1) Param. Symbol Characteristic Min Typ† Max Units Conditions No. 71 TscH SCK input high time Continuous 1.25TCY + 30 — — ns 71A (slave mode) Single Byte 40 — — ns Note 1 72 TscL SCK input low time Continuous 1.25TCY + 30 — — ns 72A (slave mode) Single Byte 40 — — ns Note 1 73 TdiV2scH, Setup time of SDI data input to SCK 100 — — ns TdiV2scL edge 73A TB2B Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 — — ns Note 1 edge of Byte2 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — — ns TscL2diL 75 TdoR SDO data output rise Standard — 10 25 ns time Extended (LC) 20 45 ns 76 TdoF SDO data output fall time — 10 25 ns 78 TscR SCK output rise time Standard — 10 25 ns (master mode) Extended (LC) 20 45 ns 79 TscF SCK output fall time (master mode) — 10 25 ns 80 TscH2doV, SDO data output valid Standard — — 50 ns TscL2doV after SCK edge Extended (LC) — 100 ns 81 TdoV2scH, SDO data output setup to SCK edge TCY — — ns TdoV2scL † Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Specification 73A is only required if specifications 71A and 72A are used. 1998 Microchip Technology Inc. Preliminary DS30605A-page 115, FIGURE 14-11: EXAMPLE SPI SLAVE MODE TIMING (CKE = 0)

SS SCK

(CKP = 0) 83 71 72 78 79

SCK

(CKP = 1) 79 7880 SDO MSb BIT6 - - - - - -1 LSb 75, 76 77 SDI MSb IN BIT6 - - - -1 LSb IN Refer to Figure 14-1 for load conditions. TABLE 14-10: EXAMPLE SPI MODE REQUIREMENTS (SLAVE MODE TIMING (CKE = 0) Param. Symbol Characteristic Min Typ† Max Units Conditions No. 70 TssL2scH, SS↓ to SCK↓ or SCK↑ input TCY — — ns TssL2scL 71 TscH SCK input high time Continuous 1.25TCY + 30 — — ns 71A (slave mode) Single Byte 40 — — ns Note 1 72 TscL SCK input low time Continuous 1.25TCY + 30 — — ns 72A (slave mode) Single Byte 40 — — ns Note 1 73 TdiV2scH, Setup time of SDI data input to SCK edge 100 — — ns TdiV2scL 73A TB2B Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 — — ns Note 1 edge of Byte2 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — — ns TscL2diL 75 TdoR SDO data output rise time Standard — 10 25 ns Extended (LC) 20 45 ns 76 TdoF SDO data output fall time — 10 25 ns 77 TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns 78 TscR SCK output rise time Standard — 10 25 ns (master mode) Extended (LC) 20 45 ns 79 TscF SCK output fall time (master mode) — 10 25 ns 80 TscH2doV, SDO data output valid Standard — — 50 ns TscL2doV after SCK edge Extended (LC) — 100 ns 83 TscH2ssH, SS ↑ after SCK edge 1.5TCY + 40 — — ns TscL2ssH † Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Specification 73A is only required if specifications 71A and 72A are used. DS30605A-page 116 Preliminary 1998 Microchip Technology Inc., FIGURE 14-12: EXAMPLE SPI SLAVE MODE TIMING (CKE = 1)

SS

SCK 83 (CKP = 0) 71 72

SCK

(CKP = 1) SDO MSb BIT6 - - - - - -1 LSb 75, 76 77

SDI

MSb IN BIT6 - - - -1 LSb IN Refer to Figure 14-1 for load conditions. TABLE 14-11: EXAMPLE SPI SLAVE MODE REQUIREMENTS (CKE = 1) Param. Symbol Characteristic Min Typ† Max Units Conditions No. 70 TssL2scH, SS↓ to SCK↓ or SCK↑ input TCY — — ns TssL2scL 71 TscH SCK input high time Continuous 1.25TCY + 30 — — ns 71A (slave mode) Single Byte 40 — — ns Note 1 72 TscL SCK input low time Continuous 1.25TCY + 30 — — ns 72A (slave mode) Single Byte 40 — — ns Note 1 73A TB2B Last clock edge of Byte1 to the 1st clock 1.5TCY + 40 — — ns Note 1 edge of Byte2 74 TscH2diL, Hold time of SDI data input to SCK edge 100 — — ns TscL2diL 75 TdoR SDO data output rise Standard — 10 25 ns time Extended (LC) 20 45 ns 76 TdoF SDO data output fall time — 10 25 ns 77 TssH2doZ SS↑ to SDO output hi-impedance 10 — 50 ns 78 TscR SCK output rise time Standard — 10 25 ns (master mode) Extended (LC) — 20 45 ns 79 TscF SCK output fall time (master mode) — 10 25 ns 80 TscH2doV, SDO data output valid Standard — — 50 ns TscL2doV after SCK edge Extended (LC) — — 100 ns 82 TssL2doV SDO data output valid Standard — — 50 ns after SS↓ edge Extended (LC) — — 100 ns 83 TscH2ssH, SS ↑ after SCK edge 1.5TCY + 40 — — ns TscL2ssH † Data in “Typ” column is at 5V, 25˚C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: Specification 73A is only required if specifications 71A and 72A are used. 1998 Microchip Technology Inc. Preliminary DS30605A-page 117,

FIGURE 14-13: I2C BUS START/STOP BITS TIMING SCL

91 93 90 92

SDA

START STOP Condition Condition Note: Refer to Figure 14-1 for load conditions.

TABLE 14-12: I2C BUS START/STOP BITS REQUIREMENTS

Parameter Sym Characteristic Min Typ Max Units Conditions No. 90* TSU:STA START condition 100 kHz mode 4700 — — Only relevant for repeated START ns Setup time 400 kHz mode 600 — — condition 91* THD:STA START condition 100 kHz mode 4000 — — After this period the first clock ns Hold time 400 kHz mode 600 — — pulse is generated 92* TSU:STO STOP condition 100 kHz mode 4700 — — ns Setup time 400 kHz mode 600 — — 93 THD:STO STOP condition 100 kHz mode 4000 — — ns Hold time 400 kHz mode 600 — — * These parameters are characterized but not tested. DS30605A-page 118 Preliminary 1998 Microchip Technology Inc.,

FIGURE 14-14: I2C BUS DATA TIMING

103 100 102

SCL

106 107 91 92

SDA

In 109 109

SDA

Out Note: Refer to Figure 14-1 for load conditions.

TABLE 14-13: I2C BUS DATA REQUIREMENTS

Parameter Sym Characteristic Min Max Units Conditions No. 100* THIGH Clock high time 100 kHz mode 4.0 — µs Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 0.6 — µs Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 101* TLOW Clock low time 100 kHz mode 4.7 — µs Device must operate at a mini- mum of 1.5 MHz 400 kHz mode 1.3 — µs Device must operate at a mini- mum of 10 MHz SSP Module 1.5TCY — 102* TR SDA and SCL rise 100 kHz mode — 1000 ns time 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF 103* TF SDA and SCL fall time 100 kHz mode — 300 ns 400 kHz mode 20 + 0.1Cb 300 ns Cb is specified to be from 10-400 pF 90* TSU:STA START condition 100 kHz mode 4.7 — µs Only relevant for repeated setup time 400 kHz mode 0.6 — µs START condition 91* THD:STA START condition hold 100 kHz mode 4.0 — µs After this period the first clock time 400 kHz mode 0.6 — µs pulse is generated 106* THD:DAT Data input hold time 100 kHz mode 0 — ns 400 kHz mode 0 0.9 µs 107* TSU:DAT Data input setup time 100 kHz mode 250 — ns Note 2 400 kHz mode 100 — ns 92* TSU:STO STOP condition setup 100 kHz mode 4.7 — µs time 400 kHz mode 0.6 — µs 109* TAA Output valid from 100 kHz mode — 3500 ns Note 1 clock 400 kHz mode — — ns 110* TBUF Bus free time 100 kHz mode 4.7 — µs Time the bus must be free 400 kHz mode 1.3 — µs before a new transmission can start Cb Bus capacitive loading — 400 pF * These parameters are characterized but not tested. Note1: As a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions. 2: A fast-mode (400 kHz) I2C-bus device can be used in a standard-mode (100 kHz) I2C-bus system, but the requirement Tsu:DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line TR max.+tsu;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C bus specification) before the SCL line is released. 1998 Microchip Technology Inc. Preliminary DS30605A-page 119,

FIGURE 14-15: USART SYNCHRONOUS TRANSMISSION (MASTER/SLAVE) TIMING

RC6/TX/CK pin 121 121 RC7/RX/DT pin Note: Refer to Figure 14-1 for load conditions.

TABLE 14-14: USART SYNCHRONOUS TRANSMISSION REQUIREMENTS

Param Sym Characteristic Min Typ† Max Units Conditions No. 120* TckH2dtV SYNC XMIT (MASTER & SLAVE) Standard — — 80 ns Clock high to data out valid Extended (LC) — — 100 ns 121* Tckrf Clock out rise time and fall time Standard — — 45 ns (Master Mode) Extended (LC) — — 50 ns 122* Tdtrf Data out rise time and fall time Standard — — 45 ns Extended (LC) — — 50 ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested.

FIGURE 14-16: USART SYNCHRONOUS RECEIVE (MASTER/SLAVE) TIMING

RC6/TX/CK pin 125 RC7/RX/DT pin Note: Refer to Figure 14-1 for load conditions.

TABLE 14-15: USART SYNCHRONOUS RECEIVE REQUIREMENTS

Parameter Sym Characteristic Min Typ† Max Units Conditions No. 125* TdtV2ckL SYNC RCV (MASTER & SLAVE) Data setup before CK ↓ (DT setup time) 15 — — ns 126* TckL2dtl Data hold after CK ↓ (DT hold time) 15 — — ns * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. DS30605A-page 120 Preliminary 1998 Microchip Technology Inc.,

TABLE 14-16: A/D CONVERTER CHARACTERISTICS: PIC16C73B/74B-04 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16C73B/74B-20 (COMMERCIAL, INDUSTRIAL, EXTENDED) PIC16LC73B/74B-04 (COMMERCIAL, INDUSTRIAL)

Param Sym Characteristic Min Typ† Max Units Conditions No. A01 NR Resolution — — 8-bits bit VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A02 EABS Total Absolute error — — < ± 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A03 EIL Integral linearity error — — < ± 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A04 EDL Differential linearity error — — < ± 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A05 EFS Full scale error — — < ± 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A06 EOFF Offset error — — < ± 1 LSb VREF = VDD = 5.12V, VSS ≤ VAIN ≤ VREF A10 — Monotonicity — guaranteed — — VSS ≤ VAIN ≤ VREF A20 VREF Reference voltage 2.5V — VDD + 0.3 V A25 VAIN Analog input voltage VSS - 0.3 — VREF + 0.3 V A30 ZAIN Recommended impedance of — — 10.0 kΩ analog voltage source A40 IAD A/D conversion current Standard — 180 — µA Average current consump- (VDD) Extended (LC) — 90 — µA tion when A/D is on. (Note 1) A50 IREF VREF input current (Note 2) 10 — 1000 µA During VAIN acquisition. Based on differential of VHOLD to VAIN to charge CHOLD, see Section 10.1. — — 10 µA During A/D Conversion cycle * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. Note1: When A/D is off, it will not consume any current other than minor leakage current. The power-down current spec includes any such leakage from the A/D module. 2: VREF current is from RA3 pin or VDD pin, whichever is selected as reference input. 1998 Microchip Technology Inc. Preliminary DS30605A-page 121,

FIGURE 14-17: A/D CONVERSION TIMING

BSF ADCON0, GO 1 Tcy 134 (TOSC/2) (1) Q4 A/D CLK 132 A/D DATA76543210ADRES OLD_DATA NEW_DATA

ADIF

GO DONE SAMPLE SAMPLING STOPPED Note1: If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed.

TABLE 14-17: A/D CONVERSION REQUIREMENTS

Param Sym Characteristic Min Typ† Max Units Conditions No. 130 TAD A/D clock period Standard 1.6 — — µs TOSC based, VREF ≥ 3.0V Extended (LC) 2.0 — — µs TOSC based, VREF full range Standard 2.0 4.0 6.0 µs A/D RC Mode Extended (LC) 3.0 6.0 9.0 µs A/D RC Mode 131 TCNV Conversion time (not including S/H time) 11 — 11 TAD (Note 1) 132 TACQ Acquisition time Note 2 20 — µs 5* — — µs The minimum time is the amplifier settling time. This may be used if the "new" input voltage has not changed by more than 1 LSb (i.e., 20.0 mV @ 5.12V) from the last sampled voltage (as stated on CHOLD). 134 TGO Q4 to A/D clock start — TOSC/2 § — — If the A/D clock source is selected as RC, a time of TCY is added before the A/D clock starts. This allows the SLEEP instruction to be executed. 135 TSWC Switching from convert → sample time 1.5 § — — TAD * These parameters are characterized but not tested. † Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. § This specification ensured by design. Note1: ADRES register may be read on the following TCY cycle. 2: See Section 10.1 for min conditions. DS30605A-page 122 Preliminary 1998 Microchip Technology Inc., 15.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Graphs and Tables not available at this time. 1998 Microchip Technology Inc. DS30605A-page 123, NOTES: DS30605A-page 124 1998 Microchip Technology Inc., 16.0 PACKAGING INFORMATION 16.1 Package Marking Information 28-Lead PDIP (Skinny DIP) Example MMMMMMMMMMMM PIC16C73B-04/SP

XXXXXXXXXXXXXXX

AABBCDE 9817HAT 28-Lead CERDIP Windowed Example XXXXXXXXXXX PIC16C73B/JW

XXXXXXXXXXX

AABBCDE 9817CAT 28-Lead SOIC Example MMMMMMMMMMMMMMMM PIC16C73B-20/SO

XXXXXXXXXXXXXXXXXXXX

AABBCDE 9810/SAA 28-Lead SSOP Example XXXXXXXXXXXX PIC16C73B XXXXXXXXXXXX 20I/SS025 AABBCAE 9817SBP Legend: XX...X Microchip part number & customer specific information* AA Year code (last two digits of calendar year) BB Week code (week of January 1 is week ‘01’) C Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A., S = Tempe, Arizona, U.S.A. - 6” H = Tempe, Arizona, U.S.A. - 8” D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev# and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 1998 Microchip Technology Inc. DS30605A-page 125, Package Marking Information (Cont’d) 40-Lead PDIP Example MMMMMMMMMMMMMM PIC16C74B-04/P

XXXXXXXXXXXXXXXXXX

AABBCDE 9812SAA 40-Lead CERDIP Windowed Example

MMMMMMMMM PIC16C74B/JW XXXXXXXXXXX XXXXXXXXXXX AABBCDE 9805HAT

Legend: XX...X Microchip part number & customer specific information* AA Year code (last two digits of calendar year) BB Week code (week of January 1 is week ‘01’) C Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A., S = Tempe, Arizona, U.S.A. - 6” H = Tempe, Arizona, U.S.A. - 8” D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev# and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS30605A-page 126 1998 Microchip Technology Inc., Package Marking Information (Cont’d) 44-Lead TQFP Example MMMMMMMM PIC16C74B XXXXXXXXXX -20/PT

XXXXXXXXXX

AABBCDE 9811HAT 44-Lead MQFP Example MMMMMMMM PIC16C74B XXXXXXXXXX -20/PQ

XXXXXXXXXX

AABBCDE 9804SAT 44-Lead PLCC Example MMMMMMMM PIC16C74B XXXXXXXXXX -20/L

XXXXXXXXXX

AABBCDE 9803SAT Legend: XX...X Microchip part number & customer specific information* AA Year code (last two digits of calendar year) BB Week code (week of January 1 is week ‘01’) C Facility code of the plant at which wafer is manufactured C = Chandler, Arizona, U.S.A., S = Tempe, Arizona, U.S.A. - 6” H = Tempe, Arizona, U.S.A. - 8” D Mask revision number E Assembly code of the plant or country of origin in which part was assembled Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer specific information. * Standard OTP marking consists of Microchip part number, year code, week code, facility code, mask rev# and assembly code. For OTP marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. 1998 Microchip Technology Inc. DS30605A-page 127, 16.2 K04-070 28-Lead Skinny Plastic Dual In-line (SP) – 300 mil

E D

αn1E1 A1

A R

cLβA2 B1 eBBpUnits INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Row Spacing 0.300 7.62 Number of Pins n 28 28 Pitch p 0.100 2.54 Lower Lead Width B 0.016 0.019 0.022 0.41 0.48 0.56 Upper Lead Width B1† 0.040 0.053 0.065 1.02 1.33 1.65 Shoulder Radius R 0.000 0.005 0.010 0.00 0.13 0.25 Lead Thickness c 0.008 0.010 0.012 0.20 0.25 0.30 Top to Seating Plane A 0.140 0.150 0.160 3.56 3.81 4.06 Top of Lead to Seating Plane A1 0.070 0.090 0.110 1.78 2.29 2.79 Base to Seating Plane A2 0.015 0.020 0.025 0.38 0.51 0.64 Tip to Seating Plane L 0.125 0.130 0.135 3.18 3.30 3.43 Package Length D‡ 1.345 1.365 1.385 34.16 34.67 35.18 Molded Package Width E‡ 0.280 0.288 0.295 7.11 7.30 7.49 Radius to Radius Width E1 0.270 0.283 0.295 6.86 7.18 7.49 Overall Row Spacing eB 0.320 0.350 0.380 8.13 8.89 9.65 Mold Draft Angle Topα510 15 5 10 15 Mold Draft Angle Bottomβ510 15 5 10 15 * Controlling Parameter. † Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” DS30605A-page 128 1998 Microchip Technology Inc., 16.3 K04-080 28-Lead Ceramic Dual In-line with Window (JW) – 300 mil

E

W2Dn1W1 E1 A A1RcLB1 eB A2BpUnits INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Row Spacing 0.300 7.62 Number of Pins n 28 28 Pitch p 0.098 0.100 0.102 2.49 2.54 2.59 Lower Lead Width B 0.016 0.019 0.021 0.41 0.47 0.53 Upper Lead Width B1 0.050 0.058 0.065 1.27 1.46 1.65 Shoulder Radius R 0.010 0.013 0.015 0.25 0.32 0.38 Lead Thickness c 0.008 0.010 0.012 0.20 0.25 0.30 Top to Seating Plane A 0.170 0.183 0.195 4.32 4.64 4.95 Top of Lead to Seating Plane A1 0.107 0.125 0.143 2.72 3.18 3.63 Base to Seating Plane A2 0.015 0.023 0.030 0.00 0.57 0.76 Tip to Seating Plane L 0.135 0.140 0.145 3.43 3.56 3.68 Package Length D 1.430 1.458 1.485 36.32 37.02 37.72 Package Width E 0.285 0.290 0.295 7.24 7.37 7.49 Radius to Radius Width E1 0.255 0.270 0.285 6.48 6.86 7.24 Overall Row Spacing eB 0.345 0.385 0.425 8.76 9.78 10.80 Window Width W1 0.130 0.140 0.150 0.13 0.14 0.15 Window Length W2 0.290 0.300 0.310 0.29 0.3 0.31 * Controlling Parameter. 1998 Microchip Technology Inc. DS30605A-page 129, 16.4 K04-052 28-Lead Plastic Small Outline (SO) – Wide, 300 mil E1

E

p

D B

n1Xα45 ° L R2cAA1 R1φβL1 A2 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Pitch p 0.050 1.27 Number of Pins n 28 28 Overall Pack. Height A 0.093 0.099 0.104 2.36 2.50 2.64 Shoulder Height A1 0.048 0.058 0.068 1.22 1.47 1.73 Standoff A2 0.004 0.008 0.011 0.10 0.19 0.28 Molded Package Length D‡ 0.700 0.706 0.712 17.78 17.93 18.08 Molded Package Width E‡ 0.292 0.296 0.299 7.42 7.51 7.59 Outside Dimension E1 0.394 0.407 0.419 10.01 10.33 10.64 Chamfer Distance X 0.010 0.020 0.029 0.25 0.50 0.74 Shoulder Radius R1 0.005 0.005 0.010 0.13 0.13 0.25 Gull Wing Radius R2 0.005 0.005 0.010 0.13 0.13 0.25 Foot Length L 0.011 0.016 0.021 0.28 0.41 0.53 Foot Angleφ048048Radius Centerline L1 0.010 0.015 0.020 0.25 0.38 0.51 Lead Thickness c 0.009 0.011 0.012 0.23 0.27 0.30 Lower Lead Width B† 0.014 0.017 0.019 0.36 0.42 0.48 Mold Draft Angle Topα012 15 0 12 15 Mold Draft Angle Bottomβ012 15 0 12 15 * Controlling Parameter. † Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” DS30605A-page 130 1998 Microchip Technology Inc., 16.5 K04-073 28-Lead Plastic Shrink Small Outline (SS) – 5.30 mm E1

E

p

D B

n1α

L A

R2 c A1 R1 φ A2 β L1 Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Pitch p 0.026 0.65 Number of Pins n 28 28 Overall Pack. Height A 0.068 0.073 0.078 1.73 1.86 1.99 Shoulder Height A1 0.026 0.036 0.046 0.66 0.91 1.17 Standoff A2 0.002 0.005 0.008 0.05 0.13 0.21 Molded Package Length D‡ 0.396 0.402 0.407 10.07 10.20 10.33 Molded Package Width E‡ 0.205 0.208 0.212 5.20 5.29 5.38 Outside Dimension E1 0.301 0.306 0.311 7.65 7.78 7.90 Shoulder Radius R1 0.005 0.005 0.010 0.13 0.13 0.25 Gull Wing Radius R2 0.005 0.005 0.010 0.13 0.13 0.25 Foot Length L 0.015 0.020 0.025 0.38 0.51 0.64 Foot Angleφ048048Radius Centerline L1 0.000 0.005 0.010 0.00 0.13 0.25 Lead Thickness c 0.005 0.007 0.009 0.13 0.18 0.22 Lower Lead Width B† 0.010 0.012 0.015 0.25 0.32 0.38 Mold Draft Angle Topα05100510 Mold Draft Angle Bottomβ05100510 * Controlling Parameter. † Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” 1998 Microchip Technology Inc. DS30605A-page 131, 16.6 K04-016 40-Lead Plastic Dual In-line (P) – 600 mil

E D

2αn1E1 A1

A R

cLβB1A2 eBBpUnits INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Row Spacing 0.600 15.24 Number of Pins n 40 40 Pitch p 0.100 2.54 Lower Lead Width B 0.016 0.018 0.020 0.41 0.46 0.51 Upper Lead Width B1† 0.045 0.050 0.055 1.14 1.27 1.40 Shoulder Radius R 0.000 0.005 0.010 0.00 0.13 0.25 Lead Thickness c 0.009 0.010 0.011 0.23 0.25 0.28 Top to Seating Plane A 0.110 0.160 0.160 2.79 4.06 4.06 Top of Lead to Seating Plane A1 0.073 0.093 0.113 1.85 2.36 2.87 Base to Seating Plane A2 0.020 0.020 0.040 0.51 0.51 1.02 Tip to Seating Plane L 0.125 0.130 0.135 3.18 3.30 3.43 Package Length D‡ 2.013 2.018 2.023 51.13 51.26 51.38 Molded Package Width E‡ 0.530 0.535 0.540 13.46 13.59 13.72 Radius to Radius Width E1 0.545 0.565 0.585 13.84 14.35 14.86 Overall Row Spacing eB 0.630 0.610 0.670 16.00 15.49 17.02 Mold Draft Angle Topα510 15 5 10 15 Mold Draft Angle Bottomβ510 15 5 10 15 * Controlling Parameter. † Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” DS30605A-page 132 1998 Microchip Technology Inc., 16.7 K04-014 40-Lead Ceramic Dual In-line with Window (JW) – 600 mil

E W D

n 1 E1 A1

A

RcLeB B1 A2BpUnits INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX PCB Row Spacing 0.600 15.24 Number of Pins n 40 40 Pitch p 0.098 0.100 0.102 2.49 2.54 2.59 Lower Lead Width B 0.016 0.020 0.023 0.41 0.50 0.58 Upper Lead Width B1 0.050 0.053 0.055 1.27 1.33 1.40 Shoulder Radius R 0.000 0.005 0.010 0.00 0.13 0.25 Lead Thickness c 0.008 0.011 0.014 0.20 0.28 0.36 Top to Seating Plane A 0.190 0.205 0.220 4.83 5.21 5.59 Top of Lead to Seating Plane A1 0.117 0.135 0.153 2.97 3.43 3.89 Base to Seating Plane A2 0.030 0.045 0.060 0.00 1.14 1.52 Tip to Seating Plane L 0.135 0.140 0.145 3.43 3.56 3.68 Package Length D 2.040 2.050 2.060 51.82 52.07 52.32 Package Width E 0.514 0.520 0.526 13.06 13.21 13.36 Radius to Radius Width E1 0.560 0.580 0.600 14.22 14.73 15.24 Overall Row Spacing eB 0.610 0.660 0.710 15.49 16.76 18.03 Window Diameter W 0.340 0.350 0.360 8.64 8.89 9.14 * Controlling Parameter. 1998 Microchip Technology Inc. DS30605A-page 133, 16.8 K04-076 44-Lead Plastic Thin Quad Flatpack (PT) 10x10x1 mm Body, 1.0/0.1 mm Lead Form E1

E

# leads = n1pDD1

B

nXx45° L αA R2 c R1φβA1L1 A2 Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Pitch p 0.031 0.80 Number of Pins n 44 44 Pins along Width n1 11 11 Overall Pack. Height A 0.039 0.043 0.047 1.00 1.10 1.20 Shoulder Height A1 0.015 0.025 0.035 0.38 0.64 0.89 Standoff A2 0.002 0.004 0.006 0.05 0.10 0.15 Shoulder Radius R1 0.003 0.003 0.010 0.08 0.08 0.25 Gull Wing Radius R2 0.003 0.006 0.008 0.08 0.14 0.20 Foot Length L 0.005 0.010 0.015 0.13 0.25 0.38 Foot Angleφ03.5703.5 7 Radius Centerline L1 0.003 0.008 0.013 0.08 0.20 0.33 Lead Thickness c 0.004 0.006 0.008 0.09 0.15 0.20 Lower Lead Width B† 0.012 0.015 0.018 0.30 0.38 0.45 Outside Tip Length D1 0.463 0.472 0.482 11.75 12.00 12.25 Outside Tip Width E1 0.463 0.472 0.482 11.75 12.00 12.25 Molded Pack. Length D‡ 0.390 0.394 0.398 9.90 10.00 10.10 Molded Pack. Width E‡ 0.390 0.394 0.398 9.90 10.00 10.10 Pin 1 Corner Chamfer X 0.025 0.035 0.045 0.64 0.89 1.14 Mold Draft Angle Topα510 15 5 10 15 Mold Draft Angle Bottomβ512 15 5 12 15 * Controlling Parameter. † Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” JEDEC equivalent: MS-026 ACB DS30605A-page 134 1998 Microchip Technology Inc., 16.9 K04-071 44-Lead Plastic Quad Flatpack (PQ) 10x10x2 mm Body, 1.6/0.15 mm Lead Form E1

E

# leads = n1pDD1

B

nXx45° α

L

R2cAR1βφA1 L1 A2 Units INCHES MILLIMETERS* Dimension Limits MIN NOM MAX MIN NOM MAX Pitch p 0.031 0.80 Number of Pins n 44 44 Pins along Width n1 11 11 Overall Pack. Height A 0.079 0.086 0.093 2.00 2.18 2.35 Shoulder Height A1 0.032 0.044 0.056 0.81 1.11 1.41 Standoff A2 0.002 0.006 0.010 0.05 0.15 0.25 Shoulder Radius R1 0.005 0.005 0.010 0.13 0.13 0.25 Gull Wing Radius R2 0.005 0.012 0.015 0.13 0.30 0.38 Foot Length L 0.015 0.020 0.025 0.38 0.51 0.64 Foot Angleφ03.5703.5 7 Radius Centerline L1 0.011 0.016 0.021 0.28 0.41 0.53 Lead Thickness c 0.005 0.007 0.009 0.13 0.18 0.23 Lower Lead Width B† 0.012 0.015 0.018 0.30 0.37 0.45 Outside Tip Length D1 0.510 0.520 0.530 12.95 13.20 13.45 Outside Tip Width E1 0.510 0.520 0.530 12.95 13.20 13.45 Molded Pack. Length D‡ 0.390 0.394 0.398 9.90 10.00 10.10 Molded Pack. Width E‡ 0.390 0.394 0.398 9.90 10.00 10.10 Pin 1 Corner Chamfer X 0.025 0.035 0.045 0.635 0.89 1.143 Mold Draft Angle Topα510 15 5 10 15 Mold Draft Angle Bottomβ512 15 5 12 15 * Controlling Parameter. † Dimension “B” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010” (0.254 mm) per side or 0.020” (0.508 mm) more than dimensions “D” or “E.” JEDEC equivalent: MS-022 AB 1998 Microchip Technology Inc. DS30605A-page 135, 16.10 K04-048 44-Lead Plastic Leaded Chip Carrier (L) – Square E1

E

# leads = n1 D D1n12αCH2 x 45° CH1 x 45° A3 R1 L

A

A1 35° B1 c R2 β BA2 p E2 D2 Units INCHES* MILLIMETERS Dimension Limits MIN NOM MAX MIN NOM MAX Number of Pins n 44 44 Pitch p 0.050 1.27 Overall Pack. Height A 0.165 0.173 0.180 4.19 4.38 4.57 Shoulder Height A1 0.095 0.103 0.110 2.41 2.60 2.79 Standoff A2 0.015 0.023 0.030 0.38 0.57 0.76 Side 1 Chamfer Dim. A3 0.024 0.029 0.034 0.61 0.74 0.86 Corner Chamfer (1) CH1 0.040 0.045 0.050 1.02 1.14 1.27 Corner Chamfer (other) CH2 0.000 0.005 0.010 0.00 0.13 0.25 Overall Pack. Width E1 0.685 0.690 0.695 17.40 17.53 17.65 Overall Pack. Length D1 0.685 0.690 0.695 17.40 17.53 17.65 Molded Pack. Width E‡ 0.650 0.653 0.656 16.51 16.59 16.66 Molded Pack. Length D‡ 0.650 0.653 0.656 16.51 16.59 16.66 Footprint Width E2 0.610 0.620 0.630 15.49 15.75 16.00 Footprint Length D2 0.610 0.620 0.630 15.49 15.75 16.00 Pins along Width n1 11 11 Lead Thickness c 0.008 0.010 0.012 0.20 0.25 0.30 Upper Lead Width B1† 0.026 0.029 0.032 0.66 0.74 0.81 Lower Lead Width B 0.015 0.018 0.021 0.38 0.46 0.53 Upper Lead Length L 0.050 0.058 0.065 1.27 1.46 1.65 Shoulder Inside Radius R1 0.003 0.005 0.010 0.08 0.13 0.25 J-Bend Inside Radius R2 0.015 0.025 0.035 0.38 0.64 0.89 Mold Draft Angle Topα05100510 Mold Draft Angle Bottomβ05100510 * Controlling Parameter. † Dimension “B1” does not include dam-bar protrusions. Dam-bar protrusions shall not exceed 0.003” (0.076 mm) per side or 0.006” (0.152 mm) more than dimension “B1.” ‡ Dimensions “D” and “E” do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010" (0.254 mm) per side or 0.020" (0.508 mm) more than dimensions “D” or “E.” JEDEC equivalent: MO-047 AC DS30605A-page 136 1998 Microchip Technology Inc.,

APPENDIX A: REVISION HISTORY

Version Date Revision Description A 7/98 This is a new data sheet. However, the devices described in this data sheet are the upgrades to the devices found in the PIC16C6X Data Sheet, DS30234D, and the PIC16C7X Data Sheet, DS30390E.

APPENDIX B: DEVICE DIFFERENCES

The differences between the devices in this data sheet are listed in Table B-1. TABLE B-1: DEVICE DIFFERENCES Difference PIC16C63A PIC16C65B PIC16C73B PIC16C74B A/D no no 5 channels, 8 bits 8 channels, 8 bits Parallel Slave Port no yes no yes Packages 28-pin PDIP, 28-pin 40-pin PDIP, 40-pin 28-pin PDIP, 28-pin 40-pin PDIP, 40-pin windowed CERDIP, windowed CERDIP, windowed CERDIP, windowed CERDIP, 28-pin SOIC, 28-pin 44-pin TQFP, 44-pin 28-pin SOIC, 28-pin 44-pin TQFP, 44-pin SSOP MQFP, 44-pin PLCC SSOP MQFP, 44-pin PLCC

APPENDIX C: CONVERSION CONSIDERATIONS

Considerations for converting from previous versions of devices to the ones listed in this data sheet are listed in Table C-1. TABLE C-1: CONVERSION CONSIDERATIONS Difference PIC16C63/65A/73A/74A PIC16C63A/65B/73B/74B Voltage Range 2.5V - 6.0V 2.5V - 5.5V SSP module single mode SPI 4-mode SPI SSP module Can only transmit one word in SPI mode N/A of enhanced SSP. CCP module CCP does not reset TMR1 when in special N/A event trigger mode. USART module USART receiver errata in BRGH=1 mode. N/A Timer1 module Writing to TMR1L register can cause over- N/A flow in TMR1H register. 1998 Microchip Technology Inc. DS30605A-page 137,

APPENDIX D: MIGRATION FROM 18. Brown-out protection circuitry has been added. BASELINE TO Controlled by configuration word bit BODEN.

Brown-out reset ensures the device is placed in

MIDRANGE DEVICES a reset condition if VDD dips below a fixed set-

This section discusses how to migrate from a baseline point. device (i.e., PIC16C5X) to a midrange device (i.e., To convert code written for PIC16C5X to PIC16CXXX, PIC16CXXX). the user should take the following steps: The following are the list of modifications over the 1. Remove any program memory page select PIC16C5X microcontroller family: operations (PA2, PA1, PA0 bits) for CALL, GOTO. 1. Instruction word length is increased to 14-bits. 2. Revisit any computed jump operations (write to This allows larger page sizes both in program PC or add to PC, etc.) to make sure page bits memory (2K now as opposed to 512 before) and are set properly under the new scheme. register file (128 bytes now versus 32 bytes 3. Eliminate any data memory page switching. before). Redefine data variables to reallocate them. 2. A PC high latch register (PCLATH) is added to 4. Verify all writes to STATUS, OPTION, and FSR handle program memory paging. Bits PA2, PA1, registers since these have changed. PA0 are removed from STATUS register. 5. Change reset vector to 0000h. 3. Data memory paging is redefined slightly. STATUS register is modified. 4. Four new instructions have been added: RETURN, RETFIE, ADDLW, and SUBLW. Two instructions TRIS and OPTION are being phased out although they are kept for compati- bility with PIC16C5X. 5. OPTION and TRIS registers are made address- able. 6. Interrupt capability is added. Interrupt vector is at 0004h. 7. Stack size is increased to 8 deep. 8. Reset vector is changed to 0000h. 9. Reset of all registers is revisited. Five different reset (and wake-up) types are recognized. Reg- isters are reset differently. 10. Wake up from SLEEP through interrupt is added. 11. Two separate timers, Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) are included for more reliable power-up. These tim- ers are invoked selectively to avoid unnecessary delays on power-up and wake-up. 12. PORTB has weak pull-ups and interrupt on change feature. 13. T0CKI pin is also a port pin (RA4) now. 14. FSR is made a full eight bit register. 15. “In-circuit serial programming” is made possible. The user can program PIC16CXX devices using only five pins: VDD, VSS, MCLR/VPP, RB6 (clock) and RB7 (data in/out). 16. PCON status register is added with a Power-on Reset status bit (POR). 17. Code protection scheme is enhanced such that portions of the program memory can be pro- tected, while the remainder is unprotected. DS30605A-page 138 1998 Microchip Technology Inc.,

APPENDIX E: BIT/REGISTER CROSS- T0IE ... INTCON<5>

REFERENCE LIST T0IF ... INTCON<2>T0SE ... OPTION_REG<4> ADCS1:ADCS0 ...ADCON0<7:6> T1CKPS1:T1CKPS0 ... T1CON<5:4> ADIE ...PIE1<6> T1OSCEN ... T1CON<3> ADIF ...PIR1<6> T1SYNC ... T1CON<2> ADON ...ADCON0<0> T2CKPS1:T2CKPS0 ... T2CON<1:0> BF ...SSPSTAT<0> TMR1CS ... T1CON<1> BOR ...PCON<0> TMR1IE ... PIE1<0> BRGH ...TXSTA<2> TMR1IF ... PIR1<0> C ...STATUS<0> TMR1ON ... T1CON<0> CCP1IE ...PIE1<2> TMR2IE ... PIE1<1> CCP1IF ...PIR1<2> TMR2IF ... PIR1<1> CCP1M3:CCP1M0 ...CCP1CON<3:0> TMR2ON ... T2CON<2> CCP1X:CCP1Y ...CCP1CON<5:4> TO ... STATUS<4> CCP2IE ...PIE2<0> TOUTPS3:TOUTPS0 ... T2CON<6:3> CCP2IF ...PIR2<0> TRMT ... TXSTA<1> CCP2M3:CCP2M0 ...CCP2CON<3:0> TX9 ... TXSTA<6> CCP2X:CCP2Y ...CCP2CON<5:4> TX9D ... TXSTA<0> CHS2:CHS0 ...ADCON0<5:3> TXEN ... TXSTA<5> CKE ...SSPSTAT<6> TXIE ... PIE1<4> CKP ...SSPCON<4> TXIF ... PIR1<4> CREN ...RCSTA<4> UA ... SSPSTAT<1> CSRC ...TXSTA<7> WCOL ... SSPCON<7> D/A ...SSPSTAT<5> Z ... STATUS<2> DC ...STATUS<1> FERR ...RCSTA<2> GIE ...INTCON<7> GO/DONE ...ADCON0<2> IBF ...TRISE<7> IBOV ...TRISE<5> INTE ...INTCON<4> INTEDG ...OPTION_REG<6> INTF ...INTCON<1> IRP ...STATUS<7> OBF ...TRISE<6> OERR ...RCSTA<1> P ...SSPSTAT<4> PCFG2:PCFG0 ...ADCON1<2:0> PD ...STATUS<3> PEIE ...INTCON<6> POR ...PCON<1> PS2:PS0 ...OPTION_REG<2:0> PSA ...OPTION_REG<3> PSPIE ...PIE1<7> PSPIF ...PIR1<7> PSPMODE ...TRISE<4> R/W ...SSPSTAT<2> RBIE ...INTCON<3> RBIF ...INTCON<0> RBPU ...OPTION_REG<7> RCIE ...PIE1<5> RCIF ...PIR1<5> RP1:RP0 ...STATUS<6:5> RX9 ...RCSTA<6> RX9D ...RCSTA<0> S ...SSPSTAT<3> SMP ...SSPSTAT<7> SPEN ...RCSTA<7> SREN ...RCSTA<5> SSPEN ...SSPCON<5> SSPIE ...PIE1<3> SSPIF ...PIR1<3> SSPM3:SSPM0 ...SSPCON<3:0> SSPOV ...SSPCON<6> SYNC ...TXSTA<4> T0CS ...OPTION_REG<5> 1998 Microchip Technology Inc. DS30605A-page 139, NOTES: DS30605A-page 140 1998 Microchip Technology Inc.,

INDEX A

A/D ... 75 A/D Converter Enable (ADIE Bit) ... 18 A/D Converter Flag (ADIF Bit) ... 19, 77 A/D Converter Interrupt, Configuring ... 77 ADCON0 Register... 13, 75 ADCON1 Register... 14, 75, 76 ADRES Register ... 13, 75, 77 Analog Port Pins ... 7, 8, 9, 34, 35 Analog Port Pins, Configuring... 79 Block Diagram... 77 Block Diagram, Analog Input Model... 78 Channel Select (CHS2:CHS0 Bits) ... 75 Clock Select (ADCS1:ADCS0 Bits)... 75 Configuring the Module... 77 Conversion Clock (TAD) ... 79 Conversion Status (GO/DONE Bit) ... 75, 77 Conversions ... 80 Converter Characteristics ... 121 Module On/Off (ADON Bit)... 75 Port Configuration Control (PCFG2:PCFG0 Bits) ... 76 Sampling Requirements... 78 Special Event Trigger (CCP)... 47, 80 Timing Diagram... 122 Absolute Maximum Ratings ... 101 ADCON0 Register... 13, 75 ADCS1:ADCS0 Bits ... 75 ADON Bit ... 75 CHS2:CHS0 Bits... 75 GO/DONE Bit... 75, 77 ADCON1 Register... 14, 75, 76 PCFG2:PCFG0 Bits ... 76 ADRES Register ... 13, 75, 77 Architecture PIC16C63A/PIC16C73B Block Diagram... 5 PIC16C65B/PIC16C74B Block Diagram... 6 Assembler MPASM Assembler... 98

B

Banking, Data Memory ... 11, 15 Brown-out Reset (BOR) ... 81, 83, 85, 86, 87 BOR Enable (BODEN Bit)... 81 BOR Status (BOR Bit)... 22 Timing Diagram... 110

C

Capture (CCP Module) ... 46 Block Diagram... 46 CCP Pin Configuration... 46 CCPR1H:CCPR1L Registers... 46 Changing Between Capture Prescalers... 46 Software Interrupt ... 46 Timer1 Mode Selection ... 46 Capture/Compare/PWM (CCP)... 45 CCP1 ... 45 CCP1CON Register... 13, 45 CCPR1H Register... 13, 45 CCPR1L Register ... 13, 45 Enable (CCP1IE Bit) ... 18 Flag (CCP1IF Bit) ... 19 RC2/CCP1 Pin... 7, 9 CCP2 ... 45 CCP2CON Register... 13, 45 CCPR2H Register... 13, 45 CCPR2L Register ... 13, 45 Enable (CCP2IE Bit) ... 20 1998 Microchip Technology Inc. Flag (CCP2IF Bit) ... 21 RC1/T1OSI/CCP2 Pin ... 7, 9 Interaction of Two CCP Modules... 45 Timer Resources ... 45 Timing Diagram ... 112 CCP1CON Register... 45 CCP1M3:CCP1M0 Bits ... 45 CCP1X:CCP1Y Bits... 45 CCP2CON Register... 45 CCP2M3:CCP2M0 Bits ... 45 CCP2X:CCP2Y Bits... 45 Code Protection... 81, 94 CP1:CP0 Bits... 81 Compare (CCP Module) ... 47 Block Diagram ... 47 CCP Pin Configuration ... 47 CCPR1H:CCPR1L Registers ... 47 Software Interrupt ... 47 Special Event Trigger ... 41, 47, 80 Timer1 Mode Selection... 47 Configuration Bits ... 81 Conversion Considerations ... 137

D

Data Memory ... 11 Bank Select (RP1:RP0 Bits) ... 11, 15 General Purpose Registers ... 11 Register File Map ... 12 Special Function Registers... 12, 13 DC Characteristics... 102, 104 Development Support ... 97 Development Tools... 97 Device Differences ... 137 Direct Addressing ... 24

E

Electrical Characteristics ... 101 Errata...4 External Power-on Reset Circuit ... 85

F

Firmware Instructions ... 95 ftp site ... 147 Fuzzy Logic Dev. System (fuzzyTECH-MP) ... 99

I

I/O Ports ... 25 I2C (SSP Module) ... 56 ACK Pulse ... 56, 57, 58, 59, 60 Addressing... 57 Block Diagram ... 56 Buffer Full Status (BF Bit)... 52 Clock Polarity Select (CKP Bit)... 53 Data/Address (D/A Bit) ... 52 Master Mode... 60 Mode Select (SSPM3:SSPM0 Bits)... 53 Multi-Master Mode... 60 Read/Write Bit Information (R/W Bit)... 52, 57, 58, 59 Receive Overflow Indicator (SSPOV Bit)... 53 Reception ... 58 Reception Timing Diagram... 58 Serial Clock (RC3/SCK/SCL) ... 59 Slave Mode... 56 Start (S Bit) ... 52, 60 Stop (P Bit) ... 52, 60 Synchronous Serial Port Enable (SSPEN Bit)... 53 Timing Diagram, Data... 119 Timing Diagram, Start/Stop Bits ... 118 Transmission ... 59 Update Address (UA Bit) ... 52 ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ... 97 DS30605A-page 141, ID Locations ... 81, 94 In-Circuit Serial Programming (ICSP) ... 81, 94 Indirect Addressing ... 24 FSR Register ... 11, 13, 24 INDF Register ... 13 Instruction Format ... 95 Instruction Set ... 95 Summary Table... 96 INTCON Register ... 13, 17 GIE Bit... 17 INTE Bit... 17 INTF Bit ... 17 PEIE Bit... 17 RBIE Bit ... 17 RBIF Bit... 17, 27 T0IE Bit ... 17 T0IF Bit ... 17 Interrupt Sources... 81, 90 A/D Conversion Complete ... 77 Block Diagram... 90 Capture Complete (CCP)... 46 Compare Complete (CCP)... 47 Interrupt on Change (RB7:RB4 )... 27 RB0/INT Pin, External ... 7, 8, 91 SSP Receive/Transmit Complete ... 51 TMR0 Overflow ... 38, 91 TMR1 Overflow ... 39, 41 TMR2 to PR2 Match ... 44 TMR2 to PR2 Match (PWM) ... 43, 48 USART Receive/Transmit Complete ... 61 Interrupts, Context Saving During ... 91 Interrupts, Enable Bits A/D Converter Enable (ADIE Bit) ... 18 CCP1 Enable (CCP1IE Bit)... 18, 46 CCP2 Enable (CCP2IE Bit)... 20 Global Interrupt Enable (GIE Bit) ... 17, 90 Interrupt on Change (RB7:RB4) Enable (RBIE Bit) ... 17, 91 Peripheral Interrupt Enable (PEIE Bit) ... 17 PSP Read/Write Enable (PSPIE Bit) ... 18 RB0/INT Enable (INTE Bit) ... 17 SSP Enable (SSPIE Bit) ... 18 TMR0 Overflow Enable (T0IE Bit)... 17 TMR1 Overflow Enable (TMR1IE Bit) ... 18 TMR2 to PR2 Match Enable (TMR2IE Bit) ... 18 USART Receive Enable (RCIE Bit) ... 18 USART Transmit Enable (TXIE Bit) ... 18 Interrupts, Flag Bits A/D Converter Flag (ADIF Bit) ... 19, 77 CCP1 Flag (CCP1IF Bit) ... 19, 46, 47 CCP2 Flag (CCP2IF Bit) ... 21 Interrupt on Change (RB7:RB4) Flag (RBIF Bit) ... 17, 27, 91 PSP Read/Write Flag (PSPIF Bit) ... 19 RB0/INT Flag (INTF Bit)... 17 SSP Flag (SSPIF Bit) ... 19 TMR0 Overflow Flag (T0IF Bit) ... 17, 91 TMR1 Overflow Flag (TMR1IF Bit) ... 19 TMR2 to PR2 Match Flag (TMR2IF Bit) ... 19 USART Receive Flag (RCIF Bit) ... 19 USART Transmit Flag (TXIE Bit) ... 19

K

KeeLoq Evaluation and Programming Tools... 99

M

Master Clear (MCLR) ... 7, 8 MCLR Reset, Normal Operation ... 83, 86, 87 MCLR Reset, SLEEP... 83, 86, 87 DS30605A-page 142 Memory Organization Data Memory ... 11 Program Memory... 11 MP-DriveWay™ - Application Code Generator ... 99 MPLAB C ... 99 MPLAB Integrated Development Environment Software ... 98

O

On-Line Support ... 147 OPCODE Field Descriptions... 95 OPTION_REG Register... 14, 16 INTEDG Bit ... 16 PS2:PS0 Bits ... 16, 37 PSA Bit ... 16, 37 RBPU Bit ... 16 T0CS Bit ... 16, 37 T0SE Bit ... 16, 37 OSC1/CLKIN Pin ... 7, 8 OSC2/CLKOUT Pin ... 7, 8 Oscillator Configuration ... 81, 82 HS... 82, 86 LP ... 82, 86 RC ... 82, 83, 86 Selection (FOSC1:FOSC0 Bits) ... 81 XT ... 82, 86 Oscillator, Timer1... 39, 41 Oscillator, WDT... 92

P

Packaging ... 125 Paging, Program Memory... 11, 23 Parallel Slave Port (PSP)... 9, 31, 35 Block Diagram ... 35 RE0/RD/AN5 Pin ... 9, 34, 35 RE1/WR/AN6 Pin ... 9, 34, 35 RE2/CS/AN7 Pin ... 9, 34, 35 Read Waveforms... 36 Read/Write Enable (PSPIE Bit) ... 18 Read/Write Flag (PSPIF Bit)... 19 Select (PSPMODE Bit) ... 31, 33, 35 Timing Diagram ... 113 Write Waveforms ... 35 PCON Register ... 22, 86 BOR Bit... 22 POR Bit... 22 PICDEM-1 Low-Cost PICmicro Demo Board ... 98 PICDEM-2 Low-Cost PIC16CXX Demo Board... 98 PICDEM-3 Low-Cost PIC16CXXX Demo Board ... 98 PICMASTER In-Circuit Emulator ... 97 PICSTART Plus Entry Level Development System... 97 PIE1 Register... 14, 18 ADIE Bit ... 18 CCP1IE Bit ... 18 PSPIE Bit ... 18 RCIE Bit ... 18 SSPIE Bit ... 18 TMR1IE Bit ... 18 TMR2IE Bit ... 18 TXIE Bit ... 18 PIE2 Register... 14, 20 CCP2IE Bit ... 20 Pinout Descriptions PIC16C63A/PIC16C73B... 7 PIC16C65B/PIC16C74B... 8 PIR1 Register ... 13, 19 ADIF Bit ... 19 CCP1IF Bit... 19 PSPIF Bit ... 19 1998 Microchip Technology Inc., RCIF Bit ... 19 SSPIF Bit ... 19 TMR1IF Bit... 19 TMR2IF Bit... 19 TXIF Bit ... 19 PIR2 Register... 13, 21 CCP2IF Bit ... 21 Pointer, FSR ... 24 PORTA... 7, 8 Analog Port Pins ... 7, 8 Initialization ... 25 PORTA Register ... 13, 25 RA3:RA0 and RA5 Port Pins ... 25 RA4/T0CKI Pin... 7, 8, 25 RA5/SS/AN4 Pin ... 7, 8, 54 TRISA Register ... 14, 25 PORTB... 7, 8 Initialization ... 27 PORTB Register ... 13, 27 Pull-up Enable (RBPU Bit) ... 16 RB0/INT Edge Select (INTEDG Bit)... 16 RB0/INT Pin, External... 7, 8, 91 RB3:RB0 Port Pins ... 27 RB7:RB4 Interrupt on Change... 91 RB7:RB4 Interrupt on Change Enable (RBIE Bit) ... 17, 91 RB7:RB4 Interrupt on Change Flag (RBIF Bit) ... 17, 27, 91 RB7:RB4 Port Pins ... 27 TRISB Register ... 14, 27 PORTC ... 7, 9 Block Diagram... 29 Initialization ... 29 PORTC Register ... 13, 29 RC0/T1OSO/T1CKI Pin ... 7, 9 RC1/T1OSI/CCP2 Pin... 7, 9 RC2/CCP1 Pin ... 7, 9 RC3/SCK/SCL Pin ... 7, 9, 54, 59 RC4/SDI/SDA Pin ... 7, 9, 54 RC5/SDO Pin... 7, 9, 54 RC6/TX/CK Pin ... 7, 9, 62 RC7/RX/DT Pin... 7, 9, 62, 63 TRISC Register... 14, 29, 61 PORTD ... 9, 35 Block Diagram... 31 Parallel Slave Port (PSP) Function ... 31 PORTD Register ... 13, 31 TRISD Register... 14, 31 PORTE... 9 Analog Port Pins ... 9, 34, 35 Block Diagram... 33 Input Buffer Full Status (IBF Bit) ... 33 Input Buffer Overflow (IBOV Bit) ... 33 Output Buffer Full Status (OBF Bit)... 33 PORTE Register ... 13, 33 PSP Mode Select (PSPMODE Bit) ... 31, 33, 35 RE0/RD/AN5 Pin... 9, 34, 35 RE1/WR/AN6 Pin... 9, 34, 35 RE2/CS/AN7 Pin... 9, 34, 35 TRISE Register ... 14, 33 Postscaler, Timer2 Select (TOUTPS3:TOUTPS0 Bits) ... 43 Postscaler, WDT ... 37 Assignment (PSA Bit) ... 16, 37 Block Diagram... 38 Rate Select (PS2:PS0 Bits) ... 16, 37 Switching Between Timer0 and WDT ... 38 1998 Microchip Technology Inc. Power-on Reset (POR)... 81, 83, 85, 86, 87 Oscillator Start-up Timer (OST)... 81, 85 POR Status (POR Bit) ... 22 Power Control (PCON) Register... 86 Power-down (PD Bit) ... 15, 83 Power-on Reset Circuit, External ... 85 Power-up Timer (PWRT) ... 81, 85 PWRT Enable (PWRTE Bit) ... 81 Time-out (TO Bit)... 15, 83 Time-out Sequence ... 86 Time-out Sequence on Power-up... 88, 89 Timing Diagram ... 110 Prescaler, Capture... 46 Prescaler, Timer0 ... 37 Assignment (PSA Bit) ... 16, 37 Block Diagram ... 38 Rate Select (PS2:PS0 Bits) ... 16, 37 Switching Between Timer0 and WDT... 38 Prescaler, Timer1 ... 40 Select (T1CKPS1:T1CKPS0 Bits) ... 39 Prescaler, Timer2 ... 48 Select (T2CKPS1:T2CKPS0 Bits) ... 43 PRO MATE II Universal Programmer ... 97 Product Identification System ... 149 Program Counter PCL Register ... 13, 23 PCLATH Register ... 13, 23, 91 Reset Conditions ... 86 Program Memory... 11 Interrupt Vector... 11 Paging ... 11, 23 Program Memory Map... 11 Reset Vector... 11 Program Verification ... 94 Programming Pin (VPP) ... 7, 8 Programming, Device Instructions... 95 PWM (CCP Module) ... 48 Block Diagram ... 48 CCPR1H:CCPR1L Registers ... 48 Duty Cycle ... 48 Example Frequencies/Resolutions ... 49 Output Diagram ... 48 Period ... 48 Set-Up for PWM Operation... 49 TMR2 to PR2 Match ... 43, 48 TMR2 to PR2 Match Enable (TMR2IE Bit) ... 18 TMR2 to PR2 Match Flag (TMR2IF Bit) ... 19

Q

Q-Clock... 48

R

RCSTA Register ... 62 CREN Bit ... 62 FERR Bit... 62 OERR Bit ... 62 RX9 Bit ... 62 RX9D Bit... 62 SPEN Bit... 61, 62 SREN Bit ... 62 Reader Response... 148 Register File ... 11 Register File Map ... 12 Reset ... 81, 83 Block Diagram ... 84 Reset Conditions for All Registers... 87 Reset Conditions for PCON Register ... 86 Reset Conditions for Program Counter ... 86 Reset Conditions for STATUS Register ... 86 DS30605A-page 143, Timing Diagram... 110 Revision History ... 137

S

SEEVAL Evaluation and Programming System... 99 SLEEP... 81, 83, 93 Software Simulator (MPLAB-SIM)... 99 Special Features of the CPU... 81 Special Function Registers ... 12, 13 Speed, Operating ... 1, 101 SPI (SSP Module) Block Diagram... 54 Buffer Full Status (BF Bit) ... 52 Clock Edge Select (CKE Bit)... 52 Clock Polarity Select (CKP Bit) ... 53 Data Input Sample Phase (SMP Bit)... 52 Mode Select (SSPM3:SSPM0 Bits) ... 53 Receive Overflow Indicator (SSPOV Bit) ... 53 Serial Clock (RC3/SCK/SCL)... 54 Serial Data In (RC4/SDI/SDA) ... 54 Serial Data Out (RC5/SDO) ... 54 Slave Select (RA5/SS/AN4)... 54 Synchronous Serial Port Enable (SSPEN Bit) ... 53 SSP... 51 Enable (SSPIE Bit)... 18 Flag (SSPIF Bit) ... 19 RA5/SS/AN4 Pin ... 7, 8 RC3/SCK/SCL Pin ... 7, 9 RC4/SDI/SDA Pin ... 7, 9 RC5/SDO Pin... 7, 9 RCSTA Register ... 13 SPBRG Register ... 14 SSPADD Register... 14 SSPBUF Register ... 13 SSPCON Register ... 13, 53 SSPSTAT Register ... 14, 52 TMR2 Output for Clock Shift ... 43, 44 TXSTA Register ... 14 Write Collision Detect (WCOL Bit) ... 53 SSPCON Register... 53 CKP Bit ... 53 SSPEN Bit... 53 SSPM3:SSPM0 Bits... 53 SSPOV Bit ... 53 WCOL Bit ... 53 SSPSTAT Register ... 52 BF Bit ... 52 CKE Bit ... 52 D/A Bit ... 52 P bit ... 52, 60 R/W Bit ... 52, 57, 58, 59 S Bit ... 52, 60 SMP Bit ... 52 UA Bit ... 52 Stack ... 23 STATUS Register... 13, 15, 91 C Bit ... 15 DC Bit... 15 IRP Bit ... 15 PD Bit ... 15, 83 RP1:RP0 Bits ... 15 TO Bit ... 15, 83 Z Bit... 15

T

T1CON Register... 13, 39 T1CKPS1:T1CKPS0 Bits ... 39 T1OSCEN Bit ... 39 T1SYNC Bit... 39 DS30605A-page 144 TMR1CS Bit... 39 TMR1ON Bit ... 39 T2CON Register ... 13, 43 T2CKPS1:T2CKPS0 Bits... 43 TMR2ON Bit ... 43 TOUTPS3:TOUTPS0 Bits ... 43 Timer0... 37 Block Diagram ... 37 Clock Source Edge Select (T0SE Bit) ... 16, 37 Clock Source Select (T0CS Bit) ... 16, 37 Overflow Enable (T0IE Bit) ... 17 Overflow Flag (T0IF Bit) ... 17, 91 Overflow Interrupt ... 38, 91 RA4/T0CKI Pin, External Clock ... 7, 8 Timing Diagram ... 111 TMR0 Register ... 13 Timer1... 39 Block Diagram ... 40 Capacitor Selection ... 41 Clock Source Select (TMR1CS Bit) ... 39 External Clock Input Sync (T1SYNC Bit)... 39 Module On/Off (TMR1ON Bit) ... 39 Oscillator... 39, 41 Oscillator Enable (T1OSCEN Bit) ... 39 Overflow Enable (TMR1IE Bit) ... 18 Overflow Flag (TMR1IF Bit) ... 19 Overflow Interrupt ... 39, 41 RC0/T1OSO/T1CKI Pin... 7, 9 RC1/T1OSI/CCP2 Pin ... 7, 9 Special Event Trigger (CCP) ... 41, 47 T1CON Register ... 13, 39 Timing Diagram ... 111 TMR1H Register ... 13, 39 TMR1L Register ... 13, 39 Timer2 Block Diagram ... 44 PR2 Register ... 14, 43, 48 SSP Clock Shift ... 43, 44 T2CON Register ... 13, 43 TMR2 Register ... 13, 43 TMR2 to PR2 Match Enable (TMR2IE Bit) ... 18 TMR2 to PR2 Match Flag (TMR2IF Bit) ... 19 TMR2 to PR2 Match Interrupt... 43, 44, 48 Timing Diagrams I2C Reception (7-bit Address)... 58 Time-out Sequence on Power-up... 88, 89 USART Asynchronous Master Transmission ... 67 USART Asynchronous Reception ... 68 USART Synchronous Reception ... 72 USART Synchronous Transmission ... 71 Wake-up from SLEEP via Interrupt ... 94 Timing Diagrams and Specifications ... 108 A/D Conversion ... 122 Brown-out Reset (BOR)... 110 Capture/Compare/PWM (CCP) ... 112 CLKOUT and I/O ... 109 External Clock ... 108 I2C Bus Data... 119 I2C Bus Start/Stop Bits ... 118 Oscillator Start-up Timer (OST)... 110 Parallel Slave Port (PSP) ... 113 Power-up Timer (PWRT) ... 110 Reset ... 110 Timer0 and Timer1 ... 111 USART Synchronous Receive ( Master/Slave) ... 120 USART SynchronousTransmission 1998 Microchip Technology Inc., ( Master/Slave)... 120 Watchdog Timer (WDT) ... 110 TRISE Register ... 14, 33 IBF Bit ... 33 IBOV Bit ... 33 OBF Bit ... 33 PSPMODE Bit... 31, 33, 35 TXSTA Register ... 61 BRGH Bit ... 61, 63 CSRC Bit... 61 SYNC Bit... 61 TRMT Bit... 61 TX9 Bit ... 61 TX9D Bit... 61 TXEN Bit ... 61

U

USART... 61 Asynchronous Mode ... 66 Master Transmission ... 67 Receive Block Diagram ... 68 Reception... 68 Transmit Block Diagram ... 66 Baud Rate Generator (BRG)... 63 Baud Rate Error, Calculating ... 63 Baud Rate Formula... 63 Baud Rates, Asynchronous Mode (BRGH=0) ... 64 Baud Rates, Asynchronous Mode (BRGH=1) ... 65 Baud Rates, Synchronous Mode ... 64 High Baud Rate Select (BRGH Bit) ... 61, 63 Sampling... 63 Clock Source Select (CSRC Bit)... 61 Continuous Receive Enable (CREN Bit)... 62 Framing Error (FERR Bit) ... 62 Mode Select (SYNC Bit) ... 61 Overrun Error (OERR Bit) ... 62 RC6/TX/CK Pin ... 7, 9 RC7/RX/DT Pin... 7, 9 RCREG Register... 13 RCSTA Register ... 62 Receive Data, 9th bit (RX9D Bit) ... 62 Receive Enable (RCIE Bit)... 18 Receive Enable, 9-bit (RX9 Bit) ... 62 Receive Flag (RCIF Bit) ... 19 Serial Port Enable (SPEN Bit)... 61, 62 Single Receive Enable (SREN Bit) ... 62 Synchronous Master Mode... 70 Reception... 72 Timing Diagram, Synchronous Receive ... 120 Timing Diagram, Synchronous Transmission ... 120 Transmission ... 71 Synchronous Slave Mode... 73 Transmit Data, 9th Bit (TX9D)... 61 Transmit Enable (TXEN Bit)... 61 Transmit Enable (TXIE Bit) ... 18 Transmit Enable, Nine-bit (TX9 Bit) ... 61 Transmit Flag (TXIE Bit) ... 19 Transmit Shift Register Status (TRMT Bit)... 61 TXREG Register ... 13 TXSTA Register ... 61

W

W Register ... 91 Wake-up from SLEEP... 81, 93 Interrupts... 86, 87 MCLR Reset ... 87 1998 Microchip Technology Inc. Timing Diagram ... 94 WDT Reset ... 87 Watchdog Timer (WDT)... 81, 92 Block Diagram ... 92 Enable (WDTE Bit) ... 81, 92 Programming Considerations ... 92 RC Oscillator ... 92 Time-out Period ... 92 Timing Diagram ... 110 WDT Reset, Normal Operation... 83, 86, 87 WDT Reset, SLEEP ... 83, 86, 87 WWW, On-Line Support ... 4, 147 DS30605A-page 145, NOTES: DS30605A-page 146 1998 Microchip Technology Inc.,

ON-LINE SUPPORT

Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape or Microsoft Explorer. Files are also available for FTP download from our FTP site.

Connecting to the Microchip Internet Web Site

The Microchip web site is available by using your favorite Internet browser to attach to: www.microchip.com The file transfer site is available by using an FTP ser- vice to connect to: ftp://ftp.futureone.com/pub/microchip The web site and file transfer site provide a variety of services. Users may download files for the latest Development Tools, Data Sheets, Application Notes, User's Guides, Articles and Sample Programs. A vari- ety of Microchip specific business information is also available, including listings of Microchip sales offices, distributors and factory representatives. Other data available for consideration is: • Latest Microchip Press Releases • Technical Support Section with Frequently Asked Questions • Design Tips • Device Errata • Job Postings • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Sys- tems, technical information and more • Listing of seminars and events 1998 Microchip Technology Inc.

Systems Information and Upgrade Hot Line

The Systems Information and Upgrade Line provides system users a listing of the latest versions of all of Microchip's development systems software products. Plus, this line provides information on how customers can receive any currently available upgrade kits.The Hot Line Numbers are: 1-800-755-2345 for U.S. and most of Canada, and 1-602-786-7302 for the rest of the world. Trademarks: The Microchip name, logo, PIC, PICSTART, PICMASTER and PRO MATE are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. PICmicro, FlexROM, MPLAB and fuzzyLAB are trademarks and SQTP is a service mark of Microchip in the U.S.A. All other trademarks mentioned herein are the property of their respective companies. DS30605A-page 147,

READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (602) 786-7578. Please list the following information, and use this outline to provide us with your comments about this Data Sheet. To: Technical Publications Manager Total Pages Sent RE: Reader Response From: Name Company Address City / State / ZIP / Country Telephone: (_) _ - _ FAX: (_) _ - _ Application (optional): Would you like a reply? Y N Device: PIC16C63A/65B/73B/74B Literature Number: DS30605A Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this data sheet easy to follow? If not, why? 4. What additions to the data sheet do you think would enhance the structure and subject? 5. What deletions from the data sheet could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? 8. How would you improve our software, systems, and silicon products? DS30605A-page 148 1998 Microchip Technology Inc.,

PIC16C63A/65B/73B/74B PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. -XX X /XX XXX Examples: Device Frequency Temperature Package Pattern a) PIC16C74B -04/P 301 = Commercial temp., Range Range PDIP package, 4 MHz, normal VDD limits, QTP pattern #301. b) PIC16LC63A - 04I/SO = Industrial temp., SOIC package, 200 kHz, Extended VDD limits. Device PIC16C6X(1), PIC16C6XT(2);VDD range 4.0V to 5.5V (1) (2) c) PIC16C65B - 20I/P = Industrial temp., PDIPPIC16LC6X , PIC16LC6XT ;VDD range 2.5V to 5.5V PIC16C7X(1), PIC16C7XT(2) package, 20MHz, normal VDD limits. ;VDD range 4.0V to 5.5V PIC16LC7X(1), PIC16LC7XT(2);VDD range 2.5V to 5.5V Frequency Range 04 = 4 MHz Note 1: C = CMOS 20 = 20 MHz LC = Low Power CMOS 2: T = in tape and reel - SOIC, SSOP, PLCC, QFP, TQ and FP Temperature Range blank = 0°C to 70°C (Commercial) packages only. I = -40°C to +85°C (Industrial) E = -40°C to +125°C (Extended) Package JW = Windowed CERDIP PQ = MQFP (Metric PQFP) PT = TQFP (Thin Quad Flatpack) SO = SOIC SP = Skinny plastic dip P = PDIP L = PLCC SS = SSOP Pattern QTP, SQTP, Code or Special Requirements (blank otherwise) * JW Devices are UV erasable and can be programmed to any device configuration. JW Devices meet the electrical requirement of each oscillator type (including LC devices). 1998 Microchip Technology Inc. DS30605A-page 149, NOTES: DS30605A-page 150 1998 Microchip Technology Inc., NOTES: 1998 Microchip Technology Inc. DS30605A-page 151,

M WORLDWIDE SALES AND SERVICE AMERICAS AMERICAS (continued) ASIA/PACIFIC (continued) Corporate Office Toronto Singapore

Microchip Technology Inc. Microchip Technology Inc. Microchip Technology Singapore Pte Ltd. 2355 West Chandler Blvd. 5925 Airport Road, Suite 200 200 Middle Road Chandler, AZ 85224-6199 Mississauga, Ontario L4V 1W1, Canada #07-02 Prime Centre Tel: 602-786-7200 Fax: 602-786-7277 Tel: 905-405-6279 Fax: 905-405-6253 Singapore 188980 Technical Support: 602 786-7627 Tel: 65-334-8870 Fax: 65-334-8850 Web: http://www.microchip.com ASIA/PACIFIC Taiwan, R.O.C

Atlanta Hong Kong Microchip Technology Taiwan

Microchip Technology Inc. Microchip Asia Pacific 10F-1C 207 500 Sugar Mill Road, Suite 200B RM 3801B, Tower Two Tung Hua North Road Atlanta, GA 30350 Metroplaza Taipei, Taiwan, ROC Tel: 770-640-0034 Fax: 770-640-0307 223 Hing Fong Road Tel: 886-2-2717-7175 Fax: 886-2-2545-0139

Boston Kwai Fong, N.T., Hong Kong EUROPE

Microchip Technology Inc. Tel: 852-2-401-1200 Fax: 852-2-401-3431 5 Mount Royal Avenue India United Kingdom Marlborough, MA 01752 Microchip Technology Inc. Arizona Microchip Technology Ltd. Tel: 508-480-9990 Fax: 508-480-8575 India Liaison Office 505 Eskdale Road

Chicago No. 6, Legacy, Convent Road Winnersh Triangle

Microchip Technology Inc. Bangalore 560 025, India Wokingham 333 Pierce Road, Suite 180 Tel: 91-80-229-0061 Fax: 91-80-229-0062 Berkshire, England RG41 5TU Itasca, IL 60143 Japan Tel: 44-1189-21-5858 Fax: 44-1189-21-5835 Tel: 630-285-0071 Fax: 630-285-0075 Microchip Technology Intl. Inc. France

Dallas Benex S-1 6F Arizona Microchip Technology SARL

Microchip Technology Inc. 3-18-20, Shinyokohama Zone Industrielle de la Bonde 14651 Dallas Parkway, Suite 816 Kohoku-Ku, Yokohama-shi 2 Rue du Buisson aux Fraises Dallas, TX 75240-8809 Kanagawa 222-0033 Japan 91300 Massy, France Tel: 972-991-7177 Fax: 972-991-8588 Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79

Dayton Korea Germany

Microchip Technology Inc. Microchip Technology Korea Arizona Microchip Technology GmbH Two Prestige Place, Suite 150 168-1, Youngbo Bldg. 3 Floor Gustav-Heinemann-Ring 125 Miamisburg, OH 45342 Samsung-Dong, Kangnam-Ku D-81739 Müchen, Germany Tel: 937-291-1654 Fax: 937-291-9175 Seoul, Korea Tel: 49-89-627-144 0 Fax: 49-89-627-144-44 Tel: 82-2-554-7200 Fax: 82-2-558-5934

Detroit ItalyShanghai

Microchip Technology Inc. Arizona Microchip Technology SRL 42705 Grand River, Suite 201 Microchip Technology Centro Direzionale Colleoni Novi, MI 48375-1727 RM 406 Shanghai Golden Bridge Bldg. Palazzo Taurus 1 V. Le Colleoni 1 Tel: 248-374-1888 Fax: 248-374-2874 2077 Yan’an Road West, Hong Qiao District 20041 Agrate Brianza Shanghai, PRC 200335 Milan, Italy

Los Angeles Tel: 86-21-6275-5700 Fax: 86 21-6275-5060 Tel: 39-39-6899939 Fax: 39-39-6899883

Microchip Technology Inc. 18201 Von Karman, Suite 1090 7/7/98 Irvine, CA 92612 Tel: 714-263-1888 Fax: 714-263-1338

New York Microchip received ISO 9001 Quality System certification for its worldwide

Microchip Technology Inc. headquarters, design, and wafer 150 Motor Parkway, Suite 202 Hauppauge, NY 11788 fabrication facilities in January, 1997. Tel: 516-273-5305 Fax: 516-273-5335 Our field-programmable PICmicro™

San Jose 8-bit MCUs, Serial EEPROMs,

related specialty memory products Microchip Technology Inc. 2107 North First Street, Suite 590 and development systems conform San Jose, CA 95131 to the stringent quality standards of Tel: 408-436-7950 Fax: 408-436-7955 the International Standard

Organization (ISO).

All rights reserved. © 1998, Microchip Technology Incorporated, USA. 8/98 Printed on recycled paper. Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded by updates. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. The Microchip logo and name are registered trademarks of Microchip Technology Inc. in the U.S.A. and other countries. All rights reserved. All other trademarks mentioned herein are the property of their respective companies.

DS30605A-page 152 1998 Microchip Technology Inc.

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