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PCM2704 and PCM2705 Not Recommended For New Designs PCM2704, PCM2705 PCM2706, PCM2707 Burr-Brown Audio www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009 STEREO AUDIO DAC WITH USB INTERFACE, SINGLE-ENDED HEADPHONE OUTPUT AND S/PDIF OUTPUT 1FEATURES – External ROM Interface (PCM2704/6) 2345• On-Chip USB Interface: – Serial Programming Interface (PCM2705/7) – No Need of Dedicated Device Driver – I2S Interface (Selectable on PCM2706/7) – With Full-Speed Transceivers • Package: – Fully Compliant With USB 1.1 Specification – 28-Pin SSOP (PCM2704/5) – Certified by USB-IF – 32-Pin TQFP (PCM2706/7)...
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PCM2704 and PCM2705 Not Recommended For New Designs

PCM2704, PCM2705 PCM2706, PCM2707

Burr-Brown Audio

www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009 STEREO AUDIO DAC WITH USB INTERFACE, SINGLE-ENDED HEADPHONE OUTPUT AND S/PDIF OUTPUT 1FEATURES – External ROM Interface (PCM2704/6) 2345• On-Chip USB Interface: – Serial Programming Interface (PCM2705/7) – No Need of Dedicated Device Driver – I2S Interface (Selectable on PCM2706/7) – With Full-Speed Transceivers • Package: – Fully Compliant With USB 1.1 Specification – 28-Pin SSOP (PCM2704/5) – Certified by USB-IF – 32-Pin TQFP (PCM2706/7) – Partially Programmable Descriptors – Adaptive Isochronous Transfer for APPLICATIONS Playback • USB Headphones – Bus-Powered or Self-Powered Operation • USB Audio Speaker • Sampling Rate: 32, 44.1, 48 kHz • USB CRT/LCD Monitor • On-Chip Clock Generator With Single 12-MHz • USB Audio Interface Box Clock Source • USB-Featured Consumer Audio Product • Single Power Supply: DESCRIPTION – Bus-Powered: 5 V, Typical (VBUS) The PCM2704/5/6/7 is TI's single-chip USB stereo – Self-Powered: 3.3 V, Typical audio DAC with USB-compliant full-speed protocol • 16-Bit Delta-Sigma Stereo DAC controller and S/PDIF. The USB-protocol controller – Analog Performance at5V(Bus-Powered), works with no software code, but USB descriptors 3.3 V (Self-Powered): can be modified in some parts (for example, vendor ID/product ID) through the use of an external ROM – THD+N: 0.006% RL > 10 kΩ, (PCM2704/6), SPI (PCM2705/7), or on request. (1) Self-Powered The PCM2704/5/6/7 employs SpAct™ architecture, – THD+N: 0.025% RL = 32 Ω TI's unique system that recovers the audio clock from – SNR = 98 dB USB packet data. On-chip analog PLLs with SpAct enable playback with low clock jitter. – Dynamic Range: 98 dB – PO = 12 mW, RL = 32 Ω – Oversampling Digital Filter – Pass-Band Ripple = ±0.04 dB – Stop-Band Attenuation = –50 dB – Single-Ended Voltage Output – Analog LPF Included • Multiple Functions: – Up to Eight Human Interface Device (HID) Interfaces (Depending on Model and (1) The modification of the USB descriptor through external ROM Settings) or SPI must comply with USB-IF guidelines, and the vendor – Suspend Flag ID must be your own ID as assigned by the USB-IF. The descriptor also can be modified by changing a mask; contact – S/PDIF Out With SCMS your representative for details.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SpAct is a trademark of Texas Instruments. 3System Two, Audio Precision are trademarks of Audio Precision, Inc. 4I2S is a trademark of NXP Semiconductors. 5All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date. Copyright © 2003–2009, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not

necessarily include testing of all parameters., PCM2704, PCM2705 PCM2704 and PCM2705 PCM2706, PCM2707 Not Recommended For New Designs SLES081F–JUNE 2003–REVISED JANUARY 2009... www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1)

VBUS –0.3 V to 6.5 VSupply voltage VCCP, VCCL, VCCR, VDD –0.3 V to 4 V Supply voltage differences VCCP, VCCL, VCCR, VDD ±0.1 V Ground voltage differences PGND, AGNDL, AGNDR, DGND, ZGND ±0.1 V HOST –0.3 V to 6.5 V Digital input voltage D+, D–, HID0/MS, HID1/MC, HID2/MD, XTI, XTO, DOUT, SSPND, CK, DT, PSEL, FSEL, TEST, TEST0, TEST1, FUNC0, FUNC1, FUNC2, FUNC3 –0.3 V to (VDD + 0.3) V < 4 V VCOM –0.3 V to (VCCP + 0.3) V < 4 V Analog input voltage VOUTR –0.3 V to (VCCR + 0.3) V < 4 V VOUTL –0.3 V to (VCCL + 0.3) V < 4 V Input current (any pins except supplies) ±10 mA Ambient temperature under bias –40°C to 125°C Storage temperature –55°C to 150°C Junction temperature 150°C Lead temperature (soldering) 260°C, 5 s Package temperature (IR reflow, peak) 260°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range

MIN NOM MAX UNIT V 4.35 5 5.25 Supply voltage BUS V VCCP, VCCL, VCCR, VDD 3 3.3 3.6 Digital input logic level TTL compatible Digital input clock frequency 11.994 12 12.006 MHz Analog output load resistance 16 32 Ω Analog output load capacitance 100 pF Digital output load capacitance 20 pF Operating free-air temperature, TA –25 85 C

2 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated,

PCM2704 and PCM2705 PCM2704, PCM2705 Not Recommended For New Designs PCM2706, PCM2707

www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009 ELECTRICAL CHARACTERISTICS all specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz,16-bit data (unless otherwise noted)

PCM2704DB, PCM2705DB, PARAMETER TEST CONDITIONS PCM2706PJT, PCM2707PJT UNIT MIN TYP MAX DIGITAL INPUT/OUTPUT Host interface Apply USB revision 1.1, full-speed Audio data format USB isochronous data format INPUT LOGIC VIH 2 3.3 VIL –0.3 0.8Input logic level Vdc V (1)IH 2 5.5 V (1)IL –0.3 0.8 I (2)IH VIN = 3.3 V ±10 I (2)IL V = 0 V ±10Input logic current IN µA IIH VIN = 3.3 V 65 100 IIL VIN = 0 V ±10 OUTPUT LOGIC V (3)OH IOH = –2 mA 2.8 V (3)OL I = 2 mA 0.3Output logic level OL Vdc VOH IOH = –2 mA 2.4 VOL IOL = 2 mA 0.4 CLOCK FREQUENCY Input clock frequency, XTI 11.994 12 12.006 MHz

fs Sampling frequency 32, 44.1, 48 kHz

DAC CHARACTERISTICS Resolution 16 Bits Audio data channel 1, 2 Channel DC ACCURACY Gain mismatch, channel-to-channel ±2 ±8 % of FSR Gain error ±2 ±8 % of FSR Bipolar zero error ±3 ±6 % of FSR DYNAMIC PERFORMANCE (4) RL > 10 kΩ, self-powered, V 0.006% 0.01% Line (5) OUT

= 0 dB

THD+N Total harmonic RL > 10 kΩ, bus-powered,distortion + noise V = 0 dB 0.012% 0.02%OUT Headphone RL = 32 Ω, self-/bus-powered, VOUT = 0 dB

0.025%

THD+N Total harmonic distortion + noise VOUT = –60 dB 2% Dynamic range EIAJ, A-weighted 90 98 dB S/N Signal-to-noise ratio EIAJ, A-weighted 90 98 dB Channel separation 60 70 dB

(1) HOST (2) D+, D–, HOST, TEST, TEST0, TEST1, DT, PSEL, FSEL, XTI (3) FUNC0, FUNC1, FUNC2 (4) fIN = 1 kHz, using the System Two™ Cascade audio measurement system by Audio Precision™ in the RMS mode with a 20-kHz LPF and 400-Hz HPF. (5) THD+N performance varies slightly, depending on the effective output load, including dummy load R7, R8 in Figure 32.

Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 3

, PCM2704, PCM2705 PCM2704 and PCM2705 PCM2706, PCM2707 Not Recommended For New Designs SLES081F–JUNE 2003–REVISED JANUARY 2009... www.ti.com ELECTRICAL CHARACTERISTICS (continued) all specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz,16-bit data (unless otherwise noted)

PCM2704DB, PCM2705DB, PARAMETER TEST CONDITIONS PCM2706PJT, PCM2707PJT UNIT MIN TYP MAX ANALOG OUTPUT Output voltage 0.55 VCCL, 0.55 VCCR Vp-p Center voltage 0.5 VCCP V Line AC coupling 10 kΩ Load impedance Headphone AC coupling 16 32 Ω

–3 dB 140 kHz

LPF frequency response

f = 20 kHz –0.1 dB

DIGITAL FILTER PERFORMANCE Pass band 0.454 fs Hz Stop band 0.546 fs Hz Pass-band ripple ±0.04 dB Stop-band attenuation –50 dB Delay time 20/fs s POWER SUPPLY REQUIREMENTS VBUS Bus-powered 4.35 5 5.25 Voltage range VCCP, VCCL, VCCR, Vdc V Self-powered 3 3.3 3.6DD Line DAC operation 23 30

mA

Supply current Headphone DAC operation RL = 32 Ω) 35 46 Line/headphone Suspend mode (6) 150 190 µA Line DAC operation 76 108 Power dissipation mW

(self-powered) Headphone DAC operation RL = 32 Ω) 116 166

Line/headphone Suspend mode (6) 495 684 µW Line DAC operation 115 158 Power dissipation mW

(bus-powered) Headphone DAC operation RL = 32 Ω) 175 242

Line/headphone Suspend mode (6) 750 998 µW Internal power-supply VCCP, VCCL, VCCR,

voltage (7) V Bus-powered 3.2 3.35 3.5 VdcDD

TEMPERATURE RANGE Operating temperature –25 85 °C

28-pin SSOP (PCM2704/5) 100 θJA Thermal resistance °C/W32-pin TQFP (PCM2706/7) 80 (6) Under USB suspend state. (7) VDD, VCCP, VCCL, VCCR. These pins work as output pins of internal power supply for bus-powered operation. 4 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated,

PCM2704 and PCM2705 PCM2704, PCM2705 Not Recommended For New Designs PCM2706, PCM2707

www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009 PIN ASSIGNMENTS

PCM2704/PCM2705 PCM2706/PCM2707 DB PACKAGE PJT PACKAGE

(TOP VIEW) (TOP VIEW)

XTO 1 28 XTI CK 2 27 SSPND DT 3 26 TEST0 PSEL 4 25 TEST1 24 23 22 21 20 19 18 17 DOUT 5 24 HID2/MD ZGND 25 16 PSEL DGND 6 23 HID1/MC AGNDL 26 15 DT V 7 22 HID0/MS VCCL 27 14DD CK D– 8 21 HOST VOUTL 28 13 XTO D+ 9 20 VCCP VOUTR 29 12 XTI VBUS 10 19 PGND VCCR 30 11 SSPND ZGND 11 18 VCOM AGNDR 31 10 TEST AGNDL 12 17 AGNDR VCOM 32 9 FSEL VCCL 13 16 VCCR12345678 VOUTL 14 15 VOUTR P0020-01

Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 5

PGND VBUS VCCP D+ HOST D– FUNC3 VDD FUNC0 DGND HID0/MS FUNC1 HID1/MC FUNC2 HID2/MD DOUT

, PCM2704, PCM2705 PCM2704 and PCM2705 PCM2706, PCM2707 Not Recommended For New Designs SLES081F–JUNE 2003–REVISED JANUARY 2009... www.ti.com Terminal Functions (PCM2704DB/PCM2705DB)

TERMINAL I/O DESCRIPTION NAME NO. AGNDL 12 — Analog ground for headphone amplifier of L-channel AGNDR 17 — Analog ground for headphone amplifier of R-channel CK2OClock output for external ROM (PCM2704). Must be left open (PCM2705). D+ 9 I/O USB differential input/output plus (1) D– 8 I/O USB differential input/output minus (1) DGND 6 — Digital ground DOUT5OS/PDIF output DT 3 I/O Data input/output for external ROM (PCM 2704). Must be left open with pullup resistor (PCM2705). (1) HID0/MS 22 I HID key state input (mute), active HIGH (PCM2704). MS input (PCM2705). (2) HID1/MC 23 I HID key state input (volume up), active HIGH (PCM2704). MC input (PCM2705). (2) HID2/MD 24 I HID key state input (volume down), active HIGH (PCM2704). MD input (PCM2705). (2) HOST 21 I Host detection during self-powered operation (connect to VBUS). Max power select during bus-powered

operation (LOW: 100 mA, HIGH: 500 mA). (3)

PGND 19 — Analog ground for DAC, OSC, and PLL PSEL4IPower source select (LOW: self-power, HIGH: bus-power) (1) SSPND 27 O Suspend flag, active LOW (LOW: suspend, HIGH: operational) TEST0 26 I Test pin. Must be set HIGH (1) TEST1 25 I Test pin. Must be set HIGH (1) VBUS 10 — Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation. VCCL 13 — Analog power supply for headphone amplifier of L-channel (4) VCCP 20 — Analog power supply for DAC, OSC, and PLL (4) V 16 — Analog power supply for headphone amplifier of R-channel (4)CCR VCOM 18 — Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND. V (4)DD 7 — Digital power supply VOUTL 14 O DAC analog output for L-channel VOUTR 15 O DAC analog output for R-channel XTI 28 I Crystal oscillator input (1) XTO1OCrystal oscillator output ZGND 11 — Ground for internal regulator

(1) LV-TTL level (2) LV-TTL level with internal pulldown (3) LV-TTL level, 5-V tolerant (4) Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications. 6 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated,

PCM2704 and PCM2705 PCM2704, PCM2705 Not Recommended For New Designs PCM2706, PCM2707

www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009 Terminal Functions (PCM2706PJT/PCM2707PJT)

TERMINAL I/O DESCRIPTION NAME NO. AGNDL 26 — Analog ground for headphone amplifier of L-channel AGNDR 31 — Analog ground for headphone amplifier of R-channel CK 14 O Clock output for external ROM (PCM2706). Must be left open (PCM2707). D+ 23 I/O USB differential input/output plus (1) D– 22 I/O USB differential input/output minus (1) DGND 20 — Digital ground DOUT 17 O S/PDIF output/I2S™ data output DT 15 I/O Data input/output for external ROM (PCM2706). Must be left open with pullup resistor (PCM2707). (1) FSEL9IFunction select (LOW: I2S DATA output, HIGH: S/PDIF output) (1) FUNC0 5 I/O HID key state input (next track), active HIGH (FSEL = 1). I2S LR clock output (FSEL = 0). (2) FUNC1 19 I/O HID key state input (previous track), active HIGH (FSEL = 1). I2S bit clock output (FSEL = 0). (2) FUNC2 18 I/O HID key state input (stop), active HIGH (FSEL = 1). I2S system clock output (FSEL = 0). (2) FUNC34IHID key state input (play/pause), active HIGH (FSEL = 1). I2S data input (FSEL = 0). (2) HID0/MS6IHID key state input (mute), active HIGH (PCM2706). MS input (PCM2707) (2) HID1/MC7IHID key state input (volume up), active HIGH (PCM2706). MC input (PCM2707) (2) HID2/MD8IHID key state input (volume down), active HIGH (PCM2706). MD input (PCM2707) (2) HOST3IHost detection during self-powered operation (connect to VBUS). Max power select during bus-powered

operation. (LOW: 100 mA, HIGH: 500 mA). (3)

PGND 1 — Analog ground for DAC, OSC, and PLL PSEL 16 I Power source select (LOW: self-power, HIGH: bus-power) (1) SSPND 11 O Suspend flag, active LOW (LOW: suspend, HIGH: operational) TEST 10 I Test pin. Must be set HIGH (1) VBUS 24 — Connect to USB power (VBUS) for bus-powered operation. Connect to VDD for self-powered operation. VCCL 27 — Analog power supply for headphone amplifier of L-channel (4) VCCP 2 — Analog power supply for DAC, OSC, and PLL (4) VCCR 30 — Analog power supply for headphone amplifier of R-channel (4) VCOM 32 — Common voltage for DAC (VCCP/2). Connect decoupling capacitor to PGND. VDD 21 — Digital power supply (4) VOUTL 28 O DAC analog output for L-channel VOUTR 29 O DAC analog output for R-channel XTI 12 I Crystal oscillator input (1) XTO 13 O Crystal oscillator output ZGND 25 — Ground for internal regulator

(1) LV-TTL level (2) LV-TTL level with internal pulldown (3) LV-TTL level, 5-V tolerant (4) Connect decoupling capacitor to GND. Supply 3.3 V for self-powered applications.

Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 7

, PCM2704, PCM2705 PCM2704 and PCM2705 PCM2706, PCM2707 Not Recommended For New Designs SLES081F–JUNE 2003–REVISED JANUARY 2009... www.ti.com BLOCK DIAGRAM (PCM2704DB/PCM2705DB)

VCCP VCCL VCCR VDD PGND AGNDL AGNDR DGND ZGND Power Manager SSPND

5-V to 3.3-V

Voltage Regulator VBUS VCOM USB Analog Protocol VOUTL ControllerPLL DAC D+ V ControlOUTR Endpoint D– DOUT S/PDIF Encoder EEPROM CK ISO-Out Interface(1) FIFO DT Endpoint HOST HID SPI HID0/MS PSEL Endpoint Interface(2) HID1/MC HID2/MD TEST0 TEST1

96 MHz Tracker

PLL (×8)

(SpAct)

XTI 12 MHz XTO B0054-01

(1) Applies to PCM2704DB (2) Applies to PCM2705DB 8 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

USB SIE XCVR

,

PCM2704 and PCM2705 PCM2704, PCM2705 Not Recommended For New Designs PCM2706, PCM2707

www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009 BLOCK DIAGRAM (PCM2706PJT/PCM2707PJT)

VCCP VCCL VCCR VDD PGND AGNDL AGNDR DGND ZGND Power Manager SSPND

5-V to 3.3-V

Voltage Regulator VBUS VCOM USB Analog Protocol VOUTL ControllerPLL DAC V R Control D+ OUT Endpoint D– S/PDIF Encoder DOUT FSEL DOUT LRCK FUNC0 BCK FUNC1 I2S I/F EEPROM SYSCK CK FUNC2 ISO-Out Interface(1) DIN FIFO DT FUNC3 Endpoint HOST HID3: Next Track(1) HID4: Previous Track(1) HID5: Stop (1) HID SPI HID0/MS HID6: Play/Pause (1) Endpoint Interface(2) HID1/MC HID2/MD PSEL TEST

96 MHz Tracker

PLL (×8)

(SpAct)

XTI 12 MHz XTO B0055-01

(1) Applies to PCM2706PJT (2) Applies to PCM2707PJT Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 9

USB SIE XCVR

, PCM2704, PCM2705 PCM2704 and PCM2705 PCM2706, PCM2707 Not Recommended For New Designs SLES081F–JUNE 2003–REVISED JANUARY 2009... www.ti.com TYPICAL PERFORMANCE CURVES OF INTERNAL FILTER All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted). DAC Digital Interpolation Filter Frequency Response AMPLITUDE AMPLITUDE vs vs FREQUENCY FREQUENCY 0 0.05 0.04 −20 0.03 −40 0.02 0.01 −60 0.00 −80 −0.01 −100 −0.02 −0.03 −120 −0.04 −140 −0.05012340.0 0.1 0.2 0.3 0.4 0.5 f – Frequency [× fS] f – Frequency [× fS]

G001 G002

Figure 1. Frequency Response Figure 2. Pass-Band Ripple DAC Analog Low-Pass Filter Frequency Response AMPLITUDE AMPLITUDE vs vs FREQUENCY FREQUENCY 0.0 0 −0.5 −20 −1.0 −40 −1.5 −60 −2.0 −80 0.01 0.1 1 10 100 1 10 100 1k 10k f – Frequency – kHz f – Frequency – kHz

G003 G004

Figure 3. Pass-Band Characteristics Figure 4. Stop-Band Characteristics 10 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

Amplitude – dB Amplitude – dB Amplitude – dB Amplitude – dB

,

PCM2704 and PCM2705 PCM2704, PCM2705 Not Recommended For New Designs PCM2706, PCM2707

www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009 TYPICAL PERFORMANCE CURVES All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted). TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 0.05 0.05

Bus-Powered Self-Powered VOUT = 0 dB VOUT = 0 dB

0.04 0.04 0.03 0.03 32 Ω 32 Ω 0.02 0.02 10 kΩ 0.01 0.01 10 kΩ 0.00 0.00 −50 −25 0 25 50 75 100 −50 −25 0 25 50 75 100

TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C G005 G006

Figure 5. Figure 6. TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE 0.05 0.05

Bus-Powered Self-Powered VOUT = 0 dB VOUT = 0 dB

0.04 0.04 0.03 0.03 32 Ω 32 Ω 0.02 0.02 10 kΩ 0.01 0.01 10 kΩ 0.00 0.00 4.0 4.5 5.0 5.5 3.0 3.1 3.2 3.3 3.4 3.5 3.6

VCC – Supply Voltage – V VCC – Supply Voltage – V G007 G008

Figure 7. Figure 8. Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 11

THD+N – Total Harmonic Distortion + Noise – % THD+N – Total Harmonic Distortion + Noise – % THD+N – Total Harmonic Distortion + Noise – % THD+N – Total Harmonic Distortion + Noise – %

, PCM2704, PCM2705 PCM2704 and PCM2705 PCM2706, PCM2707 Not Recommended For New Designs SLES081F–JUNE 2003–REVISED JANUARY 2009... www.ti.com TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted). TOTAL HARMONIC DISTORTION + NOISE TOTAL HARMONIC DISTORTION + NOISE vs vs SAMPLING FREQUENCY SAMPLING FREQUENCY 0.05 0.05

Bus-Powered Self-Powered VOUT = 0 dB VOUT = 0 dB

0.04 0.04 32 Ω 0.03 0.03 32 Ω 0.02 0.02 10 kΩ 0.01 0.01 10 kΩ 0.00 0.00 30 35 40 45 50 30 35 40 45 50 fS – Sampling Frequency – kHz fS – Sampling Frequency – kHz

G009 G010

Figure 9. Figure 10. DYNAMIC RANGE and SNR DYNAMIC RANGE and SNR vs vs FREE-AIR TEMPERATURE FREE-AIR TEMPERATURE 105 105

Bus-Powered Self-Powered

103 103 101 101 99 99

Dynamic Range Dynamic Range

97 97

SNR SNR

95 95 −50 −25 0 25 50 75 100 −50 −25 0 25 50 75 100

TA – Free-Air Temperature – °C TA – Free-Air Temperature – °C G011 G012

Figure 11. Figure 12. 12 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

Dynamic Range and SNR – dB THD+N – Total Harmonic Distortion + Noise – % Dynamic Range and SNR – dB THD+N – Total Harmonic Distortion + Noise – %

,

PCM2704 and PCM2705 PCM2704, PCM2705 Not Recommended For New Designs PCM2706, PCM2707

www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009 TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted). DYNAMIC RANGE and SNR DYNAMIC RANGE and SNR vs vs SUPPLY VOLTAGE SUPPLY VOLTAGE 105 105

Bus-Powered Self-Powered

103 103 101 101 99 99

Dynamic Range Dynamic Range SNR SNR

97 97 95 95 4.0 4.5 5.0 5.5 3.0 3.1 3.2 3.3 3.4 3.5 3.6

VCC – Supply Voltage – V VCC – Supply Voltage – V G013 G014

Figure 13. Figure 14. DYNAMIC RANGE and SNR DYNAMIC RANGE and SNR vs vs SAMPLING FREQUENCY SAMPLING FREQUENCY 105 105

Bus-Powered Self-Powered

103 103 101 101

Dynamic Range

99 Dynamic Range 99

SNR

97 SNR 97 95 95 30 35 40 45 50 30 35 40 45 50 fS – Sampling Frequency – kHz fS – Sampling Frequency – kHz

G015 G016

Figure 15. Figure 16. Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 13

Dynamic Range and SNR – dB Dynamic Range and SNR – dB Dynamic Range and SNR – dB Dynamic Range and SNR – dB

, PCM2704, PCM2705 PCM2704 and PCM2705 PCM2706, PCM2707 Not Recommended For New Designs SLES081F–JUNE 2003–REVISED JANUARY 2009... www.ti.com TYPICAL PERFORMANCE CURVES (continued) All specifications at TA = 25°C, VBUS = 5 V, fS = 44.1 kHz, fIN = 1 kHz, 16-bit data (unless otherwise noted). SUSPEND CURRENT SUSPEND CURRENT vs vs SUPPLY VOLTAGE FREE-AIR TEMPERATURE 200 200 150 150 100 100 50 50004.0 4.5 5.0 5.5 −50 −25 0 25 50 75 100

VBUS – Supply Voltage – V TA – Free-Air Temperature – °C G017 G018

Figure 17. Figure 18. AMPLITUDE AMPLITUDE vs vs FREQUENCY FREQUENCY00−20 −20 −40 −40 −60 −60 −80 −80 −100 −100 −120 −120 −140 −1400510 15 20 0 20 40 60 80 100 120 f – Frequency – kHz f – Frequency – kHz

G019 G020

Figure 19. Output Spectrum (–60 dB, N = 8192) Figure 20. Output Spectrum (–60 dB, N = 8192) 14 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

Amplitude – dB Suspend Current – µA Amplitude – dB Suspend Current – µA

,

PCM2704 and PCM2705 PCM2704, PCM2705 Not Recommended For New Designs PCM2706, PCM2707

www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009 DETAILED DESCRIPTION Clock and Reset

For both USB and audio functions, the PCM2704/5/6/7 requires a 12-MHz (±500 ppm) clock, which can be

generated by the built-in oscillator using a 12-MHz crystal resonator. The 12-MHz crystal resonator must be connected to XTI (pin 28 for PCM2704/5, pin 12 for PCM2706/7) and XTO (pin 1 for PCM2704/5, pin 13 for

PCM2706/7) with one large (1-MΩ) resistor and two small capacitors, the capacitance of which depends on the

specified load capacitance of the crystal resonator. An external clock can be supplied from XTI (pin 28 for

PCM2704/5, pin 12 for PCM2706/7). If an external clock is supplied, XTO (pin 1 for PCM2704/5, pin 13 for PCM2706/7) must be left open. Because no clock disabling pin is provided, it is not recommended to use the

external clock supply. SSPND (pin 27 for PCM2704/5, pin 11 for PCM2706/7) is unable to use clock disabling.

The PCM2704/5/6/7 has an internal power-on reset circuit, and it works automatically when VDD (pin 7 for PCM2704/5, pin 21 for PCM2706/7) exceeds2Vtypical (1.6 V–2.4 V), which is equivalent to VBUS (pin 10 for PCM2704/5, pin 24 for PCM2706/7) exceeding3Vtypical for bus-powered applications. Approximately 700 µs is

required until internal reset release. Operation Mode Selection

The PCM2704/5/6/7 has the following mode-select pins. Power Configuration Select/Host Detection PSEL (pin 4 for PCM2704/5, pin 16 for PCM2706/7) is dedicated to selecting the power source. This selection

affects the configuration descriptor. While in bus-powered operation, maximum power consumption from VBUS is determined by HOST (pin 21 for PCM2704/5, pin 3 for PCM2706/7). For self-powered operation, HOST must be connected to VBUS of the USB bus with a pulldown resistor to detect attach and detach. (To avoid excessive suspend current, the pulldown should be a high-value resistor.)

Table 1. Power Configuration Select PSEL DESCRIPTION

0 Self-powered 1 Bus-powered

HOST DESCRIPTION

0 Detached from USB (self-powered)/100 mA (bus-powered) 1 Attached to USB (self-powered)/500 mA (bus-powered)

Function Select (PCM2706/7) FSEL (pin 9) determines the function of FUNC0–FUNC3 (pins 4, 5, 18, and 19) and DOUT (pin17). When the I2S

interface is required, FSEL must be set to LOW. Otherwise, FSEL must be set to HIGH.

Table 2. Function Select FSEL DOUT FUNC0 FUNC1 FUNC2 FUNC3

0 Data out (I2S) LRCK (I2S) BCK (I2S) SYSCK (I2S) Data in (I2S) 1 S/PDIF data Next track (HID) (1) Previous track (HID) (1) Stop (HID) (1) Play/pause (HID) (1) (1) Valid on the PCM2706; no function assigned on the PCM2707.

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, PCM2704, PCM2705 PCM2704 and PCM2705 PCM2706, PCM2707 Not Recommended For New Designs SLES081F–JUNE 2003–REVISED JANUARY 2009... www.ti.com USB Interface Control data and audio data are transferred to the PCM2704/5/6/7 via D+ (pin 9 for PCM2704/5, pin 23 for PCM2706/7) and D– (pin 8 for PCM2704/5, pin 22 for PCM2706/7). D+ should be pulled up with a 1.5-kΩ (±5%) resistor. To avoid back voltage in self-powered operation, the device must not provide power to the pullup resistor on D+ while VBUS of the USB port is inactive. All data to/from the PCM2704/5/6/7 are transferred at full speed. The following information is provided in the device descriptor. Some parts of the device descriptor can be modified through external ROM (PCM2704/6), SPI (PCM2705/7), or internal mask ROM on request. Table 3. Device Descriptor

DEVICE DESCRIPTOR DESCRIPTION USB revision 1.1 compliant Device class 0x00 (device defined interface level) Device subclass 0x00 (not specified) Device protocol 0x00 (not specified) Max packet size for endpoint08bytes Vendor ID 0x08BB (default value, can be modified) Product ID 0x2704/0x2705/0x2706/0x2707 (These values correspond to the model number, and the value can bemodified.) Device release number 1.0 (0x0100) Number of configurations 1 Vendor strings Burr-Brown from TI (default value, can be modified) Product strings USB Audio DAC (default value, can be modified) Serial number Not supported

The following information is contained in the configuration descriptor. Some parts of the configuration descriptor can be modified through external ROM (PCM2704/6), SPI (PCM2705/7), or internal mask ROM on request. Table 4. Configuration Descriptor

CONFIGURATION DESCRIPTOR DESCRIPTION Interface Three interfaces Power attribute 0x80 or 0xC0 (bus-powered or self-powered, depending on PSEL; no remote wake up. This value canbe modified.) Max power 0x0A, 0x32 or 0xFA (20 mA for self-powered, 100 mA or 500 mA for bus-powered, depending onPSEL and HOST. This value can be modified.)

The following information is contained in the string descriptor. Some parts of the string descriptor can be modified through external ROM (PCM2704/6), SPI (PCM2705/7), or internal mask ROM on request. Table 5. String Descriptor

STRING DESCRIPTOR DESCRIPTION

#0 0x0409 #1 Burr-Brown from TI (default value, can be modified) #2 USB Audio DAC (default value, can be modified) 16 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated,

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www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009 Device Configuration Figure 21 illustrates the USB audio function topology. The PCM2704/5/6/7 has three interfaces. Each interface is enabled by some alternative settings.

Endpoint #0 Default Endpoint FU Endpoint #2

(IF #1) IT OT

TID1 TID2 Analog Out Audio Streaming Interface UID3 Standard Audio Control Interface (IF #0) Endpoint #5

(IF #2)

HID Interface PCM2704/5/6/7 M0024-01

Figure 21. USB Audio Function Topology Interface #0 (Default/Control Interface) Interface #0 is the control interface. Setting #0 is the only possible setting for interface #0. Setting #0 describes the standard audio control interface. Audio control interface consists of a terminal. The PCM2704/5/6/7 has three terminals: • Input terminal (IT #1) for isochronous-out stream • Output terminal (OT #2) for audio analog output • Feature unit (FU #3) for DAC digital attenuator Input terminal #1 is defined as a USB stream (terminal type 0x0101). Input terminal #1 can accept two-channel audio streams constructed of left and right channels. Output terminal #2 is defined as a speaker (terminal type 0x0301). Feature unit #3 supports the following sound control features: • Volume control • Mute control The built-in digital volume controller can be manipulated by an audio-class-specific request from 0 dB to –64 dB in steps of 1 dB. Changes are made by incrementing or decrementing one step (1 dB) for every 1/fS time interval, until the volume level reaches the requested value. Each channel can be set to a separate value. The master volume control is not supported. A request to the master volume is stalled and ignored. The built-in digital mute controller can be manipulated by an audio-class-specific request. A master mute control request is acceptable. A mute control request to an individual channel is stalled and ignored. The digital volume control does not affect the S/PDIF and I2S outputs (PCM2706/7).

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Interface #1 (Isochronous-Out Interface) Interface #1 is for the audio-streaming data-out interface. Interface #1 has the following three alternative settings. Alternative setting #0 is the zero-bandwidth setting. All other alternative settings are operational settings. ALTERNATIVE DATA FORMAT TRANSFER SAMPLING RATESETTING MODE (kHz)

00 Zero bandwidth 01 16-bit Stereo 2s complement (PCM) Adaptive 32, 44.1, 48 02 16-bit Mono 2s complement (PCM) Adaptive 32, 44.1, 48

Interface #2 (HID Interface) Interface #2 is the interrupt-data-in interface. Interface #2 comprises the HID consumer control device. Alternative setting #0 is the only possible setting for interface #2. On the HID device descriptor, eight HID items are reported as follows for any model, in any configuration. Basic HID Operation Interface #2 can report the following three key statuses for any model. These statuses can be set by the HID0–HID2 pins (PCM2704/6) or the SPI port (PCM2705/7).

• Mute (0xE2) • Volume up (0xE9) • Volume down (0xEA)

Extended HID Operation (PCM2705/6/7) By using the FUNC0–FUNC3 pins (PCM2706) or the SPI port (PCM2705/7), the following additional conditions

can be reported to the host. • Play/Pause (0xCD) • Stop (0xB7) • Previous (0xB6) • Next (0xB5)

Auxiliary HID Status Report (PCM2705/7) One additional HID status can be reported to the host though the SPI port. This status flag is defined by SPI

command or external ROM. This definition must be described as on the report descriptor with a three-byte usage

ID. AL A/V Capture (0x0193) is assigned as the default for this status flag. Endpoints The PCM2704/5/6/7 has three endpoints:

• Control endpoint (EP #0) • Isochronous-out audio data-stream endpoint (EP #2) • HID endpoint (EP #5)

The control endpoint is a default endpoint. The control endpoint is used to control all functions of the PCM2704/5/6/7 by standard USB request and USB audio-class-specific request from the host. The

isochronous-out audio data-stream endpoint is an audio sink endpoint that receives the PCM audio data. The isochronous-out audio data-stream endpoint accepts the adaptive transfer mode. The HID endpoint is an interrupt-in endpoint. The HID endpoint reports HID status every 10 ms.

The HID endpoint is defined as a consumer-control device. The HID function is designed as an independent

endpoint from the isochronous-out endpoint. This means that the effect of HID operation depends on host software. Typically, the HID function is used to control the primary audio-out device. 18 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated,

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www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009

DAC

The PCM2704/5/6/7 has a DAC that uses an oversampling technique with 128-fS second-order multibit noise shaping. This technique provides extremely low quantization noise in the audio band, and the built-in analog low-pass filter removes the high-frequency components of the noise-shaping signal. DAC outputs through the headphone amplifier VOUTL and VOUTR can provide 12 mW at 32 Ω, as well as 1.8 VPP into a 10-kΩ load. Digital Audio Interface—S/PDIF Output The PCM2704/5/6/7 employs S/PDIF output. Isochronous-out data from the host are encoded to S/PDIF output DOUT, as well as to DAC analog outputs VOUTL and VOUTR. Interface format and timing follow the IEC-60958 standard. Monaural data are converted to the stereo format at the same data rate. S/PDIF output is not supported in the I2S I/F enable mode. The implementation of this feature is optional. Note that it is your responsibility to determin whether to implement this feature in your product or not. Channel Status Information The channel status information is fixed as consumer application, PCM mode, copyright, and digital/digital converter. All other bits are fixed as 0s, except for the sample frequency, which is set automatically according to the data received through the USB. Copyright Management Digital audio data output always is encoded as original with SCMS control. Only one generation of digital duplication is allowed. Digital Audio Interface—I2S Interface Output (PCM2706/7) The PCM2706 and PCM2707 can support the I2S interface, which is enabled by FSEL (pin 9). In the I2S interface enabled mode, pins 4, 18, 19, 5, and 17 are assigned as DIN, SYSCK, BCK, LRCK, and DOUT, respectively. They provide digital output/input data in the 16-bit I2S format, which also is accepted by the internal DAC. I2S interface format and timing are shown in Figure 22, Figure 23, and Figure 24.

SYSCK

(256 fS) 1/fS

LRCK L-Channel R-Channel BCK

(64 fS)

DOUT12314 15 1612314 15 16 1 2 MSB LSB MSB LSB MSB DIN12314 15 1612314 15 16 1 2 T0009-04

Figure 22. Audio Data Interface Format

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LRCK (Output) 50% of VDD

t(BCL) t(BCH) t(BL)

BCK (Output) 50% of VDD

t(BCY) t(BD) t(LD)

DOUT (Output) 50% of VDD

t(DS) t(DH)

DIN (Input) 50% of VDD T0010-05

SYMBOL PARAMETER MIN MAX UNIT t(BCY) BCK pulse cycle time 300 ns t(BCH) BCK pulse duration, HIGH 100 ns t(BCL) BCK pulse duration, LOW 100 ns t(BL) LRCK delay time from BCK falling edge –20 40 ns t(BD) DOUT delay time from BCK falling edge –20 40 ns t(LD) DOUT delay time from LRCK edge –20 40 ns t(DS) DIN setup time 20 ns t(DH) DIN hold time 20 ns NOTE: Load capacitance of LRCK, BCK, and DOUT is 20 pF. Figure 23. Audio Interface Timing

SYSCK

(Output) t(SLL) t(SLH)

LRCK

(Output) t(SBL) t(SBH)

BCK

(Output)

T0196-01

SYMBOL PARAMETER MIN MAX UNIT t(SLL), t(SLH) LRCK delay time from SYSCK rising edge –5 10 ns t(SBL), t(SBH) BCK delay time from SYSCK rising edge –5 10 ns NOTE: Load capacitance is 20 pF. Figure 24. Audio Clock Timing 20 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated,

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www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009 DESCRIPTOR DATA MODIFICATION The descriptor data can be modified through I2C port by external ROM (PCM2704/6) or through our SPI port by an SPI host such as an MCU (PCM2705/7) under a particular condition of PSEL pin and HOST pin. A condition of PSEL pin = High and HOST pin = High is needed to modify the descriptor data, and D+ pull-up must not be activated before completion of programming the descriptor data through external ROM or SPI port. The descriptor data have to be sent from external ROM to PCM2704/6 or or from SPI host to PCM2705/7 in LSB first with specified byte order. Also, the content of the power attribute and max power must be consistent with PSEL setting and power usage from USB VBUS of actual application. Therefore, the descriptor data modification in self-powered configuration (PSEL = Low) is not supported. External ROM Descriptor (PCM2704/6) The PCM2704/6 supports an external ROM interface to override internal descriptors. Pin 3 (for PCM2704)/pin 15 (for PCM2706) is assigned as DT (serial data) and pin 2 (for PCM2704)/pin 14 (for PCM2706) is assigned as CK (serial clock) of the I2C interface when using the external ROM descriptor. Descriptor data is transferred from the external ROM to the PCM2704/6 through the I2C interface the first time when the device activates after power-on reset. Before completing a read of the external ROM, the PCM2704/6 replies with NACK for any USB command request from the host to the device itself. The descriptor data, which can be in external ROM, are as follows. String descriptors must be described in ANSI ASCII code (1 byte for each character). String descriptors are converted automatically to unicode strings for transmission to the host. The device address of the external ROM is fixed as 0xA0. The data must be stored from address 0x00 and must consist of 57 bytes, as described in the following items. The data bits must be sent from LSB to MSB on the I2C bus. This means that each byte of data must be stored with its bits in reverse order. Read operation is performed at a frequency of XTI/384 (approximately 30 kHz). The content of power attribute and max power must be consistent with actual application circuit configuration (PSEL setting and actual power usage from VBUS of USB connector); otherwise, it may cause improper or unexpected PCM2704/6 operation. • Vendor ID (2 bytes) • Product ID (2 bytes) • Product string (16 bytes in ANSI ASCII code) • Vendor string (32 bytes in ANSI ASCII code) • Power attribute (1 byte) • Max power (1 byte) • Auxiliary HID usage ID in report descriptor (3 bytes)

DT CK S 1−7891−8 9 1−899P Device Address R/W ACK DATA ACK DATA ACK NACK Start Condition R/W: Read Operation if 1; Otherwise, Write Operation Stop Condition ACK: Acknowledgment of a Byte if 0 DATA: 8 Bits (Byte) NACK: Not Acknowledgment if 1 T0049-02 MMMSSMSMSMM S Device address R/W ACK DATA ACK DATA ACK ... NACK P

Figure 25. External ROM Read Operation

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Start Repeated Start Stop

t(D-HD) t(DT-F) t(BUF) t(D-SU) t(DT-R) t(P-SU)

DT

t(CK-R) t(RS-HD) t(LOW)

CK

t(S-HD) t(HI) t(RS-SU) t(CK-F)

T0050-02

SYMBOL PARAMETER MIN MAX UNIT f(CK) CK clock frequency 100 kHz t(BUF) Bus free time between a STOP and a START condition 4.7 µs t(LOW) Low period of the CK clock 4.7 µs t(HI) High period of the CK clock 4 µs t(RS-SU) Setup time for START/repeated START condition 4.7 µs t(S-HD) t Hold time for START/repeated START condition 4 µs(RS-HD) t(D-SU) Data setup time 250 ns t(D-HD) Data hold time 0 900 ns t(CK-R) Rise time of CK signal 20 + 0.1 CB 1000 ns t(CK-F) Fall time of CK signal 20 + 0.1 CB 1000 ns t(DT-R) Rise time of DT signal 20 + 0.1 CB 1000 ns t(DT-F) Fall time of DT signal 20 + 0.1 CB 1000 ns t(P-SU) Setup time for STOP condition 4 µs CB Capacitive load for DT and CK lines 400 pF VNH Noise margin at HIGH level for each connected device (including hysteresis) 0.2 VDD V Figure 26. External ROM Read Interface Timing Requirements 22 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated,

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www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009 External ROM Example Here is an example of external ROM data, with an explanation of the example following the data. 0xBB, 0x08, 0x04, 0x27, 0x50, 0x72, 0x6F, 0x64, 0x75, 0x63, 0x74, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x2E, 0x56, 0x65, 0x6E, 0x64, 0x6F, 0x72, 0x20, 0x73, 0x74, 0x72, 0x69, 0x6E, 0x67, 0x73, 0x20, 0x61, 0x72, 0x65, 0x20, 0x70, 0x6C, 0x61, 0x63, 0x65, 0x64, 0x20, 0x68, 0x65, 0x72, 0x65, 0x2E, 0x20, 0x80, 0x7D, 0x0A, 0x93, 0x01 The data are stored beginning at address 0x00. Vendor ID: 0x08BB Product ID: 0x2704 Product string: Product strings (16 bytes). Vendor string: Vendor strings are placed here (32 bytes, 31 visible characters are followed by 1 space). Power attribute (bmAttribute): 0x80 (Bus-powered). Max power (maxPower): 0x7D (250 mA). Auxiliary HID usage ID: 0x0A, 0x93, 0x01 (AL A/V capture). Note that the data bits must be sent from LSB to MSB on the I2C bus. This means that each data byte must be stored with its bits in reverse order.

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, PCM2704, PCM2705 PCM2704 and PCM2705 PCM2706, PCM2707 Not Recommended For New Designs SLES081F–JUNE 2003–REVISED JANUARY 2009... www.ti.com Serial Programming Interface (PCM2705/7) The PCM2705/7 supports the serial programming interface (SPI) to program the descriptor and to set the HID state. Descriptor data are described in the SubSec1 8.8External ROM Descriptor section. t(MHH)

MS 50% of VDD

t(MLS) t(MCL) t(MCH) t(MLH)

MC 50% of VDD

t(MCY)

MD LSB 50% of VDD

t(MDS) t(MDH)

T0013-04

SYMBOL PARAMETER MIN TYP MAX UNIT t(MCY) MC pulse cycle time 100 ns t(MCL) MC low-level time 50 ns t(MCH) MC high-level time 50 ns t(MHH) MS high-level time 100 ns t(MLS) MS falling edge to MC rising edge 20 ns t(MLH) MS hold time 20 ns t(MDH) MD hold time 15 ns t(MDS) MD setup time 20 ns Figure 27. SPI Timing Diagram (1) Single Write Operation 16 Bits

MS MC MD MSB LSB MSB

(2) Continuous Write Operation 16 Bits N Frames

MS MC MD MSB LSB MSB LSB MSB LSB N Frames T0012-02

Figure 28. SPI Write Operation 24 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated,

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www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009 SPI Register (PCM2705/7)

B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0

0000ST 0 ADDR 0 D0 D1 D2 D3 D4 D5 D6 D7

D[7:0] Function of the lower 8 bits depends on the value of the ST (B11) bit. ST = 0 (HID status write) D7 Reports MUTE HID status to the host (active high) D6 Reports volume-up HID status to the host (active high) D5 Reports volume-down HID status to the host (active high) D4 Reports next-track HID status to the host (active high) D3 Reports previous-track HID status to the host (active high) D2 Reports stop HID status to the host (active high) D1 Reports play/pause HID status to the host (active high) D0 Reports extended command status to the host (active high) ST = 1 (ROM data write) D[7:0] Internal descriptor ROM data, D0:LSB, D7:MSB The content of power attribute and max power must be consistent with the actual application circuit

configuration (PSEL setting and actual power usage from VBUS of USB connector); otherwise, it may cause improper or unexpected PCM2705/7 operation.

ADDR Starts write operation for internal descriptor reprogramming (active high) This bit resets descriptor ROM address counter and indicates following words should be ROM data (described

in the External ROM Example section). 456 bits of ROM data must be continuously followed after this bit has been asserted. The data bits must be sent from LSB (D0) to MSB (D7).

To set ADDR high, ST must be set low. Note that the lower 8 bits are still active as an HID status write when ST is set low. ST Determines the function of the lower 8-bit data as follows:

0: HID status write 1: Descriptor ROM data write

Table 6. Functionality of ST and ADDR Bit Combinations ST ADDR FUNCTION

0 0 HID status write01HID status write and descriptor ROM address reset10Descriptor ROM data write11Reserved

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, PCM2704, PCM2705 PCM2704 and PCM2705 PCM2706, PCM2707 Not Recommended For New Designs SLES081F–JUNE 200Î3–RÎEVISÎED JANUARY 2009... www.ti.comUSB Host InteÎÎrfaÎÎce SequencePower-On, AttachThe PCM2704/5ÎÎ/6/ÎÎ , anÎÎÎd Playback Sequence7 isÎready for setup when the reset sequence has finished and the USB bus is attached. Aftera connection hÎasÎbeeÎn established by setup, the PCM2704/5/6/7 is ready to accept USB audio data. Whilewaiting for the aÎudiÎo dÎata (idle state)Î, the analoÎg output isÎset toÎbipÎolar zero (BPZ).When receiving the audio data, the PCM2704/5/6/7 stores the first audio packet, which contains 1 ms of audiodata, into the inÎÎterÎÎnalÎÎstorage buffeÎÎr. The PCMÎÎ2704/5/6ÎÎ/7 startÎÎs pÎÎlayiÎÎÎng tÎÎÎhe audÎÎÎioÎÎÎdataÎÎÎafÎÎÎterÎÎÎdeteÎÎÎcting the nextsubsequent start-of-frame (SOF) packet.ÎÎÎÎÎÎ ÎÎ3.3 VV ÎÎÎ 2.0 V (Typ.) (Typ.)DD0 V ÎÎÎÎÎÎÎÎÎ Bus ReÎset Set CÎonfigurationÎ ÎÎ1sÎt AudÎio DataÎÎ2ndÎ AudÎio DBus IdD+/D− ÎÎ le ÎÎÎÎ Î ataÎÎÎÎÎÎÎ

SOF SOF SOF SSPND ÎÎÎÎÎÎÎÎÎ BPZVOUTLVOUTR

700 µs Device Setup 1 ms

Internal Reset Ready for Setup Ready for Playback T0055-01

Figure 29. Initial Sequence 26 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated,

PCM2704 and PCM2705 PCM2704, PCM2705 Not Recommended For New Designs PCM2706, PCM2707

www.ti.com...ÎÎÎ...ÎÎÎ...ÎÎÎ...ÎÎÎ...ÎÎÎ...ÎÎÎ...ÎÎÎ...ÎÎÎ...ÎÎÎ...ÎÎÎ...ÎÎÎ...ÎÎÎ...ÎÎÎ...ÎÎÎ...ÎÎÎ... SLES081F–JUNE 2003–REVISED JANUARY 2009Play, Stop, andÎDeÎtacÎh SÎequenceWhen the host finishes or abortsÎtheÎplÎaybÎackÎ, thÎe PÎCMÎ270Î4/5Î/6/7 stÎops playing after completing the output ofthe last audio data.VBUS ÎAudio Data Audio Data Last Audio Data ÎD+/D– ÎSOF SOF SOF SOF SOÎF

VOUTL VOUTR

ÎÎ 1 ms DetachÎ T0056-01Î Figure 30. Play, Stop, and DetachSuspend and ReÎsume SequenceThe PCM2704/5/6/7 enters the suspend state after the USB bus has been in a constant idle state forapproximately 5 ms. While the PCM2704/5/6/7 is in the suspend state, SSPND flag (pin 27 for PCM2704/5,pin 11 for PCM2706/7) is asserted. The PCM2704/5/6/7 wakes up immediatelyÎÎÎÎÎwheÎÎÎÎÎn detecting the non-idle stateon the USB bus. IdleD+/D−

SSPND

5 ms Suspend

VOUTL VOUTR Active Active

2.5 ms

T0057-01

Figure 31. Suspend and Resume Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 27, PCM2704, PCM2705 PCM2704 and PCM2705 PCM2706, PCM2707 Not Recommended For New Designs SLES081F–JUNE 2003–REVISED JANUARY 2009... www.ti.com Typical Circuit Connection 1 (Example of USB Speaker) Figure 32 illustrates a typical circuit connection for an internal-descriptor, bus-powered, 500-mA application.

X1 C1 C2 R1 PCM2704DB

(3)

External ROM

(Optional) 1 XTO XTI 28

SUSPEND SCL 2 CK SSPND 27 SDA 3 DT TEST0 26 R (2)9 4 PSEL TEST1 25 S/PDIF OUT 5 DOUT HID2/MD 24 VOLUME–

6 DGND HID1/MC 23

USB ’B’ R C7 VOLUME+2 Connector 7 VDD HID0/MS 22 R3 MUTE

(2)

D– 8 D– HOST 21 R4 C4 D+ 9 D+ V (3)CCP 20 VBUS 10 VBUS PGND 19 C3 + C8 GND 11 ZGND VCOM 18

12 AGNDL AGNDR 17

C6 C5

13 VCCL VCCR 16 C9 C13 (1) (1) + + 14 VOUT L VOUTR 15 + +

C11 C12 C10 C14 TPA200X Power Amp R5 R6 R7 R8

NOTE: X1: 12-MHz crystal resonator. C1, C2: 10-pF to 33-pF capacitor (depending on load capacitance of crystal resonator). C3-C7: 1-µF ceramic capacitor. C8: 10-µF electrolytic capacitor. C9, C10: 100-µF electrolytic capacitor (depending on tradeoff between required frequency response and discharge time for resume). C11, C12: 0.022-µF ceramic capacitor. C13, C14: 1-µF electrolytic capacitor. R1: 1 MΩ resistor. R2, R9: 1.5 kΩ resistors. R3, R4: 22 Ω resistors. R5, R6: 16 Ω resistors. R7, R8: 330 Ω resistors (depending on tradeoff between required THD performance and pop-noise level for suspend). (1) Output impedance of VOUTL and VOUTR during suspend mode or lack of power supply is 26 kΩ ±20%, which is the discharge path for C9 and C10. (2) Descriptor programming through external ROM is only available when PSEL and HOST are high. (3) External ROM power can be supplied from VCCP, but any other active component must not use VCCP, VCCL, VCCR, or VDD as a power source. Figure 32. Bus-Powered Application NOTE: The circuit illustrated in Figure 32 is for information only. The entire board design should be considered to meet the USB specification as a USB-compliant product. 28 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated,

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www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009 Typical Circuit Connection 2 (Example of Remote Headphone) Figure 33 illustrates a typical circuit connection for a bus-powered, 100-mA headphone with seven HIDs.

C9 Headphone

+ +

C11 C12 C10 R C 5 R6 R7 R8 R9 R10

6 C3 C4 + 32 31 30 29 28 27 26 25 USB ’B’

R Connector2 C5

1 PGND V 24BUS V

R BUS3

(3) 2 VCCP D+ 23 D+ (2) 3 HOST D– 22 D–

PLAY/PAUSE

4 FUNC3 V 21

R4 DD GND NEXT TRACK PCM2706PJT C8

5 FUNC0 DGND 20 C7

MUTE PREVIOUS TRACK

6 HID0/MS FUNC1 19

VOLUME+ STOP

7 HID1/MC FUNC2 18

VOLUME–

8 HID2/MD DOUT 17 (3)

External ROM

(Optional) 91 10 11 12 13 14 5 16

SDA SUSPEND R1 R11 SCL X1 C1 C2

NOTE: X1: 12-MHz crystal resonator. C1, C2: 10-pF to 33-pF capacitors (depending on load capacitance of crystal resonator). C3-C5, C7, C8: 1-µF ceramic capacitors. C6: 10-µF electrolytic capacitor. C9, C10: 100-µF electrolytic capacitors (depending on required frequency response). C11, C12: 0.022-µF ceramic capacitors. R1: 1 MΩ resistor. R2, R11: 1.5 kΩ resistors. R3, R4: 22 Ω resistors. R5, R6: 16 Ω resistors. R7-R10: 3.3 kΩ resistors. (1) Output impedance of VOUTL and VOUTR during suspend mode or lack of power supply is 26 kΩ ±20%, which is the discharge path for C9 and C10. (2) Descriptor programming through external ROM is only available when PSEL and HOST are high. (3) External ROM power can be supplied from VCCP, but any other active component must not use VCCP, VCCL, VCCR, or VDD as a power source. Figure 33. Bus-Powered Application NOTE: The circuit illustrated in Figure 33 is for information only. The entire board design should be considered to meet the USB specification as a USB-compliant product. Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 29

FSEL VCOM TEST AGNDR SSPND VCCR

(1)

XTI VOUT R

(1)

XTO VOUT L CK VCCL DT AGNDL

(2)

PSEL ZGND

, PCM2704, PCM2705 PCM2704 and PCM2705 PCM2706, PCM2707 Not Recommended For New Designs SLES081F–JUNE 2003–REVISED JANUARY 2009... www.ti.com Typical Circuit Connection 3 (Example of DSP Surround Processing Amp) Figure 34 illustrates a typical circuit connection for an I2S- and SPI-enabled self-powered application. +

C8 Headphone

+

C10 C11 C9 C6 C3 C4

+ R6 R7 R8 R9 R10 R11 32 31 30 29 28 27 26 25 USB ’B’

Connector R (3)C 25

1 PGND V 24 V (3)BUS (4) R BUS

T AS300X 3

2 232VD+ D+I S I/F Audio Device + CCP (2) 3 HOST D– 22 D–

DIN

4 RFUNC3 V 21 (3) 4 RDD + 12 GND

LRCK PCM2707PJT C7

5 FUNC0 DGND 20

MS (4) BCK

6 HID0/MS FUNC1 19

MC SYSTEM CLOCK

7 HID1/MC FUNC2 18

MD DOUT

8 HID2/MD DOUT 17 91 10 11 12 13 14 51 6

R5 SUSPEND R1 X1 Power C C 3.3 V1 2 GND

NOTE: X1: 12-MHz crystal resonator. C1, C2: 10-pF to 33-pF capacitors (depending on load capacitance of crystal resonator). C3, C4: 1-µF ceramic capacitors. C5, C7: 0.1-µF ceramic capacitor and 10-µF electrolytic capacitor. C6: 10-µF electrolytic capacitors. C8, C9: 100-µF electrolytic capacitors (depending on required frequency response). C10, C11: 0.022-µF ceramic capacitors. R1, R12: 1 MΩ resistors. R2, R5: 1.5 kΩ resistors. R3, R4: 22 Ω resistors. R6, R7: 16 Ω resistors. R8-R11: 3.3 kΩ resistors. (1) Output impedance of VOUTL and VOUTR during suspend mode or lack of power supply is 26 kΩ ±20%, which is the discharge path for C8 and C9. (2) Descriptor programming through SPI is only available when PSEL and HOST are high. (3) D+ pull-up must not be activated (HIGH: 3.3V) while the device is detached from USB or power supply is not applied on VDD and VCCx. VBUS of USB (5V) can be used to detect USB power status. (4) MS must be high until the PCM2707 power supply is ready and the SPI host (DSP) is ready to send data. Also, the SPI host must handle the D+ pull-up if the descriptor is programmed through the SPI. D+ pull-up must not be activated (HIGH = 3.3 V) before programming of the PCM2707 through the SPI is complete. Figure 34. Self-Powered Application NOTE: The circuit illustrated in Figure 34 is for information only. The entire board design should be considered to meet the USB specification as a USB-compliant product. 30 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated

FSEL VCOM TEST AGNDR SSPND VCCR

(1)

XTI VOUT R

(1)

XTO VOUT L CK VCCL DT AGNDL

(2)

PSEL ZGND

,

PCM2704 and PCM2705 PCM2704, PCM2705 Not Recommended For New Designs PCM2706, PCM2707

www.ti.com... SLES081F–JUNE 2003–REVISED JANUARY 2009

APPENDIX

Operating Environment For current information on the PCM2704/2705/2706/2707 operating environment, see the Updated Operating Environments for PCM270X, PCM290X Applications application report, SLAA374, available through the TI web site at www.ti.com.

Copyright © 2003–2009, Texas Instruments Incorporated Submit Documentation Feedback 31

, PCM2704, PCM2705 PCM2704 and PCM2705 PCM2706, PCM2707 Not Recommended For New Designs SLES081F–JUNE 2003–REVISED JANUARY 2009... www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (November 2007) to Revision F ... Page • Added new feature... 1 • Moved text to end of Digital Audio Interface-S/PDIF Output section... 19 • Added Descriptor Data Modification paragraph... 21 • Deleted HOST from list of circuit configuration terms... 21 • Deleted HOST from list of circuit configuration terms... 25 • Added notes to Figure 32, Figure 33, and Figure 34 for clarifying requirement of descriptor programing... 28 Changes from Revision D (December 2006) to Revision E ... Page • Deleted operating environment information from data sheet and added reference to application report ... 31 32 Submit Documentation Feedback Copyright © 2003–2009, Texas Instruments Incorporated,

PACKAGE OPTION ADDENDUM

www.ti.com 24-Jan-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Qty Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples (1) Drawing (2) (3) (4) PCM2704DB NRND SSOP DB 28 47 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2704 & no Sb/Br) PCM2704DBG4 NRND SSOP DB 28 47 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2704 & no Sb/Br) PCM2704DBR NRND SSOP DB 28 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2704 & no Sb/Br) PCM2704DBRG4 NRND SSOP DB 28 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2704 & no Sb/Br) PCM2705DB NRND SSOP DB 28 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2705 & no Sb/Br) PCM2705DBG4 NRND SSOP DB 28 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2705 & no Sb/Br) PCM2705DBR NRND SSOP DB 28 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2705 & no Sb/Br) PCM2705DBRG4 NRND SSOP DB 28 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2705 & no Sb/Br) PCM2706PJT ACTIVE TQFP PJT 32 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2706 & no Sb/Br) PCM2706PJTG4 ACTIVE TQFP PJT 32 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2706 & no Sb/Br) PCM2706PJTR ACTIVE TQFP PJT 32 1000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2706 & no Sb/Br) PCM2706PJTRG4 ACTIVE TQFP PJT 32 1000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2706 & no Sb/Br) PCM2707PJT ACTIVE TQFP PJT 32 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2707 & no Sb/Br) PCM2707PJTG4 ACTIVE TQFP PJT 32 250 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2707 & no Sb/Br) PCM2707PJTR ACTIVE TQFP PJT 32 1000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2707 & no Sb/Br) PCM2707PJTRG4 ACTIVE TQFP PJT 32 1000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -25 to 85 PCM2707 & no Sb/Br) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. Addendum-Page 1,

PACKAGE OPTION ADDENDUM

www.ti.com 24-Jan-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2,

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Mar-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1 Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant (mm) W1 (mm) PCM2704DBR SSOP DB 28 2000 330.0 17.4 8.5 10.8 2.4 12.0 16.0 Q1 PCM2705DBR SSOP DB 28 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 PCM2706PJTR TQFP PJT 32 1000 330.0 16.8 9.6 9.6 1.5 12.0 16.0 Q2 PCM2707PJTR TQFP PJT 32 1000 330.0 16.8 9.6 9.6 1.5 12.0 16.0 Q2 Pack Materials-Page 1,

PACKAGE MATERIALS INFORMATION

www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) PCM2704DBR SSOP DB 28 2000 336.6 336.6 28.6 PCM2705DBR SSOP DB 28 2000 367.0 367.0 38.0 PCM2706PJTR TQFP PJT 32 1000 367.0 367.0 38.0 PCM2707PJTR TQFP PJT 32 1000 367.0 367.0 38.0 Pack Materials-Page 2,

MECHANICAL DATA

MPQF112 – NOVEMBER 2001

PJT (S-PQFP–N32) PLASTIC QUAD FLATPACK

0,80 0,45 0,20 M 0,30 0,20 0,09 Gage Plane 0,15 0,25 1 0,05 0°– 7° 7,00 SQ 9,00 SQ 0,75 0,45 1,05 0,95 Seating Plane 1,20 0,10 1,00 4203540/A 11/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Falls within JEDEC MS-026 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1,

MECHANICAL DATA

MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001

DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE

28 PINS SHOWN 0,38 0,65 0,15 M 0,22 28 15 0,25 0,09 5,60 8,20 5,00 7,40 Gage Plane 1 14 0,25 A 0°–8° 0,95 0,55 Seating Plane 2,00 MAX 0,05 MIN 0,10 PINS ** 14 16 20 24 28 30 38

DIM

A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 4040065 /E 12/01 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-150 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265,

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily performed. TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered documentation. Information of third parties may be subject to additional restrictions. Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use of any TI components in safety-critical applications. In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and requirements. Nonetheless, such components are subject to these terms. No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties have executed a special agreement specifically governing such use. Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and regulatory requirements in connection with such use. TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of non-designated products, TI will not be responsible for any failure to meet ISO/TS16949. Products Applications Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps DSP dsp.ti.com Energy and Lighting www.ti.com/energy Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial Interface interface.ti.com Medical www.ti.com/medical Logic logic.ti.com Security www.ti.com/security Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video RFID www.ti-rfid.com OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com Wireless Connectivity www.ti.com/wirelessconnectivity Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2013, Texas Instruments Incorporated]
15

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DISCRETE SEMICONDUCTORS DATA SHEET M3D176 1N914; 1N916 High-speed diodes Product specification 1996 Apr 10 Supersedes data of April 1992 File under Discrete Semiconductors, SC01 FEATURES DESCRIPTION • Hermetically sealed leaded glass The 1N914; 1N916 are high-speed switching diodes fabricated in pla
DISCRETE SEMICONDUCTORS DATA SHEET
DISCRETE SEMICONDUCTORS DATA SHEET handbook, halfpage M3D119 1N5817; 1N5818; 1N5819 Schottky barrier diodes Product specification 1996 May 03 Supersedes data of April 1992 File under Discrete Semiconductors, SC01 FEATURES DESCRIPTION • Low switching losses The 1N5817 to 1N5819 types are Schottky bar
DISCRETE SEMICONDUCTORS DATA SHEET 1N5225B to 1N5267B Voltage regulator diodes Product specification 1996 Apr 26 Supersedes data of April 1992 File under Discrete Semiconductors, SC01
DISCRETE SEMICONDUCTORS DATA SHEET M3D176 1N5225B to 1N5267B Voltage regulator diodes Product specification 1996 Apr 26 Supersedes data of April 1992 File under Discrete Semiconductors, SC01 FEATURES DESCRIPTION • Total power dissipation: Low-power voltage regulator diodes in hermetically sealed lea
DISCRETE SEMICONDUCTORS DATA SHEET 1N5059 to 1N5062 Controlled avalanche rectifiers Product specification 1996 Jun 20 Supersedes data of April 1992 File under Discrete Semiconductors, SC01
DISCRETE SEMICONDUCTORS DATA SHEET handbook, 2 columns M3D116 1N5059 to 1N5062 Controlled avalanche rectifiers Product specification 1996 Jun 20 Supersedes data of April 1992 File under Discrete Semiconductors, SC01 FEATURES DESCRIPTION This package is hermetically sealed and fatigue free as coeffic
DISCRETE SEMICONDUCTORS DATA SHEET 1N4728A to 1N4749A Voltage regulator diodes Product specification 1996 Apr 26 Supersedes data of April 1992 File under Discrete Semiconductors, SC01
DISCRETE SEMICONDUCTORS DATA SHEET handbook, halfpage M3D130 1N4728A to 1N4749A Voltage regulator diodes Product specification 1996 Apr 26 Supersedes data of April 1992 File under Discrete Semiconductors, SC01 FEATURES DESCRIPTION • Total power dissipation: Low voltage regulator diodes in hermetical
DISCRETE SEMICONDUCTORS DATA SHEET 1N4531; 1N4532 High-speed diodes Product specification 1996 Apr 03 Supersedes data of April 1992 File under Discrete Semiconductors, SC01
DISCRETE SEMICONDUCTORS DATA SHEET handbook, halfpage M3D050 1N4531; 1N4532 High-speed diodes Product specification 1996 Apr 03 Supersedes data of April 1992 File under Discrete Semiconductors, SC01 FEATURES DESCRIPTION • Hermetically sealed leaded glass The 1N4531, 1N4532 are high-speed switching d
DISCRETE SEMICONDUCTORS DATA SHEET
DISCRETE SEMICONDUCTORS DATA SHEET M3D176 1N4150; 1N4151; 1N4153 High-speed diodes Product specification 1996 Apr 19 Supersedes data of April 1992 File under Discrete Semiconductors, SC01 FEATURES DESCRIPTION • Hermetically sealed leaded glass The 1N4150, 1N4151, 1N4153 are high-speed switching diod