Download: Features Description with 4K Bytes

Features • Compatible with MCS-51™ Products • 4K Bytes of Reprogrammable Flash Memory - Endurance: 1,000 Write/Erase Cycles • 2.7V to 6V Operating Range • Fully Static Operation: 0 Hz to 12 MHz • Three-Level Program Memory Lock • 128 x 8-Bit Internal RAM • 32 Programmable I/O Lines • Two 16-Bit Timer/Counters • Six Interrupt Sources 8-Bit • Programmable Serial Channel • Low Power Idle and Power Down Modes Microcontroller Description with 4K Bytes The AT89LV51 is a low-voltage, high-performance CMOS 8-bit microcomputer with Flash 4K bytes of Flash Programmable and Erasable Read Only Memory. The...
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Features

• Compatible with MCS-51™ Products • 4K Bytes of Reprogrammable Flash Memory - Endurance: 1,000 Write/Erase Cycles • 2.7V to 6V Operating Range • Fully Static Operation: 0 Hz to 12 MHz • Three-Level Program Memory Lock • 128 x 8-Bit Internal RAM • 32 Programmable I/O Lines • Two 16-Bit Timer/Counters • Six Interrupt Sources 8-Bit • Programmable Serial Channel • Low Power Idle and Power Down Modes Microcontroller

Description with 4K Bytes The AT89LV51 is a low-voltage, high-performance CMOS 8-bit microcomputer with Flash

4K bytes of Flash Programmable and Erasable Read Only Memory. The device is manufactured using Atmel's high density nonvolatile memory technology and is com- patible with the industry standard MCS-51™ instruction set and pinout. The on-chip

Flash allows the program memory to be reprogrammed in-system or by a conven- AT89LV51

tional nonvolatile memory programmer. By combining a versatile 8-bit CPU with Flash on a monolithic chip, the Atmel AT89LV51 is a powerful microcomputer which pro- vides a highly flexible and cost effective solution to many embedded control applica- tions. PDIP

Pin ConfigurationsP1. 0140VCC

P 1 . 1239P0. 0 ( AD0) P 1 . 2338P0. 1 ( AD1) P 1 . 3437P0. 2 ( AD2) P 1 . 4536P0. 3 ( AD3) P 1 . 5635P0. 4 ( AD4) P 1 . 6734P0. 5 ( AD5) P 1 . 7833P0. 6 ( AD6)

TQFPRST932P0. 7 ( AD7)

( RXD) P 3 . 01031EA/ VPP( TXD) P 3 . 11130ALE/ PROG( INT0) P 3 . 21229PSEN( INT1) P 3 . 31328P2. 7 ( A15) INDEX( T 0 ) P 3 . 41427P2. 6 ( A14) CORNER( T 1 ) P 3 . 51526P2. 5 ( A13) ( W R ) P 3 . 61625P2. 4 ( A12) ( R D ) P 3 . 71724P2. 3 ( A11) 4442403836344341393735XTAL21823P2. 2 ( A10) P 1 . 5133P0. 4 ( AD4) X TAL11922P2. 1 ( A 9 ) P 1 . 6232P0. 5 ( AD5) GND2021P2. 0 ( A 8 ) P 1 . 7331P0. 6 ( AD6) RST430P0. 7 ( AD7) ( RXD) P 3 . 0529EA/ VPPNC628NCPLCC ( TXD) P 3 . 1727ALE/ PROG( INT0) P 3 . 2826PSEN( INT1) P 3 . 3925P2. 7 ( A15) ( T 0 ) P 3 . 41024P2. 6 ( A14) ( T 1 ) P 3 . 51123P2. 5 ( A13) INDEX1315171921CORNER121416182022642444240P1. 57531434139P0. 4 ( AD4) P 1 . 6838P0. 5 ( AD5) P 1 . 7937P0. 6 ( AD6) RST1036P0. 7 ( AD7) ( RXD) P 3 . 01135EA/ VPPNC1234NC( TXD) P 3 . 11333ALE/ PROG( INT0) P 3 . 21432PSEN( INT1) P 3 . 31531P2. 7 ( A15) ( T 0 ) P 3 . 41630P2. 6 ( A14) ( T 1 ) P 3 . 517192123252729P2. 5 ( A13) 182022242628( W R ) P 3 . 6P1. 4 ( R D ) P 3 . 7P1. 3 X TAL2P1. 2 X TAL1P1. 1GNDP1. 0GNDNC( A 8 ) P 2 . 0VCC( A 9 ) P 2 . 1P0. 0 ( AD0) ( A10) P 2 . 2P0. 1 ( AD1) ( A11) P 2 . 3P0. 2 ( AD2) ( A12) P 2 . 4P0. 3 ( AD3) ( W R ) P 3 . 6P1. 4 ( R D ) P 3 . 7P1. 3 X TAL2P1. 2 X TAL1P1. 1GNDP1. 0NCNC( A 8 ) P 2 . 0VCC( A 9 ) P 2 . 1P0. 0 ( AD0) ( A10) P 2 . 2P0. 1 ( AD1) ( A11) P 2 . 3P0. 2 ( AD2) ( A12) P 2 . 4P0. 3 ( AD3), Block Diagram 2 AT89LV51, The AT89LV51 provides the following standard features: when emitting 1s. During accesses to external data mem- 4K bytes of Flash, 128 bytes of RAM, 32 I/O lines, two 16 ory that use 8-bit addresses (MOVX @ RI), Port 2 emits the bit timer/counters, a five vector two-level interrupt architec- contents of the P2 Special Function Register. ture, a full duplex serial port, on-chip oscillator and clock Port 2 also receives the high-order address bits and some circuitry. In addition, the AT89LV51 is designed with static control signals during Flash programming and verification. logic for operation down to zero frequency and supports two software selectable power saving modes. The Idle Port 3 Mode stops the CPU while allowing the RAM, timer/ Port 3 is an 8-bit bidirectional I/O port with internal pullups. counters, serial port and interrupt system to continue func- The Port 3 output buffers can sink/source four TTL inputs. tioning. The Power Down Mode saves the RAM contents When 1s are written to Port 3 pins they are pulled high by but freezes the oscillator disabling all other chip functions the internal pullups and can be used as inputs. As inputs, until the next hardware reset. Port 3 pins that are externally being pulled low will source current (IIL) because of the pullups.

Pin Description Port 3 also serves the functions of various special features

of the AT89LV51 as listed below:

VCC

Supply voltage. Port Pin Alternate Functions

GND

Ground. P3.0 RXD (serial input port) Port 0 P3.1 TXD (serial output port) Port 0 is an 8-bit open drain bidirectional I/O port. As an P3.2 INT0 (external interrupt 0) output port each pin can sink eight TTL inputs. When 1s are written to port 0 pins, the pins can be used as high- P3.3 INT1 (external interrupt 1) impedance inputs. P3.4 T0 (timer 0 external input) Port 0 may also be configured to be the multiplexed low- P3.5 T1 (timer 1 external input) order address/data bus during accesses to external pro- gram and data memory. In this mode P0 has internal pul- P3.6 WR (external data memory write strobe) lups. P3.7 RD (external data memory read strobe) Port 0 also receives the code bytes during Flash program- ming, and outputs the code bytes during program verifica- Port 3 also receives some control signals for Flash pro- tion. External pullups are required during program verifica- gramming and verification. tion. RST Port 1 Reset input. A high on this pin for two machine cycles while Port 1 is an 8 bit bidirectional I/O port with internal pullups. the oscillator is running resets the device. The Port 1 output buffers can sink/source four TTL inputs. ALE/PROG When 1s are written to Port 1 pins they are pulled high by Address Latch Enable output pulse for latching the low byte the internal pullups and can be used as inputs. As inputs, of the address during accesses to external memory. This Port 1 pins that are externally being pulled low will source pin is also the program pulse input (PROG) during Flash current (IIL) because of the internal pullups. programming. Port 1 also receives the low-order address bytes during In normal operation ALE is emitted at a constant rate of 1/ Flash programming and verification. 6 the oscillator frequency, and may be used for external Port 2 timing or clocking purposes. Note, however, that one ALE Port 2 is an 8-bit bidirectional I/O port with internal pullups. pulse is skipped during each access to external Data Mem- The Port 2 output buffers can sink/source four TTL inputs. ory. When 1s are written to Port 2 pins they are pulled high by PSEN the internal pullups and can be used as inputs. As inputs, Program Store Enable is the read strobe to external pro- Port 2 pins that are externally being pulled low will source gram memory. current (IIL) because of the internal pullups. When the AT89LV51 is executing code from external pro- Port 2 emits the high-order address byte during fetches gram memory, PSEN is activated twice each machine from external program memory and during accesses to cycle, except that two PSEN activations are skipped during external data memory that use 16 bit addresses (MOVX @ each access to external data memory. DPTR). In this application it uses strong internal pullups, EA/VPP Special Function Registers External Access Enable. EA must be strapped to GND in A map of the on-chip memory area called the Special Func- order to enable the device to fetch code from external pro- tion Register (SFR) space is shown in Table 1. gram memory locations starting at 0000H up to FFFFH. Note, however, that if lock bit 1 is programmed, EA will be Note that not all of the addresses are occupied, and unoc- internally latched on reset. cupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return EA should be strapped to VCC for internal program execu- random data, and write accesses will have an indetermi- tions. nate effect. This pin also receives the 12-volt programming enable volt- User software should not write 1s to these unlisted loca- age (VPP) during Flash programming, when 12-volt pro- tions, since they may be used in future products to invoke gramming is selected. new features. In that case, the reset or inactive values of XTAL1 the new bits will always be 0. Input to the inverting oscillator amplifier and input to the Timer 0 and 1 internal clock operating circuit. Timer 0 and Timer 1 in the AT89LV51 operate the same XTAL2 way as Timer 0 and Timer 1 in the AT89C51. Output from the inverting oscillator amplifier. Table 1. AT89LV51 SFR Map and Reset Values 0F8H 0FFH 0F0H B00000000 0F7H 0E8H 0EFH 0E0H ACC00000000 0E7H 0D8H 0DFH 0D0H PSW00000000 0D7H 0C8H T2CON T2MOD RCAP2L RCAP2H TL2 TH200000000 XXXXXX00 00000000 00000000 00000000 00000000 0CFH 0C0H 0C7H 0B8H IPXX000000 0BFH 0B0H P311111111 0B7H 0A8H IE0X000000 0AFH 0A0H P211111111 0A7H 98H SCON SBUF00000000 XXXXXXXX 9FH 90H P111111111 97H 88H TCON TMOD TL0 TL1 TH0 TH100000000 00000000 00000000 00000000 00000000 00000000 8FH 80H P0 SP DPL DPH PCON11111111 00000111 00000000 00000000 0XXX0000 87H 4 AT89LV51,

Oscillator Characteristics

XTAL1 and XTAL2 are the input and output, respectively, Figure 1. Oscillator Connections of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz C2 crystal or ceramic resonator may be used. To drive the XTAL2 device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. There are no requirements on the duty cycle of the external C1 XTAL1 clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maxi- mum voltage high and low time specifications must be observed GND

Idle Mode

In idle mode, the CPU puts itself to sleep while all the on- chip peripherals remain active. The mode is invoked by Notes: C1, C2 = 30 pF ± 10 pF for Crystals software. The content of the on-chip RAM and all the spe- = 40 pF ± 10 pF for Ceramic Resonators cial functions registers remain unchanged during this mode. The idle mode can be terminated by any enabled interrupt or by a hardware reset. Figure 2. External Clock Drive Configuration It should be noted that when idle is terminated by a hard- ware reset, the device normally resumes program execu- NC XTAL2 tion, from where it left off, up to two machine cycles before the internal reset algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to EXTERNAL the port pins is not inhibited. To eliminate the possibility of OSCILLATOR XTAL1 an unexpected write to a port pin when Idle is terminated by SIGNAL reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external GND memory.,

Status of External Pins During Idle and Power Down

Mode Program Memory ALE PSEN PORT0 PORT1 PORT2 PORT3 Idle Internal11Data Data Data Data Idle External11Float Data Address Data Power Down Internal00Data Data Data Data Power Down External00Float Data Data Data

Power Down Mode Reset redefines the SFRs but does not change the on-chip

RAM. The reset should not be activated before V is In the power down mode the oscillator is stopped, and the CCrestored to its normal operating level and must be held instruction that invokes power down is the last instruction active long enough to allow the oscillator to restart and sta- executed. The on-chip RAM and Special Function Regis- bilize. ters retain their values until the power down mode is termi- nated. The only exit from power down is a hardware reset.

Lock Bit Protection Modes (1)

Program Lock Bits LB1 LB2 LB3 Protection Type1UUUNo program lock features. 2PUUMOVC instructions executed from external program memory are disabled from fetching code bytes from internal memory, EA is sampled and latched on reset, and further programming of the Flash is disabled. 3PPUSame as mode 2, also verify is disabled. 4PPPSame as mode 3, also external execution is disabled. Note: 1. The lock bits can only be erased with the Chip Erase operation.

Program Memory Lock Bits

On the chip are three lock bits which can be left unpro- VPP = 12V grammed (U) or can be programmed (P) to obtain the addi- AT89LV51 tional features listed in the table below: Top-Side Mark xxxx When lock bit 1 is programmed, the logic level at the EA pin yyww is sampled and latched during reset. If the device is pow- (030H)=1EH ered up without a reset, the latch initializes to a random value, and holds that value until reset is activated. It is nec- Signature (031H)=61H essary that the latched value of EA be in agreement with (032H)=FFH the current logic level at that pin in order for the device to The AT89LV51 code memory array is programmed byte- function properly. by-byte. To program any non-blank byte in the on-chip Flash Code Memory, the entire memory must be erased

Programming the Flash using the Chip Erase Mode.

The AT89LV51 is normally shipped with the on-chip Flash Programming Algorithm: Before programming the memory array in the erased state (i.e. contents=FFH) and AT89LV51, the address, data and control signals should be ready to be programmed. set up according to the Flash programming mode table and Figure 2 and Figure 3. To program the AT89LV51, the fol- The respective top-side marking and device signature lowing sequence should be followed: codes are listed below: 1. Input the desired memory location on the address lines. 2. Input the appropriate data byte on the data lines. 3. Activate the correct combination of control signals. 6 AT89LV51, 4. Raise EA/VPP to 12V if in the high-voltage programming mode. Chip Erase: The entire Flash array and the lock bits are 5. Pulse ALE/PROG once to program a byte in the Flash erased electrically by using the proper combination of con- array or the lock bits. The byte-write cycle is self-timed trol signals and by holding ALE/PROG low for 10 ms. The and typically takes no more than 1.5 ms. Repeat steps 1 code array is written with all “1”s. The chip erase operation through 5 changing the address and data for the entire must be executed before the code memory can be re-pro- array or until the end of the object file is reached. grammed. Data Polling: The AT89LV51 features Data Polling to indi- Reading the Signature Bytes: The signature bytes are cate the end of a write cycle. During a write cycle, an read by the same procedure as a normal verification of attempted read of the last byte written will result in the com- locations 030H and 031H, except that P3.6 and P3.7 need plement of the written data on PO.7. Once the write cycle to be pulled to a logic low. The values returned are: has been completed, true data is valid on all outputs, and (030H) = 1EH indicates manufactured by Atmel the next cycle may begin. Data Polling may begin any time (031H) = 61H indicates 89LV51 after a write cycle has been initiated. (032H) = FFH (High-Voltage) Ready/Busy: The progress of byte programming can also be monitored by the RDY/BSY output signal. P3.4 is pulled low after ALE goes high during programming to indicate Programming Interface BUSY. P3.4 is pulled high again when programming is Every code byte in the Flash array can be written and the done to indicate READY. entire array can be erased by using the appropriate combi- Program Verify: If lock bits LB1 and LB2 have not been nation of control signals. The write operation cycle is self- programmed, the programmed code data can be read back timed and once initiated, will automatically time itself to via the address and data lines for verification. The lock bits completion. cannot be verified directly. Verification of the lock bits is All major programming vendors offer worldwide support for achieved by observing that their features are enabled. the Atmel microcontroller series. Please contact your local programming vendor for the appropriate software revision.

Flash Programming Modes

ALE/ Mode RST PSEN EA/VPP P2.6 P2.7 P3.6 P3.7PROG Write Code DataHLH/12VLHHHRead Code DataHLHHLLHHWrite Lock Bit - 1HLH/12VHHHHBit - 2HLH/12VHHLLBit - 3HLH/12VHLHL(1) Chip EraseHLH/12VHLLLRead Signature ByteHLHHLLLLNote: 1. Chip Erase requires a 10 ms PROG pulse., Figure 2. Programming the Flash Figure 3. Verifying the Flash

Flash Programming and Verification Characteristics

TA = 0°C to 70°C, VCC = 5.0V ± 10% Symbol Parameter Min Max Units V (1)PP Programming Enable Voltage 11.5 12.5VI(1)PP Programming Enable Current 25 µA 1/tCLCL Oscillator Frequency 4 12 MHz tAVGL Address Setup to PROG Low 48tCLCL tGHAX Address Hold After PROG 48tCLCL tDVGL Data Setup to PROG Low 48tCLCL tGHDX Data Hold After PROG 48tCLCL tEHSH P2.7 (ENABLE) High to VPP 48t CLCL tSHGL VPP Setup to PROG Low 10 µs t (1)GHSL VPP Hold After PROG 10 µs tGLGH PROG Width 1 110 µs tAVQV Address to Data Valid 48t CLCL tELQV ENABLE Low to Data Valid 48tCLCL tEHQZ Data Float After ENABLE 0 48tCLCL tGHBL PROG High to BUSY Low 1.0 µs tWC Byte Write Cycle Time 2.0 ms Note: 1. Only used in 12-volt programming mode. 8 AT89LV51,

Flash Programming and Verification Waveforms - High Voltage Mode (VPP = 12V)

PROGRAMMING VERIFICATION P1.0 - P1.7 P2.0 - P2.3 ADDRESS ADDRESS tAVQV PORT 0 DATA IN DATA OUT tDVGL tGHDX tAVGL tGHAX ALE/PROG tSHGL tt GHSLGLGH VPP LOGIC 1 EA/VPP LOGIC 0 tEHSH t tEHQZP2.7 ELQV (ENABLE) tGHBL P3.4 (RDY/BSY) BUSY READY tWC

Flash Programming and Verification Waveforms - Low Voltage Mode (VPP = 5V)

PROGRAMMING VERIFICATION P1.0 - P1.7 P2.0 - P2.3 ADDRESS ADDRESS tAVQV PORT 0 DATA IN DATA OUT tDVGL tGHDX tAVGL tGHAX ALE/PROG tSHGL tGLGH LOGIC 1 EA/VPP LOGIC 0 tEHSH t tEHQZP2.7 ELQV (ENABLE) tGHBL P3.4 (RDY/BSY) BUSY READY tWC,

Absolute Maximum Ratings*

*NOTICE: Stresses beyond those listed under “Absolute Maxi- Operating Temperature ... -55°C to +125°C mum Ratings” may cause permanent damage to the device. This is a stress rating only and functional Storage Temperature... -65°C to +150°C operation of the device at these or any other condi- tions beyond those indicated in the operational sec- Voltage on Any Pin tions of this specification is not implied. Exposure to with Respect to Ground... -1.0V to +7.0V absolute maximum rating conditions for extended periods may affect device reliability. Maximum Operating Voltage ...6.6V DC Output Current ...15.0 mA

DC Characteristics

TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted) Symbol Parameter Condition Min Max Units VIL Input Low Voltage (Except EA) -0.5 0.2 VCC - 0.1 V VIL1 Input Low Voltage (EA) -0.5 0.2 VCC - 0.3 V VIH Input High Voltage (Except XTAL1, RST) 0.2 VCC + 0.9 VCC + 0.5 V VIH1 Input High Voltage (XTAL1, RST) 0.7 VCC VCC + 0.5 V (1) V Output Low VoltageOL (Ports 1,2,3) IOL = 1.6 mA 0.45VVOutput Low Voltage (1) OL1 (Port 0, ALE, PSEN) IOL = 3.2 mA 0.45 V IOH = -60 µA, VCC = 5V ± 10% 2.4VVOutput High VoltageOH (Ports 1,2,3, ALE, PSEN) IOH = -20 µA 0.75 VCC V IOH = -10 µA 0.9 VCC V IOH = -800 µA, VCC = 5V ± 10% 2.4VVOutput High VoltageOH1 (Port 0 in External Bus Mode) IOH = -300 µA 0.75 VCC V IOH = -80 µA 0.9 VCCVILogical 0 Input CurrentIL (Ports 1,2,3) VIN = 0.45V -50 µA I Logical 1 to 0 Transition Current TL (Ports 1,2,3) VIN = 2V, VCC = 5V ± 10% -650 µA I Input Leakage Current LI (Port 0, EA) 0.45 < VIN < VCC ±10 µA RRST Reset Pulldown Resistor 50 300 KΩ CIO Pin Capacitance Test Freq. = 1 MHz, TA = 25°C 10 pF Active Mode, 12 MHz, VCC = 6V/3V 20/5.5 mA Power Supply Current Idle Mode, 12 MHz, VCC = 6V/3V 5/1 mA

ICC

VCC = 6V 100 µA Power Down Mode (2) VCC = 3V 20 µA 10 AT89LV51,

AC Characteristics

Under operating conditions, load capacitance for Port 0, ALE/PROG, and PSEN = 100 pF; load capacitance for all other outputs = 80 pF.

External Program and Data Memory Characteristics

12 MHz Oscillator Variable Oscillator Symbol Parameter Units Min Max Min Max 1/tCLCL Oscillator Frequency 0 12 MHz tLHLL ALE Pulse Width 127 2tCLCL-40 ns tAVLL Address Valid to ALE Low 43 tCLCL-40 ns tLLAX Address Hold After ALE Low 48 tCLCL-35 ns tLLIV ALE Low to Valid Instruction In 233 4tCLCL-100 ns tLLPL ALE Low to PSEN Low 43 tCLCL-40 ns tPLPH PSEN Pulse Width 205 3tCLCL-45 ns tPLIV PSEN Low to Valid Instruction In 145 3tCLCL-105 ns tPXIX Input Instruction Hold After PSEN00ns tPXIZ Input Instruction Float After PSEN 59 tCLCL-25 ns tPXAV PSEN to Address Valid 75 tCLCL-8 ns tAVIV Address to Valid Instruction In 312 5tCLCL-105 ns tPLAZ PSEN Low to Address Float 10 10 ns tRLRH RD Pulse Width 400 6tCLCL-100 ns tWLWH WR Pulse Width 400 6tCLCL-100 ns tRLDV RD Low to Valid Data In 252 5tCLCL-165 ns tRHDX Data Hold After RD00ns tRHDZ Data Float After RD 97 2tCLCL-70 ns tLLDV ALE Low to Valid Data In 517 8tCLCL-150 ns tAVDV Address to Valid Data In 585 9tCLCL-165 ns tLLWL ALE Low to RD or WR Low 200 300 3tCLCL-50 3tCLCL+50 ns tAVWL Address to RD or WR Low 203 4tCLCL-130 ns tQVWX Data Valid to WR Transition 23 tCLCL-60 ns tQVWH Data Valid to WR High 433 7tCLCL-150 ns tWHQX Data Hold After WR 33 tCLCL-50 ns tRLAZ RD Low to Address Float00ns tWHLH RD or WR High to ALE High 43 123 tCLCL-40 tCLCL+40 ns,

External Program Memory Read Cycle

tLHLL

ALE

tPLPH tAVLL tt LLIVLLPL PSEN tPLIVttPXAVPLAZttPXIZLLAX tPXIX PORT 0 A0 - A7 INSTR IN A0 - A7 tAVIV PORT 2 A8 - A15 A8 - A15

External Data Memory Read Cycle

tLHLL

ALE

tWHLH

PSEN

tLLDV tRLRH tLLWL RD tLLAXttRLDV tRHDZ AVLL tRLAZ tRHDX PORT 0 A0 - A7 FROM RI OR DPL DATA IN A0 - A7 FROM PCL INSTR IN tAVWL tAVDV PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH 12 AT89LV51,

External Data Memory Cycle

tLHLL

ALE

tWHLH

PSEN

tLLWL tWLWH WR tLLAX t tAVLL QVWX tWHQX tQVWH PORT 0 A0 - A7 FROM RI OR DPL DATA OUT A0 - A7 FROM PCL INSTR IN tAVWL PORT 2 P2.0 - P2.7 OR A8 - A15 FROM DPH A8 - A15 FROM PCH

External Clock Drive Waveforms

tCHCX tCHCX tCLCH tCHCLVCC- 0.5V 0.7 VCC 0.2 VCC - 0.1V 0.45V tCLCX tCLCL

External Clock Drive

Symbol Parameter Min Max Units 1/tCLCL Oscillator Frequency 0 12 MHz tCLCL Clock Period 83.3 ns tCHCX High Time 20 ns tCLCX Low Time 20 ns tCLCH Rise Time 20 ns tCHCL Fall Time 20 ns,

Serial Port Timing: Shift Register Mode Test Conditions

(VCC = 2.7V to 6V; Load Capacitance = 80 pF) 12 MHz Osc Variable Oscillator Symbol Parameter Units Min Max Min Max tXLXL Serial Port Clock Cycle Time 1.0 12tCLCL µs tQVXH Output Data Setup to Clock Rising Edge 700 10tCLCL-133 ns tXHQX Output Data Hold After Clock Rising Edge 50 2tCLCL-117 ns tXHDX Input Data Hold After Clock Rising Edge00ns tXHDV Clock Rising Edge to Input Data Valid 700 10t CLCL-133 ns

Shift Rgister Mode Timing Waveforms

INSTRUCTION012345678

ALE

tXLXL

CLOCK

tQVXH tXHQX WRITE TO SBUF01234567tXHDX OUTPUT DATA t SET TIXHDV CLEAR RI VALID VALID VALID VALID VALID VALID VALID VALID INPUT DATA SET RI

AC Testing Input/Output Waveforms (1) Float Waveforms (1)

VCC- 0.5V 0.2 VC C + 0.9V V + 0.1V - 0.1V LOAD VOL TEST POINTS V Timing ReferenceLOAD Points 0.2 VC C - 0.1V V - 0.1V V + 0.1V0.45V LOAD OL Note: 1. AC inputs during testing are driven at 2.4V for a Note: 1. For timing purposes, a port pin is no longer floating logic "1" and 0.45V for a logic "0". Timing measure- when a 100 mV change from load voltage occurs. A ments are made at 2.0V for a logic "1" and 0.8V for a port pin begins to float when a 100 mV change from logic "0". the loaded VOH/VOL level occurs. 14 AT89LV51,

AT89LV51

ICC (mA) TYPICAL ICC (ACTIVE) at 25oCVCC = 6.0 V 12 VCC = 5.0V4VCC = 3.0V04812 16 20 24 F (MHz)

AT89LV51

ICC (mA) TYPICAL ICC (IDLE) at 25oC4.8 VCC = 6.0 V 4.0 3.2 2.4 VCC = 5.0 V 1.6 0.8 VCC = 3.0 V 0.004812 16 20 24 F (MHz)

AT89LV51

TYPICAL ICC vs. VOLTAGE- POWER DOWN (85°C) I 15

C C

µA53.0V 4.0V 5.0V 6.0V

Vcc VOLTAGE

,

Ordering Information

Speed Power Supply Ordering Code Package Operation Range (MHz) 12 2.7V to 6V AT89LV51-12AC 44A AT89LV51-12JC 44J Commercial AT89LV51-12PC 40P6 (0°C to 70°C) 12 2.7V to 6V AT89LV51-12AI 44A AT89LV51-12JI 44J Industrial AT89LV51-12PI 40P6 (-40°C to 85°C) Package Type 44A 44 Lead, Thin Plastic Gull Wing Quad Flatpack (TQFP) 44J 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40P6 40 Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 16 AT89LV51]
15

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