Download: GENERAL DESCRIPTION QUICK REFERENCE DATA PINNING - SOT223 PIN CONFIGURATION SYMBOL
GENERAL DESCRIPTION QUICK REFERENCE DATA Glass passivated, sensitive gate SYMBOL PARAMETER MAX. UNIT thyristor in a plastic envelope, suitable for surface mounting, intended for use VDRM, Repetitive peak off-state voltages 400 V in general purpose switching and VRRM phase control applications. This IT(AV) Average on-state current 0.6 A device is intended to be interfaced IT(RMS) RMS on-state current1Adirectly to microcontrollers, logic ITSM Non-repetitive peak on-state current8Aintegrated circuits and other low power gate trigger circuits. PINNING - SOT223 PIN CONFIGURATION SYMBOL PIN DESCRIPT...
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GENERAL DESCRIPTION QUICK REFERENCE DATA
Glass passivated, sensitive gate SYMBOL PARAMETER MAX. UNIT thyristor in a plastic envelope, suitable for surface mounting, intended for use VDRM, Repetitive peak off-state voltages 400 V in general purpose switching and VRRM phase control applications. This IT(AV) Average on-state current 0.6 A device is intended to be interfaced IT(RMS) RMS on-state current1Adirectly to microcontrollers, logic ITSM Non-repetitive peak on-state current8Aintegrated circuits and other low power gate trigger circuits.PINNING - SOT223 PIN CONFIGURATION SYMBOL
PIN DESCRIPTION 1 cathodeak2anode 3 gate tab anode123gLIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134). SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT VDRM. VRRM Repetitive peak off-state - 4001Vvoltages IT(AV) Average on-state current half sine wave; Tsp ≤ 112 ˚C - 0.63 A IT(RMS) RMS on-state current all conduction angles - 1 A ITSM Non-repetitive peak half sine wave; Tj = 125 ˚C prior to surge; on-state current with reapplied VDRM(max) t = 10 ms - 8At= 8.3 ms - 9 A I2t I2t for fusing t = 10 ms - 0.32 A2s dIT/dt Repetitive rate of rise of ITM = 2 A; IG = 10 mA; dIG/dt = 100 mA/µs - 50 A/µs on-state current after triggering IGM Peak gate current - 1 A VGM Peak gate voltage - 5 V VRGM Peak reverse gate voltage - 5 V PGM Peak gate power - 2 W PG(AV) Average gate power over any 20 ms period - 0.1 W Tstg Storage temperature -40 150 ˚C Tj Operating junction - 125 ˚C temperature 1 Although not recommended, off-state voltages up to 800V may be applied without damage, but the thyristor may switch to the on-state. The rate of rise of current should not exceed 15 A/µs. February 1996 1 Rev 1.100,THERMAL RESISTANCES
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Rth j-sp Thermal resistance - - 15 K/W junction to solder point Rth j-a Thermal resistance pcb mounted, minimum footprint - 156 - K/W junction to ambient pcb mounted; pad area as in fig:14 - 70 - K/WSTATIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise stated SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT IGT Gate trigger current VD = 12 V; IT = 10 mA; gate open circuit - 50 200 µA IL Latching current VD = 12 V; IGT = 0.5 mA; RGK = 1 kΩ - 2 6 mA IH Holding current VD = 12 V; IGT = 0.5 mA; RGK = 1 kΩ - 2 5 mA VT On-state voltage IT = 2 A - 1.35 1.5 V VGT Gate trigger voltage VD = 12 V; IT = 10 mA; gate open circuit - 0.5 0.8 V VD = VDRM(max); IT = 10 mA; Tj = 125 ˚C; 0.2 0.3 - V gate open circuit ID, IR Off-state leakage current VD = VDRM(max); VR = VRRM(max); Tj = 125 ˚C; - 0.05 0.1 mA RGK = 1 kΩDYNAMIC CHARACTERISTICS
Tj = 25 ˚C unless otherwise stated SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT dVD/dt Critical rate of rise of VDM =67% VDRM(max); Tj = 125 ˚C; - 25 - V/µs off-state voltage exponential waveform; RGK = 1k Ω tgt Gate controlled turn-on ITM = 2 A; VD = VDRM(max); IG = 10 mA; - 2 - µs time dIG/dt = 0.1 A/µs tq Circuit commutated VD = 67% VDRM(max); Tj = 125 ˚C; - 100 - µs turn-off time ITM = 1.6 A; VR = 35 V; dITM/dt = 30 A/µs; dVD/dt = 2 V/µs; RGK = 1 kΩ February 1996 2 Rev 1.100, Ptot / W BT169W Tsp(max) / C ITSM / A BT169 1 110 10 conduction form angle factor a = 1.57 I ITSM degreesaT0.8 4 1.960 2.8 113 82.2 T time 90 2.2 120 1.9 2.8 Tj initial = 125 C max 0.6 180 1.57 4 116 6 0.4 119 4 0.2 12220125 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 01 10 100 1000 IF(AV) / A Number of half cycles at 50HzFig.1. Maximum on-state dissipation, Ptot, versus Fig.4. Maximum permissible non-repetitive peak
average on-state current, IT(AV), where a = form on-state current ITSM, versus number of cycles, for factor = IT(RMS)/ IT(AV). sinusoidal currents, f = 50 Hz. ITSM / A BT169 IT(RMS) / A BT134W 1000 2 1.5 10 I IT TSM 0.5 T time Tj initial = 125 C max 10us 100us 1ms 10ms 00.01 0.1 1 10 T / s surge duration / sFig.2. Maximum permissible non-repetitive peak Fig.5. Maximum permissible repetitive rms on-state
on-state current ITSM, versus pulse width tp, for current IT(RMS), versus surge duration, for sinusoidal sinusoidal currents, tp ≤ 10ms. currents, f = 50 Hz; Tsp ≤ 112˚C. IT(RMS) / A BT134W VGT(Tj) 1.2 VGT(25 C) BT151 1.6 112 C 1.4 0.8 1.2 0.6 1 0.4 0.8 0.2 0.6 -50 0 50 100 150 0.4-50 0 50 100 150 Tsp / C Tj / CFig.3. Maximum permissible rms current IT(RMS) , Fig.6. Normalised gate trigger voltage
versus solder point temperature Tsp. VGT(Tj)/ VGT(25˚C), versus junction temperature Tj.February 1996 3 Rev 1.100
, IGT(Tj) IT / A BT169W IGT(25 C) BT16953Tj = 125 C Tj = 25 C 2.5 4 Vo = 1.0 V Rs = 0.27 Ohms231.5 2 typ max 0.500-50 0 50 100 150 0 0.5 1 1.5 2 2.5 Tj / C VT / VFig.7. Normalised gate trigger current Fig.10. Typical and maximum on-state characteristic. IGT(Tj)/ IGT(25˚C), versus junction temperature Tj.
IL(Tj) Zth j-sp (K/W) BT169W IL(25 C) BT169 100 2.5 10 1.5 P tp1D0.1 0.5t00.01 -50 0 50 100 150 10us 0.1ms 1ms 10ms 0.1s 1s 10s Tj / C tp / sFig.8. Normalised latching current IL(Tj)/ IL(25˚C), Fig.11. Transient thermal impedance Zth j-sp, versus
versus junction temperature Tj, RGK = 1 kΩ. pulse width tp. IH(Tj) dVD/dt (V/us)1000 IH(25 C) BT169 2.5 2 RGK = 1 kohms 1.5 1 10 0.501-50 0 50 100 150 0 50 100 150 Tj / C Tj / CFig.9. Normalised holding current IH(Tj)/ IH(25˚C), Fig.12. Typical, critical rate of rise of off-state voltage,
versus junction temperature Tj, RGK = 1 kΩ. dVD/dt versus junction temperature Tj.February 1996 4 Rev 1.100
,MOUNTING INSTRUCTIONS PRINTED CIRCUIT BOARD
Dimensions in mm. Dimensions in mm. 3.8 36 4.6 4.5 2.3 6.3 (3x) 4.6 7 Fig.13. soldering pattern for surface mounting Fig.14. PCB for thermal resistance and power rating SOT223. for SOT223. PCB: FR4 epoxy glass (1.6 mm thick), copper laminate (35 µm thick). February 1996 5 Rev 1.100,MECHANICAL DATA
Dimensions in mm 6.7 6.3 Net Mass: 0.11gB0.32 3.1 0.24 2.9 0.2MA4A0.10 0.02 3.7 7.3 3.3 6.7 16 13 max123max 1.8 1.05 2.3 0.80 max 0.1 M B0.85 0.60 (4x) 4.6 Fig.15. SOT223 surface mounting package. Notes 1. For further information, refer to surface mounting instructions for SOT223 envelope. 2. Epoxy meets UL94 V0 at 1/8". February 1996 6 Rev 1.100,DEFINITIONS
Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. Philips Electronics N.V. 1996 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. February 1996 7 Rev 1.100]15
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