Download: Data Sheet No. PD60173-E HALF-BRIDGE DRIVER Features • Floating channel designed for bootstrap operation Packages • Gate drive supply range from 10 to 20V 8-Lead SOIC

Data Sheet No. PD60173-E HALF-BRIDGE DRIVER Features

• Floating channel designed for bootstrap operation Packages Fully operational to +600V Tolerant to negative transient voltage 14-Lead PDIP dV/dt immune IR21834 • Gate drive supply range from 10 to 20V 8-Lead SOIC • Undervoltage lockout for both channels IR2183S • 3.3V and 5V input logic compatible • Matched propagation delay for both channels • Logic and power ground +/- 5V offset. • 8-Lead PDIPLower di/dt gate driver for better noise immunity • IR2183Output source/sink current capability 1.4A/1.8A 14-Lead SOIC IR21834S

Description

The IR2183(4)(S) are high voltage, IR2181/IR2183/IR2184 Feature Comparison high speed power MOSFET and IGBT drivers with dependent high and low side referenced output channels. Pro- prietary HVIC and latch immune CMOS technologies enable rugge- !"#" && $%% dized monolithic construction. The ' (&& !"#" ) && logic input is compatible with standard ' &* +( $%% (&& CMOS or LSTTL output, down to 3.3V "% ) ,&-& &* +( $%% logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which operates up to 600 volts.

Typical Connection

up to 600V

VCC

VCC VB HIN HIN HO LIN LIN V TOS LOAD COM LO up to 600V IR2183 HO IR21834VVVCC CC B HIN HIN VS TO LIN LIN LOAD (Refer to Lead Assignment for correct pin DT configuration) This/These diagram(s) showVVCOMSS SS electrical connections only. Please refer to our RDT LO Application Notes and DesignTips for proper circuit board layout. www.irf.com 1,

Absolute Maximum Ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param- eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured under board mounted and still air conditions.

Symbol Definition Min. Max. Units

VB High side floating absolute voltage -0.3 625 VS High side floating supply offset voltage VB - 25 VB + 0.3 VHO High side floating output voltage VS - 0.3 VB + 0.3 VCC Low side and logic fixed supply voltage -0.3 25

V

VLO Low side output voltage -0.3 VCC + 0.3 DT Programmable dead-time pin voltage (IR21834 only) VSS - 0.3 VCC + 0.3 VIN Logic input voltage (HIN & LIN) VSS - 0.3 VSS + 10 VSS Logic ground (IR21834 only) VCC - 25 VCC + 0.3 dVS/dt Allowable offset supply voltage transient — 50 V/ns PD Package power dissipation @ TA ≤ +25°C (8-lead PDIP) — 1.0 (8-lead SOIC) — 0.625 (14-lead PDIP) — 1.6 W (14-lead SOIC) — 1.0 RthJA Thermal resistance, junction to ambient (8-lead PDIP) — 125 (8-lead SOIC) — 200 (14-lead PDIP) — 75 °C/W (14-lead SOIC) — 120 TJ Junction temperature — 150 TS Storage temperature -50 150 °C TL Lead temperature (soldering, 10 seconds) — 300

Recommended Operating Conditions

The Input/Output logic timing diagram is shown in figure 1. For proper operation the device should be used within the recommended conditions. The VS and VSS offset rating are tested with all supplies biased at 15V differential.

Symbol Definition Min. Max. Units

VB High side floating supply absolute voltage VS + 10 VS + 20 VS High side floating supply offset voltage Note 1 600 VHO High side floating output voltage VS VB VCC Low side and logic fixed supply voltage 10 20 VLO Low side output voltage 0 VCC V VIN Logic input voltage (HIN & LIN) VSS VSS + 5 DT Programmable dead-time pin voltage (IR21834 only) VSS VCC VSS Logic ground (IR21834 only) -5 5 TA Ambient temperature -40 125 °C Note 1: Logic operational for VS of -5 to +600V. Logic state held for VS of -5V to -VBS. (Please refer to the Design Tip DT97-3 for more details). Note 2: HIN and LIN pins are internally clamped with a 5.2V zener diode. 2 www.irf.com,

Dynamic Electrical Characteristics

VBIAS (VCC, VBS) = 15V, VSS = COM, CL = 1000 pF, TA = 25°C, DT = VSS unless otherwise specified.

Symbol Definition Min. Typ. Max. Units Test Conditions

ton Turn-on propagation delay — 180 270 VS = 0V toff Turn-off propagation delay — 220 330 VS = 0V or 600V MT Delay matching | ton - toff | — 0 35 nsec tr Turn-on rise time — 40 60 VS = 0V tf Turn-off fall time — 20 35 VS = 0V DT Deadtime: LO turn-off to HO turn-on(DTLO-HO) & 280 400 520 RDT= 0 HO turn-off to LO turn-on (DTHO-LO) 456µsec RDT = 200k (IR21834) MDT Deadtime matching = | DTLO-HO - DTHO-LO | — 0 50 RDT=0 nsec — 0 600 RDT = 200k (IR21834)

Static Electrical Characteristics

VBIAS (VCC, VBS) = 15V, VSS = COM, DT= VSS and TA = 25°C unless otherwise specified. The VIL, VIH and IIN parameters are referenced to VSS/COM and are applicable to the respective input leads: HIN and LIN. The VO, IO and Ron parameters are referenced to COM and are applicable to the respective output leads: HO and LO.

Symbol Definition Min. Typ. Max. Units Test Conditions

VIH Logic “1” input voltage for HIN & logic “0” for LIN 2.7 — — VCC = 10V to 20V VIL Logic “0” input voltage for HIN & logic “1” for LIN — — 0.8 VCC = 10V to 20V

V

VOH High level output voltage, VBIAS - VO — — 1.2 IO = 0A VOL Low level output voltage, VO — — 0.1 IO = 0A ILK Offset supply leakage current — — 50 VB = VS = 600V IQBS Quiescent VBS supply current 20 60 150 µA VIN = 0V or 5V IQCC Quiescent VCC supply current 0.4 1.0 1.6 mA VIN = 0V or 5V IIN+ Logic “1” input bias current — 5 20 HIN = 5V, LIN = 0V IIN- Logic “0” input bias current — 1 2 µA HIN = 0V, LIN = 5V VCCUV+ VCC and VBS supply undervoltage positive going 8.0 8.9 9.8 VBSUV+ threshold VCCUV- VCC and VBS supply undervoltage negative going 7.4 8.2 9.0 V VBSUV- threshold VCCUVH Hysteresis 0.3 0.7 —

VBSUVH

IO+ Output high short circuit pulsed current 1.4 1.9 — VO = 0V, PW ≤ 10 µs

A

IO- Output low short circuit pulsed current 1.8 2.3 — VO = 15V, PW ≤ 10 µs www.irf.com 3,

Functional Block Diagrams

VBUV2183DETECTRHOHVPULSERQLEVELFILTERSSHIFTERHINVSS/ COMVSLEVELPULSESHIFTGENERATORDTDEADTIME& VCCSHOOT- THROUGHPREVENTIONUV+5VDETECTLOVSS/ COMLINLEVELDELAYSHIFTCOMVSSVB21834 U VDETECTRHOHVPULSERQLEVELFILTERSHINVSS/ COMSHIFTERLEVELVSPULSESHIFTGENERATORDEADTIME& DTVCCSHOOT- THROUGHPREVENTIONUV+5VDETECTLOVSS/ COMLINLEVELDELAYSHIFTCOMVSS4www.irf.com,

Lead Definitions Symbol Description

HIN Logic input for high side gate driver output (HO), in phase (referenced to COM for IR2183 and VSS for IR21834) LIN Logic input for low side gate driver output (LO), out of phase (referenced to COM for IR2183 and VSS for IR21834) DT Programmable dead-time lead, referenced to VSS. (IR21834 only) VSS Logic Ground (21834 only) VB High side floating supply HO High side gate driver output VS High side floating supply return VCC Low side and logic fixed supply LO Low side gate driver output COM Low side return

Lead Assignments

1 HIN VB81HIN VB82LIN HO72LIN HO73COM VS63COM VS64LO VCC54LO VCC 5 8-Lead PDIP 8-Lead SOIC IR2183 IR2183S 1 HIN 14 1 HIN 14 2 LIN VB 13 2 LIN VB 13 3 VSS HO 12 3 VSS HO 12 4 DT VS 11 4 DT VS 11 5 COM 10 5 COM 10 6 LO96LO97VCC87VCC 14-Lead PDIP 14-Lead SOIC IR21834 IR21834S www.irf.com 5,

Case outlines

01-6014 8-Lead PDIP 01-3003 01 (MS-001AB) INCHES MILLIMETERSDBDIM MIN MAX MIN MAXA5FOOTPRINT A .0532 .0688 1.35 1.75 A1 .0040 .0098 0.10 0.25 8X 0.72 [.028] b .013 .020 0.33 0.518765c.0075 .0098 0.19 0.256HD.189 .1968 4.80 5.00 E 0.25 [.010] A E .1497 .1574 3.80 4.0012346.46 [.255] e .050 BASIC 1.27 BASIC e1 .025 BASIC 0.635 BASIC H .2284 .2440 5.80 6.20 K .0099 .0196 0.25 0.50 L .016 .050 0.40 1.27 6X e 3X 1.27 [.050] 8X 1.78 [.070] y 0° 8° 0° 8° e1Kx45°

A

C y 0.10 [.004] 8X b A1 8X L 8X c 0.25 [.010] CABNOTES: 5 DIMENSION DOES NOT INCLUDE MOLD PROTRUS IONS. 1. DIMENS IONING & TOLERANCING PER ASME Y14.5M-1994. MOLD PROTRUSIONS NOT TO EXCEED 0.15 [.006]. 2. CONTROLLING DIMENSION: MILLIMETER 6 DIMENSION DOES NOT INCLUDE MOLD PROTRUS IONS. 3. DIMENS IONS ARE SHOWN IN MILLIMETERS [INCHES]. MOLD PROTRUSIONS NOT TO EXCEED 0.25 [.010]. 4. OUTLINE CONFORMS TO JEDEC OUTLINE MS-012AA. 7 DIMENSION IS THE LENGTH OF LEAD FOR SOLDERING TO A SUBSTRATE. 01-6027 8-Lead SOIC 01-0021 11 (MS-012AA) 6 www.irf.com, 01-6010 14-Lead PDIP 01-3002 03 (MS-001AC) 14-Lead SOIC (narrow body) 01-601901-3063 00 (MS-012AB) www.irf.com 7,

LIN HIN

50% 50%

LIN

ton tr toff tf 90% 90%

HO

LO 10% 10%

LO

Figure 1. Input/Output Timing Diagram 50% 50%

HIN

ton tr toff tf 90% 90% HO 10% 10% HIN 50% 50%

LIN

Figure 2. Switching Time Waveform Definitions 90% HO DTLO-HO 10% LO DT90% HO-LO 10% MDT= DTLO-HO - DTHO-LO Figure 3. Deadtime Waveform Definitions IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245 Tel: (310) 252-7105 Data and specifications subject to change without notice. 7/23/2001 8 www.irf.com]

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