Download: Order this document SEMICONDUCTOR TECHNICAL DATA by MLP1N06CL/D SMARTDISCRETES Internally Clamped, Current Limited N–Channel Logic Level Power MOSFET

Order this document SEMICONDUCTOR TECHNICAL DATA by MLP1N06CL/D SMARTDISCRETES Internally Clamped, Current Limited Motorola Preferred Device N–Channel Logic Level Power MOSFET These SMARTDISCRETES devices feature current limiting for short circuit VOLTAGE CLAMPED protection, an integral gate–to–source clamp for ESD protection and gate–to–drain CURRENT LIMITING clamp for over–voltage protection. No additional gate series resistance is required MOSFET when interfacing to the output of a MCU, but a 40 kΩ gate pulldown resistor is 62 VOLTS (CLAMPED) recommended to avoid a floating gate condition....
Author: Florian Hartmann Shared: 8/19/19
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Order this document SEMICONDUCTOR TECHNICAL DATA by MLP1N06CL/D SMARTDISCRETES Internally Clamped, Current Limited

Motorola Preferred Device

N–Channel Logic Level Power MOSFET

These SMARTDISCRETES devices feature current limiting for short circuit VOLTAGE CLAMPED protection, an integral gate–to–source clamp for ESD protection and gate–to–drain CURRENT LIMITING clamp for over–voltage protection. No additional gate series resistance is required

MOSFET

when interfacing to the output of a MCU, but a 40 kΩ gate pulldown resistor is 62 VOLTS (CLAMPED) recommended to avoid a floating gate condition. R = 0.75 OHMS The internal gate–to–source and gate–to–drain clamps allow the devices to be DS(on) applied without use of external transient suppression components. The gate–to– source clamp protects the MOSFET input from electrostatic gate voltage stresses up to 2.0 kV. The gate–to–drain clamp protects the MOSFET drain from drain D avalanche stresses that occur with inductive loads. This unique design provides voltage clamping that is essentially independent of operating temperature. The MLP1N06CL is fabricated using Motorola’s SMARTDISCRETES technolo- gy which combines the advantages of a power MOSFET output device with on–chip protective circuitry. This approach offers an economical means for providing additional functions that protect a power MOSFET in harsh automotive R1

G

and industrial environments. SMARTDISCRETES devices are specified over a wide temperature range from –50°C to 150°C. • Temperature Compensated Gate–to–Drain Clamp Limits Voltage Stress Applied to the Device and Protects the Load From Overvoltage R2 • Integrated ESD Diode Protection • Controlled Switching Minimizes RFI

S

• Low Threshold Voltage Enables Interfacing Power Loads to Microprocessors MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Symbol Value Unit Drain–to–Source Voltage VDSS Clamped Vdc Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR Clamped Vdc Gate–to–Source Voltage — Continuous VGS ±10 Vdc Drain Current — Continuous ID Self–limited Adc Drain Current — Single Pulse IDM 1.8 Total Power Dissipation PD 40 Watts Electrostatic Discharge Voltage (Human Body Model) ESD 2.0 kV

G

Operating and Storage Junction Temperature Range TJ, Tstg –50 to 150 °C D

S

THERMAL CHARACTERISTICS Thermal Resistance, Junction to Case RθJC 3.12 °C/W Thermal Resistance, Junction to Ambient RθJA 62.5 Maximum Lead Temperature for Soldering Purposes, TL 260 °C 1/8″ from case CASE 221A–06, Style 5 TO–220AB UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS Single Pulse Drain–to–Source Avalanche Energy EAS 80 mJ (Starting TJ = 25°C, ID = 2.0 A, L = 40 mH) (Figure 6) SMARTDISCRETES is a trademark of Motorola, Inc. Preferred devices are Motorola recommended choices for future use and best overall value. REV1MMoottoororolal,a In Tc.M 19O9S6 Power MOSFET Transistor Device Data 1,

ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain–to–Source Sustaining Voltage (Internally Clamped) V(BR)DSS Vdc (ID = 20 mA, VGS = 0) 59 62 65 (ID = 20 mA, VGS = 0, TJ = 150°C) 59 62 65 Zero Gate Voltage Drain Current IDSS µAdc (VDS = 45 V, VGS = 0) — 0.6 5.0 (VDS = 45 V, VGS = 0, TJ = 150°C) — 6.0 20 Gate–Body Leakage Current IGSS µAdc (VG = 5.0 V, VDS = 0) — 0.5 5.0 (VG = 5.0 V, VDS = 0, TJ = 150°C) — 1.0 20 ON CHARACTERISTICS* Gate Threshold Voltage VGS(th) Vdc (ID = 250 µA, VDS = VGS) 1.0 1.5 2.0 (ID = 250 µA, VDS = VGS, TJ = 150°C) 0.6 — 1.6 Static Drain–to–Source On–Resistance RDS(on) Ohms (ID = 1.0 A, VGS = 4.0 V) — 0.63 0.75 (ID = 1.0 A, VGS = 5.0 V) — 0.59 0.75 (ID = 1.0 A, VGS = 4.0 V, TJ = 150°C) — 1.1 1.9 (ID = 1.0 A, VGS = 5.0 V, TJ = 150°C) — 1.0 1.8 Forward Transconductance (ID = 1.0 A, VDS = 10 V) gFS 1.0 1.4 — mhos Static Source–to–Drain Diode Voltage (IS = 1.0 A, VGS = 0) VSD — 1.1 1.5 Vdc Static Drain Current Limit ID(lim) A (VGS = 5.0 V, VDS = 10 V) 2.0 2.3 2.75 (VGS = 5.0 V, VDS = 10 V, TJ = 150°C) 1.1 1.3 1.8 RESISTIVE SWITCHING CHARACTERISTICS* Turn–On Delay Time td(on) — 1.2 2.0 µs Rise Time (VDD = 25 V, ID = 1.0 A, tr — 4.0 6.0 Turn–Off Delay Time VGS = 5.0 V, RG = 50 Ohms) td(off) — 4.0 6.0 Fall Time tf — 3.0 5.0 * Indicates Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%. TJ = 25°C VDS ≥ 7.5 V4 –50°C 10V6V8V34V25°C 1 VGS = 3 V TJ = 150°C1000246802468VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. Output Characteristics Figure 2. Transfer Function

2 Motorola TMOS Power MOSFET Transistor Device Data ID , DRAIN CURRENT (AMPS) ID , DRAIN CURRENT (AMPS), THE SMARTDISCRETES CONCEPT From a standard power MOSFET process, several active 4 and passive elements can be obtained that provide on–chip VGS = 5 V protection to the basic power device. Such elements require VDS = 7.5 V only a small increase in silicon area and/or the addition of one 3 masking layer to the process. The resulting device exhibits significant improvements in ruggedness and reliability as well as system cost reduction. The SMARTDISCRETES device functions can now provide an economical alternative to smart 2 power ICs for power applications requiring low on–resistance, high voltage and high current. These devices are designed for applications that requirea1rugged power switching device with short circuit protection that can be directly interfaced to a microcontroller unit (MCU). Ideal applications include automotive fuel injector 0 driver, incandescent lamp driver or other applications where –50 0 50 100 150 T , JUNCTION TEMPERATURE (°C) a high in–rush current or a shorted load condition could occur. J OPERATION IN THE CURRENT LIMIT MODE Figure 3. ID(lim) Variation With Temperature The amount of time that an unprotected device can with- stand the current stress resulting from a shorted load before its maximum junction temperature is exceeded is dependent upon a number of factors that include the amount of heatsinking that is provided, the size or rating of the de- 4 vice, its initial junction temperature, and the supply voltage. ID = 1 A Without some form of current limiting, a shorted load can raise a device’s junction temperature beyond the maximum rated operating temperature in only a few milliseconds. Even with no heatsink, the MLP1N06CL can withstand a shorted load powered by an automotive battery (10 to 14 Volts) for almost a second if its initial operating temperature 2 150°C is under 100°C. For longer periods of operation in the cur- ° T = –50°C25CJrent–limited mode, device heatsinking can extend operation from several seconds to indefinitely depending on the 1 amount of heatsinking provided. SHORT CIRCUIT PROTECTION AND THE EFFECT OF TEMPERATURE00246810 The on–chip circuitry of the MLP1N06CL offers an inte- VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) grated means of protecting the MOSFET component from high in–rush current or a shorted load. As shown in the sche- Figure 4. RDS(on) Variation With matic diagram, the current limiting feature is provided by an Gate–To–Source Voltage NPN transistor and integral resistors R1 and R2. R2 senses the current through the MOSFET and forward biases the NPN transistor’s base as the current increases. As the NPN turns on, it begins to pull gate drive current through R1, drop- ping the gate drive voltage across it, and thus lowering the 1.25 voltage across the gate–to–source of the power MOSFET ID = 1 A and limiting the current. The current limit is temperature de- pendent as shown in Figure 3, and decreases from about 2.3 1 Amps at 25°C to about 1.3 Amps at 150°C. Since the MLP1N06CL continues to conduct current and VGS = 4 V dissipate power during a shorted load condition, it is impor- 0.75 tant to provide sufficient heatsinking to limit the device junc- tion temperature to a maximum of 150°C. VGS = 5 V The metal current sense resistor R2 adds about 0.4 ohms 0.5 to the power MOSFET’s on–resistance, but the effect of tem- perature on the combination is less than on a standard MOSFET due to the lower temperature coefficient of R2. The 0.25 on–resistance variation with temperature for gate voltages of –50 0 50 100 150 4 and 5 Volts is shown in Figure 5. TJ, JUNCTION TEMPERATURE (°C) Back–to–back polysilicon diodes between gate and source Figure 5. On–Resistance Variation With provide ESD protection to greater than 2 kV, HBM. This on– Temperature chip protection feature eliminates the need for an external Zener diode for systems with potentially heavy line transients. Motorola TMOS Power MOSFET Transistor Device Data 3 RDS(on), ON–RESISTANCE (OHMS) RDS(on), ON–RESISTANCE (OHMS) ID(lim) , DRAIN CURRENT (AMPS), 100 64 0 60 25 50 75 100 125 150 –50 0 50 100 150 TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C) Figure 6. Single Pulse Avalanche Energy Figure 7. Drain–Source Sustaining versus Junction Temperature Voltage Variation With Temperature FORWARD BIASED SAFE OPERATING AREA DUTY CYCLE OPERATION The FBSOA curves define the maximum drain–to–source When operating in the duty cycle mode, the maximum voltage and drain current that a device can safely handle drain voltage can be increased. The maximum operating when it is forward biased, or when it is on, or being turned on. temperature is related to the duty cycle (DC) by the following Because these curves include the limitations of simultaneous equation: high voltage and high current, up to the rating of the device, TC = (VDS x ID x DC x RθCA) + TA they are especially useful to designers of linear systems. The ° The maximum value of VDS applied when operating in acurves are based on a case temperature of 25 C and a maxi- duty cycle mode can be approximated by: mum junction temperature of 150°C. Limitations for repetitive pulses at various case temperatures can be determined by 150 – TVDS =

C

using the thermal response curves. Motorola Application ID(lim) x DC x RθJC Note, AN569, “Transient Thermal Resistance — General Data and Its Use” provides detailed instructions. 10 I – MAX MAXIMUM DC VOLTAGE CONSIDERATIONS 3 D(lim) 1 ms1.5 The maximum drain–to–source voltage that can be contin- 2 ID(lim) – MIN ms5 ms uously applied across the MLP1N06CL when it is in current dc limit is a function of the power that must be dissipated. This 1 power is determined by the maximum current limit at maxi- 0.6 DEVICE/POWER LIMITED mum rated operating temperature (1.8 A at 150°C) and not R 0.3 DS(on)

LIMITED

the RDS(on). The maximum voltage can be calculated by the V = 5 V0.2 GS following equation: SINGLE PULSE TC = 25°C0.1 (150 – T V = A ) 123610 20 30 60 100 supply ID(lim) (RθJC + RθCA) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) where the value of RθCA is determined by the heatsink that is Figure 8. Maximum Rated Forward Bias being used in the application. Safe Operating Area (MLP1N06CL) 4 Motorola TMOS Power MOSFET Transistor Device Data WAS, SINGLE PULSE AVALANCHE ENERGY (mJ) I D , DRAIN CURRENT (AMPS) BV(DSS), DRAIN–SOURCE SUSTAINING VOLTAGE (VOLTS), 1.0 0.7 D = 0.5 RθJC(t) = r(t) R0.5 θJCRθJC(t) = 3.12°C/W Max 0.3 0.2 D Curves Apply for Power 0.2 Pulse Train Shown 0.1 Read Time attT1J(pk) – TC = P(pk) RθJC(t) 0.1 0.05 0.07 0.02 0.05 P(pk) 0.03 0.01 t1 0.02 t2 SINGLE PULSE DUTY CYCLE, D =t1/t2 0.01 0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000 t, TIME (ms) Figure 9. Thermal Response (MLP1N06CL) VDD ton toff RL Vout td(on) tr td(off) tf 90% 90% Vin DUT PULSE GENERATOR z = 50 Ω OUTPUT, Vout 10% Rgen INVERTED 50Ω 90% 50 Ω 50% 50% INPUT, V PULSE WIDTHin 10% Figure 10. Switching Test Circuit Figure 11. Switching Waveforms ACTIVE CLAMPING SMARTDISCRETES technology can provide on–chip real- elements provide greater than 2.0 kV electrostatic voltage ization of the popular gate–to–source and gate–to–drain protection. Zener diode clamp elements. Until recently, such features The avalanche voltage of the gate–to–drain voltage clamp have been implemented only with discrete components is set less than that of the power MOSFET device. As soon which consume board space and add system cost. The as the drain–to–source voltage exceeds this avalanche volt- SMARTDISCRETES technology approach economically age, the resulting gate–to–drain Zener current builds a gate melds these features and the power chip with only a slight voltage across the gate–to–source impedance, turning on increase in chip area. the power device which then conducts the current. Since vir- In practice, back–to–back diode elements are formed in a tually all of the current is carried by the power device, the polysilicon region monolithicly integrated with, but electrically gate–to–drain voltage clamp element may be small in size. isolated from, the main device structure. Each back–to–back This technique of establishing a temperature compensated diode element provides a temperature compensated voltage element of about 7.2 volts. As the polysilicon region is drain–to–source sustaining voltage (Figure 7) effectively re- formed on top of silicon dioxide, the diode elements are free moves the possibility of drain–to–source avalanche in the from direct interaction with the conduction regions of the power device. power device, thus eliminating parasitic electrical effects The gate–to–drain voltage clamp technique is particularly while maintaining excellent thermal coupling. useful for snubbing loads where the inductive energy would To achieve high gate–to–drain clamp voltages, several otherwise avalanche the power device. An improvement in voltage elements are strung together; the MLP1N06CL uses ruggedness of at least four times has been observed when 8 such elements. Customarily, two voltage elements are inductive energy is dissipated in the gate–to–drain clamped used to provide a 14.4 volt gate–to–source voltage clamp. conduction mode rather than in the more stressful gate–to– For the MLP1N06CL, the integrated gate–to–source voltage source avalanche mode. Motorola TMOS Power MOSFET Transistor Device Data 5 r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE (NORMALIZED),

TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS The MLP1N06CL has been designed to allow direct inter- VBAT

face to the output of a microcontrol unit to control an isolated load. No additional series gate resistance is required, but a VDD 40 kΩ gate pulldown resistor is recommended to avoid a floating gate condition in the event of an MCU failure. The in- ternal clamps allow the device to be used without any exter- D nal transistent suppressing components.

G

MCU MLP1N06CL

S PACKAGE DIMENSIONS

NOTES: –T– SEATING STYLE 5: 1. DIMENSIONING AND TOLERANCING PER ANSIPLANE PIN 1. GATE Y14.5M, 1982.

BFC2. DRAIN 2. CONTROLLING DIMENSION: INCH. T 3. SOURCE 3. DIMENSION Z DEFINES A ZONE WHERE ALLS 4. DRAIN BODY AND LEAD IRREGULARITIES ARE

ALLOWED. INCHES MILLIMETERS

Q A DIM MIN MAX MIN MAXA 0.570 0.620 14.48 15.75

123UB0.380 0.405 9.66 10.28C 0.160 0.190 4.07 4.82

H D 0.025 0.035 0.64 0.88

F 0.142 0.147 3.61 3.73

K G 0.095 0.105 2.42 2.66 Z H 0.110 0.155 2.80 3.93

J 0.018 0.025 0.46 0.64 K 0.500 0.562 12.70 14.27

LRL0.045 0.060 1.15 1.52N 0.190 0.210 4.83 5.33 VJQ0.100 0.120 2.54 3.04

R 0.080 0.110 2.04 2.79

G S 0.045 0.055 1.15 1.39

T 0.235 0.255 5.97 6.47

D U 0.000 0.050 0.00 1.27 N V 0.045 ––– 1.15 –––

Z ––– 0.080 ––– 2.04

CASE 221A–06 ISSUE Y

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters can and do vary in different applications. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. How to reach us: USA / EUROPE: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.; Tatsumi–SPD–JLDC, Toshikatsu Otsuki, P.O. Box 20912; Phoenix, Arizona 85036. 1–800–441–2447 6F Seibu–Butsuryu–Center, 3–14–2 Tatsumi Koto–Ku, Tokyo 135, Japan. 03–3521–8315 MFAX: email is hidden – TOUCHTONE (602) 244–6609 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, INTERNET: http://Design–NET.com 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 6 ◊ Motorola TMOS Power MOSFET TransisMtoLr PD1eNv0ic6eC LD/Data]
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Order this document SEMICONDUCTOR TECHNICAL DATA by MHPM6B5A120D/D Integrated Power Stage Motorola Preferred Devices for 460 VAC Motor Drives These modules integrate a 3–phase inverter in a single convenient package. They are designed for 1.0, 2.0 and 3.0 hp motor drive applications. The inverter 5.
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Order this document SEMICONDUCTOR TECHNICAL DATA by MHPM6B20E60D3/D Integrated Power Stage Motorola Preferred Device for 230 VAC Motor Drives This module integrates a 3–phase inverter and 3–phase rectifier in a single convenient package. It is designed for 2.0 hp motor drive 20 AMP, 600 VOLT applica
Order this document SEMICONDUCTOR TECHNICAL DATA by MHPM6B10N120/D Integrated Power Stage for 460 VAC Motor Drives
Order this document SEMICONDUCTOR TECHNICAL DATA by MHPM6B10N120/D Integrated Power Stage for 460 VAC Motor Drives These modules integrate a 3–phase inverter in a single convenient package. They are designed for 2.0, 3.0, and 5.0 hp motor drive applications. The inverter incorporates advanced Motoro
Order this document SEMICONDUCTOR TECHNICAL DATA by MHPM6B15E60D3/D Integrated Power Stage for 230 VAC Motor Drives
Order this document SEMICONDUCTOR TECHNICAL DATA by MHPM6B15E60D3/D Integrated Power Stage for 230 VAC Motor Drives Motorola Preferred Devices These modules integrate a 3–phase inverter and 3–phase rectifier in a single convenient package. They are designed for 0.5, 1.0, and 1.5 hp motor drive appli
Order this document SEMICONDUCTOR TECHNICAL DATA by MHPM6B10A60D/D Motorola Preferred Devices Integrated Power Stage for 230 VAC Motor Drives
Order this document SEMICONDUCTOR TECHNICAL DATA by MHPM6B10A60D/D Motorola Preferred Devices Integrated Power Stage for 230 VAC Motor Drives 10, 20 AMP, 600 V These modules integrate a 3–phase inverter in a single convenient package. HYBRID POWER MODULES They are designed for 1.0 and 2.0 hp motor d
Order this document SEMICONDUCTOR TECHNICAL DATA by MGY40N60/D  N–Channel Enhancement–Mode Silicon Gate
Order this document SEMICONDUCTOR TECHNICAL DATA by MGY40N60/D Motorola Preferred Device N–Channel Enhancement–Mode Silicon Gate This Insulated Gate Bipolar Transistor (IGBT) uses an advanced IGBT IN TO–264 termination scheme to provide an enhanced and reliable high 40 A @ 90°C voltage–blocking cap
Order this document SEMICONDUCTOR TECHNICAL DATA by MGY40N60D/D  N–Channel Enhancement–Mode Silicon Gate IGBT & DIODE IN TO–264
Order this document SEMICONDUCTOR TECHNICAL DATA by MGY40N60D/D Motorola Preferred Device N–Channel Enhancement–Mode Silicon Gate IGBT & DIODE IN TO–264 40 A @ 90°C This Insulated Gate Bipolar Transistor (IGBT) is co–packaged 66 A @ 25°C with a soft recovery ultra–fast rectifier and uses an advance
Order this document SEMICONDUCTOR TECHNICAL DATA by MGY30N60D/D  N–Channel Enhancement–Mode Silicon Gate IGBT & DIODE IN TO–264
Order this document SEMICONDUCTOR TECHNICAL DATA by MGY30N60D/D Motorola Preferred Device N–Channel Enhancement–Mode Silicon Gate IGBT & DIODE IN TO–264 30 A @ 90°C This Insulated Gate Bipolar Transistor (IGBT) is co–packaged 50 A @ 25°C with a soft recovery ultra–fast rectifier and uses an advance