Download: Order this document SEMICONDUCTOR TECHNICAL DATA by MMDF6N03HD/D Medium Power Surface Mount Products

Order this document SEMICONDUCTOR TECHNICAL DATA by MMDF6N03HD/D Medium Power Surface Mount Products Motorola Preferred Device DUAL TMOS Dual HDTMOS devices are an advanced series of power POWER MOSFET MOSFETs which utilize Motorola’s High Cell Density TMOS 30 VOLTS process. These miniature surface mount MOSFETs feature low RDS(on) = 35 m RDS(on) and true logic level performance. Dual HDTMOS devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applica- tions are dc–dc converters, and power management in portable and batte...
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Order this document SEMICONDUCTOR TECHNICAL DATA by MMDF6N03HD/D Medium Power Surface Mount Products

Motorola Preferred Device DUAL TMOS Dual HDTMOS devices are an advanced series of power POWER MOSFET MOSFETs which utilize Motorola’s High Cell Density TMOS 30 VOLTS process. These miniature surface mount MOSFETs feature low RDS(on) = 35 m RDS(on) and true logic level performance. Dual HDTMOS devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applica- tions are dc–dc converters, and power management in portable and battery powered products such as computers, printers, cellular D and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. CASE 751–05, Style 11 • Low RDS(on) Provides Higher Efficiency and Extends Battery Life G SO–8 • Logic Level Gate Drive — Can Be Driven by Logic ICs • Miniature SO–8 Surface Mount Package — Saves Board Space S • Diode Is Characterized for Use In Bridge Circuits D • Diode Exhibits High Speed, With Soft Recovery Source–118Drain–1 • IDSS Specified at Elevated Temperature Gate–127Drain–1 • Mounting Information for SO–8 Package Provided Source–236Drain–2 G Gate–245Drain–2 Top View

S

MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) Rating Symbol Value Unit Drain–to–Source Voltage VDSS 30 Vdc Gate–to–Source Voltage — Continuous VGS ± 20 Vdc Drain Current — Continuous @ TA = 25°C ID 6.0 Adc Drain Current — Single Pulse (tp ≤ 10 µs) IDM 30 Apk Source Current — Continuous @ TA = 25°C IS 1.7 Adc Total Power Dissipation @ TA = 25°C (1) PD 2.0 Watts Operating and Storage Temperature Range TJ, Tstg – 55 to 150 °C Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C EAS 325 mJ (VDD = 30 Vdc, VGS = 5.0 Vdc, VDS = 20 Vdc, IL = 9.0 Apk, L = 10 mH, RG = 25 ) Thermal Resistance — Junction–to–Ambient RθJA 62.5 °C/W Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 sec. TL 260 °C DEVICE MARKING D6N03 (1) Mounted on G10/FR4 glass epoxy board using minimum recommended footprint. ORDERING INFORMATION Device Reel Size Tape Width Quantity MMDF6N03HDR2 13″ 12 mm embossed tape 2500 Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves — representing boundaries on device characteristics — are given to facilitate “worst case” design. Designer’s and HDTMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company. Preferred devices are Motorola recommended choices for future use and best overall value. REV2MMoottoororolal,a In Tc.M 19O9S7 Power MOSFET Transistor Device Data 1, ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted) Characteristic Symbol Min Typ Max Unit OFF CHARACTERISTICS Drain–to–Source Breakdown Voltage V(BR)DSS Vdc (VGS = 0 Vdc, ID = 0.25 mAdc) 30 — — Zero Gate Voltage Drain Current IDSS µAdc (VDS = 24 Vdc, VGS = 0 Vdc) — — 1.0 (VDS = 24 Vdc, VGS = 0 Vdc, TJ = 125°C) — — 20 Gate–Body Leakage Current (VGS = ±20 Vdc, VDS = 0 Vdc) IGSS — — 100 nAdc ON CHARACTERISTICS(1) Gate Threshold Voltage VGS(th) Vdc (VDS = VGS, ID = 0.25 mAdc) 1.0 — — Threshold Temperature Coefficient (Negative) Static Drain–to–Source On–Resistance RDS(on) mΩ (VGS = 10 Vdc, ID = 5.0 Adc) — 28 35 (VGS = 4.5 Vdc, ID = 3.9 Adc) — 42 50 Forward Transconductance (VDS = 15 Vdc, ID = 5.0 Adc) gFS — 9.0 — Mhos DYNAMIC CHARACTERISTICS Input Capacitance C — 430 600 pF (VDS = 24 Vdc, iss Output Capacitance VGS = 0 Vdc, Coss — 217 300 Transfer Capacitance f = 1.0 MHz) Crss — 67.5 135 SWITCHING CHARACTERISTICS(2) Turn–On Delay Time td(on) — 8.2 16.4 ns (VDD = 15 Vdc, Rise Time VGS = 10 Vdc, tr — 8.48 16.9 Turn–Off Delay Time ID = 1.0 Adc, td(off) — 89.6 179 RG = 6.0 Ω) Fall Time tf — 61.1 122 Turn–On Delay Time td(on) — 11.8 23 ns (VDD = 15 Vdc, Rise Time VGS = 4.5 Vdc, tr — 51.3 102 Turn–Off Delay Time ID = 1.0 Adc, td(off) — 47.2 94.5 RG = 6.0 Ω) Fall Time tf — 62 104 Gate Charge QT — 15.7 31.4 nC (See Figure 8) (VDS = 15 Vdc, Q1 — 2.0 — ID = 5.0 Adc, VGS = 10 Vdc) Q2 — 4.6 — Q3 — 3.86 — SOURCE–DRAIN DIODE CHARACTERISTICS Forward On–Voltage (IS = 1.7 Adc, VGS = 0 Vdc) VSD Vdc (IS = 1.7 Adc, VGS = 0 Vdc, — 0.77 1.2 TJ = 125°C) — 0.65 — Reverse Recovery Time trr — 54.5 — ns (IS = 5.0 Adc, VGS = 0 Vdc, ta — 14.8 — dIS/dt = 100 A/µs) tb — 39.7 — Reverse Recovery Stored Charge QRR — 0.048 — µC (1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (2) Switching characteristics are independent of operating junction temperature. 2 Motorola TMOS Power MOSFET Transistor Device Data,

TYPICAL ELECTRICAL CHARACTERISTICS

12 12 10 V 3.9 V TJ = 25°C 3.7 V 6.0 V 10 10 VDS ≥ 10 V 4.5 V 4.3 V 3.5 V8.0 8.0 4.1 V 6.0 3.3 V 6.0 100°C 25°C 4.0 3.1 V 4.0 2.9 V 2.0 2.0 TJ = –55°C VGS = 2.5 V 2.7V0000.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

0.30 0.050 TJ = 25° T = 25°CCJ0.25 ID = 6 A 0.045 VGS = 4.5 V 0.20 0.040 0.15 0.035 0.10 0.030 10 V 0.05 0 0.025 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)

Figure 3. On–Resistance versus Figure 4. On–Resistance versus Drain Current Gate–To–Source Voltage and Gate Voltage

1.8 1000 VGS = 0 V 1.6 VGS = 10 V ID = 3 A TJ = 125°C1.4 100 1.2 1.0 100°C 0.8 0.6 0.4 1.0 25°C 0.2 0 0.1 –50 –25 0 25 50 75 100 125 150 0 5.0 10 15 20 25 30 TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

Figure 5. On–Resistance Variation with Figure 6. Drain–To–Source Leakage Temperature Current versus Voltage Motorola TMOS Power MOSFET Transistor Device Data 3

RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED) RDS(on), DRAIN–TO–SOURCE RESISTANCE (OHMS) ID, DRAIN CURRENT (AMPS) RDS(on), DRAIN–TO–SOURCE RESISTANCE (OHMS)IDSS, LEAKAGE (nA) ID, DRAIN CURRENT (AMPS), POWER MOSFET SWITCHING Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at by recognizing that the power MOSFET is charge controlled. a voltage corresponding to the off–state condition when cal- The lengths of various switching intervals (∆t) are deter- culating td(on) and is read at a voltage corresponding to the mined by how fast the FET input capacitance can be charged on–state when calculating td(off). by current from the generator. The published capacitance data is difficult to use for calculat- At high switching speeds, parasitic circuit elements com- ing rise and fall because drain–gate capacitance varies plicate the analysis. The inductance of the MOSFET source greatly with applied voltage. Accordingly, gate charge data is lead, inside the package and in the circuit wiring which is used. In most cases, a satisfactory estimate of average input common to both the drain and gate current paths, produces a current (IG(AV)) can be made from a rudimentary analysis of voltage at the source which reduces the gate drive current. the drive circuit so that The voltage is determined by Ldi/dt, but since di/dt is a func- t = Q/I tion of drain current, the mathematical solution is complex.G(AV) The MOSFET output capacitance also complicates the During the rise and fall time interval when switching a resis- mathematics. And finally, MOSFETs have finite internal gate tive load, VGS remains virtually constant at a level known as resistance which effectively adds to the resistance of the the plateau voltage, VSGP. Therefore, rise and fall times may driving source, but the internal resistance is difficult to mea- be approximated by the following: sure and, consequently, is not specified. tr = Q2 x RG/(VGG – VGSP) The resistive switching time variation versus gate resis- tf = Q2 x RG/VGSP tance (Figure 9) shows how typical switching performance is where affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a VGG = the gate drive voltage, which varies from zero to VGG value of unity regardless of the switching speed. The circuit RG = the gate drive resistance used to obtain the data is constructed to minimize common and Q2 and VGSP are read from the gate charge curve. inductance in the drain and gate circuit loops and is believed readily achievable with board mounted components. Most During the turn–on and turn–off delay times, gate current is power electronic loads are inductive; the data in the figure is not constant. The simplest calculation uses appropriate val- ues from the capacitance curves in a standard equation for taken with a resistive load, which approximates an optimally voltage change in an RC network. The equations are: snubbed inductive load. Power MOSFETs may be safely op- erated into an inductive load; however, snubbing reduces td(on) = RG Ciss In [VGG/(VGG – VGSP)] switching losses. td(off) = RG Ciss In (VGG/VGSP) TJ = 25°C Ciss Coss Crss –10 –5.0 0 5.0 10 15 20 25 30 VGS VDS VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7. Capacitance Variation 4 Motorola TMOS Power MOSFET Transistor Device Data C, CAPACITANCE (pF), 12 30 1000 11 QT VDD = 15 V 10 ID = 6 A

V

9.0 GS = 10 V VGS TJ = 25°C 8.0 20 100 td(off) 7.0 Q1 Q2 tf 6.0 5.0 tr 4.0 ID = 5 A 10 10 3.0 TJ = 25°C td(on) 2.0 1.0 Q3 VDS001.0 0 2.0 4.0 6.0 8.0 10 12 14 16 1.0 10 100 Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS) Figure 8. Gate–To–Source and Drain–To–Source Figure 9. Resistive Switching Time Voltage versus Total Charge Variation versus Gate Resistance

DRAIN–TO–SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode di/dts. The diode’s negative di/dt during ta is directly con- are very important in systems using it as a freewheeling or trolled by the device clearing the stored charge. However, commutating diode. Of particular interest are the reverse re- the positive di/dt during tb is an uncontrollable diode charac- covery characteristics which play a major role in determining teristic and is usually the culprit that induces current ringing. switching losses, radiated noise, EMI and RFI. Therefore, when comparing diodes, the ratio of tb/ta serves System switching losses are largely due to the nature of as a good indicator of recovery abruptness and thus gives a the body diode itself. The body diode is a minority carrier de- comparative estimate of probable noise generated. A ratio of vice, therefore it has a finite reverse recovery time, trr, due to 1 is considered ideal and values less than 0.5 are considered the storage of minority carrier charge, QRR, as shown in the snappy. typical reverse recovery wave form of Figure 15. It is this Compared to Motorola standard cell density low voltage stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, MOSFETs, high cell density MOSFET diodes are faster repeatedly forcing the diode through reverse recovery further (shorter trr), have less stored charge and a softer reverse re- increases switching losses. Therefore, one would like a covery characteristic. The softness advantage of the high diode with short trr and low QRR specifications to minimize cell density diode means they can be forced through reverse these losses. recovery at a higher di/dt than a standard cell MOSFET The abruptness of diode reverse recovery effects the diode without increasing the current ringing or the noise gen- amount of radiated noise, voltage spikes, and current ring- erated. In addition, power dissipation incurred from switching ing. The mechanisms at work are finite irremovable circuit the diode will be less due to the shorter recovery time and parasitic inductances and capacitances acted upon by high lower switching losses. 5.0

V

4.5 GS = 0 V TJ = 25°C 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) Figure 10. Diode Forward Voltage versus Current Motorola TMOS Power MOSFET Transistor Device Data 5 VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) IS, SOURCE CURRENT (AMPS) t, TIME (ns) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS), di/dt = 300 A/µs Standard Cell Density trr High Cell Density trr tb ta t, TIME Figure 11. Reverse Recovery Time (trr)

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define averaged over a complete switching cycle must not exceed the maximum simultaneous drain–to–source voltage and (TJ(MAX) – TC)/(RθJC). drain current that a transistor can handle safely when it is for- A power MOSFET designated E–FET can be safely used ward biased. Curves are based upon maximum peak junc- in switching circuits with unclamped inductive loads. For reli- tion temperature and a case temperature (TC) of 25°C. Peak able operation, the stored energy from circuit inductance dis- repetitive pulsed power limits are determined by using the sipated in the transistor while in avalanche must be less than thermal response data in conjunction with the procedures the rated limit and must be adjusted for operating conditions discussed in AN569, “Transient Thermal Resistance – Gen- differing from those specified. Although industry practice is to eral Data and Its Use.” rate in terms of energy, avalanche energy capability is not a Switching between the off–state and the on–state may tra- constant. The energy rating decreases non–linearly with an verse any load line provided neither rated peak current (IDM) increase of peak current in avalanche and peak junction tem- nor rated voltage (VDSS) is exceeded, and that the transition perature. time (tr, tf) does not exceed 10 µs. In addition the total power 100 350 VGS = 12 V SINGLE PULSE 300 ID = 6 A TA = 25°C 1.0 ms 10 ms 1.0 dc 0.1 RDS(on) LIMIT THERMAL LIMIT 50 PACKAGE LIMIT 0.01 0 0.1 1.0 10 100 25 45 65 85 105 125 145 VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C) Figure 12. Maximum Rated Forward Biased Figure 13. Maximum Avalanche Energy versus Safe Operating Area Starting Junction Temperature 6 Motorola TMOS Power MOSFET Transistor Device Data ID, DRAIN CURRENT (AMPS) I S, SOURCE CURRENT EAS , SINGLE PULSE DRAIN–TO–SOURCE AVALANCHE ENERGY (mJ),

TYPICAL ELECTRICAL CHARACTERISTICS

1.0 D = 0.5 0.2 0.1 0.1 0.05 0.02 0.0106 0.0431 0.1643 0.3507 0.4302 0.01 CHIP 0.01 JUNCTION 0.0253 F 0.1406 F 0.5064 F 2.9468 F 177.14 F

AMBIENT

SINGLE PULSE 0.001 1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03 t, TIME (s)

Figure 14. Thermal Response

di/dt

IS

trr ta tb

TIME

tp 0.25 IS

IS Figure 15. Diode Reverse Recovery Waveform Motorola TMOS Power MOSFET Transistor Device Data 7

Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE,

INFORMATION FOR USING THE SO–8 SURFACE MOUNT PACKAGE

MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS Surface mount board layout is a critical portion of the total between the board and the package. With the correct pad design. The footprint for the semiconductor packages must be geometry, the packages will self–align when subjected to a the correct size to ensure proper solder connection interface solder reflow process. 0.060 1.52 0.275 0.155 7.0 4.0 0.024 0.050 0.6 1.270 inches mm SO–8 POWER DISSIPATION The power dissipation of the SO–8 is a function of the input the equation for an ambient temperature TA of 25°C, one can pad size. This can vary from the minimum pad size for calculate the power dissipation of the device which in this case soldering to the pad size given for maximum power is 2.0 Watts. dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RθJA, the thermal resistance from the 150°C – 25°C PD = = 2.0 Watts device junction to ambient; and the operating temperature, TA. 62.5°C/W Using the values provided on the data sheet for the SO–8 package, PD can be calculated as follows: The 62.5°C/W for the SO–8 package assumes the recommended footprint on a glass epoxy printed circuit board

T

P = J(max) – TA D to achieve a power dissipation of 2.0 Watts using the footprint RθJA shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal Clad. The values for the equation are found in the maximum Using board material such as Thermal Clad, the power ratings table on the data sheet. Substituting these values into dissipation can be doubled using the same footprint. SOLDERING PRECAUTIONS The melting temperature of solder is higher than the rated • The soldering temperature and time shall not exceed temperature of the device. When the entire device is heated 260°C for more than 10 seconds. to a high temperature, failure to complete soldering within a • When shifting from preheating to soldering, the maximum short time could result in device failure. Therefore, the temperature gradient shall be 5°C or less. following items should always be observed in order to • After soldering has been completed, the device should be minimize the thermal stress to which the devices are allowed to cool naturally for at least three minutes. subjected. Gradual cooling should be used as the use of forced • Always preheat the device. cooling will increase the temperature gradient and result • The delta temperature between the preheat and soldering in latent failure due to mechanical stress. should be 100°C or less.* • Mechanical stress or shock should not be applied during • When preheating and soldering, the temperature of the cooling. leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When * Soldering a device without preheating can cause excessive using infrared heating with the reflow soldering method, thermal shock and stress which can result in damage to the the difference shall be a maximum of 10°C. device. 8 Motorola TMOS Power MOSFET Transistor Device Data,

TYPICAL SOLDER HEATING PROFILE

For any given circuit board, there will be a group of control line on the graph shows the actual temperature that might be settings that will give the desired heat pattern. The operator experienced on the surface of a test board at or near a central must set temperatures for several heating zones and a figure solder joint. The two profiles are based on a high density and for belt speed. Taken together, these control settings make up a low density board. The Vitronics SMD310 convection/in- a heating “profile” for that particular circuit board. On frared reflow soldering system was used to generate this machines controlled by a computer, the computer remembers profile. The type of solder used was 62/36/2 Tin Lead Silver these profiles from one operating session to the next. Figure with a melting point between 177–189°C. When this type of 16 shows a typical heating profile for use when soldering a furnace is used for solder reflow work, the circuit boards and surface mount device to a printed circuit board. This profile will solder joints tend to heat first. The components on the board vary among soldering systems, but it is a good starting point. are then heated by conduction. The circuit board, because it Factors that can affect the profile include the type of soldering has a large surface area, absorbs the thermal energy more system in use, density and types of components on the board, efficiently, then distributes this energy to the components. type of solder used, and the type of board or substrate material Because of this effect, the main body of a component may be being used. This profile shows temperature versus time. The up to 30 degrees cooler than the adjacent solder joints. STEP 1 STEP 2 STEP 3 STEP 4 STEP 5 STEP 6 STEP 7 PREHEAT VENT HEATING HEATING HEATING VENT COOLING ZONE 1 “SOAK” ZONES 2 & 5 ZONES 3 & 6 ZONES 4 & 7 “RAMP” “RAMP” “SOAK” “SPIKE” 205° TO 219°C 200°C PEAK AT DESIRED CURVE FOR HIGH 170°C SOLDER JOINT MASS ASSEMBLIES 160°C 150°C 150°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS 100°C 140°C (DEPENDING ON 100°C MASS OF ASSEMBLY) DESIRED CURVE FOR LOW MASS ASSEMBLIES 50°C TIME (3 TO 7 MINUTES TOTAL) TMAX Figure 16. Typical Solder Heating Profile Motorola TMOS Power MOSFET Transistor Device Data 9,

PACKAGE DIMENSIONS A D NOTES:C 1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994. 2. DIMENSIONS ARE IN MILLIMETERS. 8 5 3. DIMENSION D AND E DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

E H 0.25MBM5. DIMENSION B DOES NOT INCLUDE MOLD

1 PROTRUSION. ALLOWABLE DAMBAR 4 PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. h X 45

B MILLIMETERSe DIM MIN MAX

A 1.35 1.75

A A1 0.10 0.25C B 0.35 0.49

SEATING C 0.18 0.25 PLANE D 4.80 5.00

L E 3.80 4.00

0.10 e 1.27 BSC H 5.80 6.20

A1Bh0.25 0.50

L 0.40 1.25 0.25MCBSAS07STYLE 11: PIN 1. SOURCE 1 2. GATE 1 3. SOURCE 2 4. GATE 2 5. DRAIN 2 6. DRAIN 2

CASE 751–05 7. DRAIN 1 SO–8 8. DRAIN 1 ISSUE S

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer. Mfax is a trademark of Motorola, Inc. How to reach us: USA/EUROPE/Locations Not Listed: Motorola Literature Distribution; JAPAN: Nippon Motorola Ltd.: SPD, Strategic Planning Office, 4–32–1, P.O. Box 5405, Denver, Colorado 80217. 303–675–2140 or 1–800–441–2447 Nishi–Gotanda, Shinagawa–ku, Tokyo 141, Japan. 81–3–5487–8488 Mfax: email is hidden – TOUCHTONE 602–244–6609 ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, – US & Canada ONLY 1–800–774–1848 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852–26629298 INTERNET: http://motorola.com/sps 10 ◊ Motorola TMOS Power MOSFET TransistoMrM DDeFv6icNe0 3DHaDta/D]
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GENERAL DESCRIPTION QUICK REFERENCE DATA Low leakage, platinum barrier, SYMBOL PARAMETER MAX. MAX. MAX. UNIT schottky rectifier diodes in a full pack, plastic envelope featuring low PBYR16- 35F 40F 45F forward voltage drop and absence of VRRM Repetitive peak reverse 35 40 45 V stored charge. These d
GENERAL DESCRIPTION QUICK REFERENCE DATA
GENERAL DESCRIPTION QUICK REFERENCE DATA Low leakage, platinum barrier SYMBOL PARAMETER MAX. MAX. MAX. UNIT schottky rectifier diodes in a plastic envelope featuring low forward PBYR16- 35 40 45 voltage drop and absence of stored VRRM Repetitive peak reverse 35 40 45 V charge. These devices can with
GENERAL DESCRIPTION QUICK REFERENCE DATA
GENERAL DESCRIPTION QUICK REFERENCE DATA Dual, low leakage, platinum barrier, SYMBOL PARAMETER MAX. MAX. MAX. UNIT schottky barrier rectifier diodes in a full pack, plastic envelope featuring PBYR15F- 35CTF 40CTF 45CTF low forward voltage drop and VRRM Repetitive peak reverse 35 40 45 V absence of s
GENERAL DESCRIPTION QUICK REFERENCE DATA
GENERAL DESCRIPTION QUICK REFERENCE DATA Dual, low leakage, platinum barrier, SYMBOL PARAMETER MAX. MAX. MAX. UNIT schottky rectifier diodes in a plastic envelope featuring low forward PBYR15- 35CT 40CT 45CT voltage drop and absence of stored VRRM Repetitive peak reverse 35 40 45 V charge. These dev
GENERAL DESCRIPTION QUICK REFERENCE DATA
GENERAL DESCRIPTION QUICK REFERENCE DATA Low leakage, platinum barrier, SYMBOL PARAMETER MAX. MAX. MAX. UNIT schottky rectifier diodes in a full pack, plastic envelope featuring low PBYR10- 35F 40F 45F forward voltage drop and absence of VRRM Repetitive peak reverse 35 40 45 V stored charge. These d
GENERAL DESCRIPTION QUICK REFERENCE DATA
GENERAL DESCRIPTION QUICK REFERENCE DATA Low leakage, platinum barrier SYMBOL PARAMETER MAX. MAX. MAX. UNIT schottky rectifier diodes in a plastic envelope featuring low forward PBYR10- 35 40 45 voltage drop and absence of stored VRRM Repetitive peak reverse 35 40 45 V charge. These devices can with
GENERAL DESCRIPTION QUICK REFERENCE DATA
GENERAL DESCRIPTION QUICK REFERENCE DATA Low leakage, platinum barrier SYMBOL PARAMETER MAX. MAX. MAX. UNIT schottky rectifier diodes in a plastic envelope featuring low forward PBYR10- 60 80 100 voltage drop and absence of stored VRRM Repetitive peak reverse 60 80 100 V charge. These devices can wi
DISCRETE SEMICONDUCTORS DATA SHEET Package outlines RF Power Transistors for UHF 1996 Feb 20 File under Discrete Semiconductors, SC08b
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DISCRETE SEMICONDUCTORS DATA SHEET Package outlines RF Power Modules and Transistors for Mobile Phones Product specification 1996 May 29 File under Discrete Semiconductors, SC09 4.0 handbook, full pagewidth 5.0 3.8 A 4.8 S 0.1 S 6.2 5.8 0.7 0.3850.7 1.45 0.6 0.25 1.75 1.25 0.19 1.35140.25 1.0 o pin
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DISCRETE SEMICONDUCTORS DATA SHEET OM2050 Wideband amplifier module Product specification 1995 Nov 13 File under Discrete Semiconductors, SC16
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DISCRETE SEMICONDUCTORS DATA SHEET OM2045 Wideband amplifier module Product specification 1995 Nov 10 File under Discrete Semiconductors, SC16
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Order this document SEMICONDUCTOR TECHNICAL DATA by MTD3302/D " Power Surface Mount Products SINGLE TMOS ! ! POWER MOSFET 30 VOLTS WaveFET devices are an advanced series of power MOSFETs which utilize Motorola’s RDS(on) = 10 m latest MOSFET technology process to achieve the lowest possible on–re