Download: VALUAT AVAILAB General Description Features

19-1635; Rev 0; 1/00

VALUAT

ION KITEE

AVAILAB

L Complete Dual-Band

General Description Features

The MAX2360 dual-band, triple-mode complete transmit- Dual-Band, Triple-Mode Operation ter for cellular phones represents the most integrated and architecturally advanced solution to date for this applica- +7dBm Output Power with -54dBc ACPR tion. The device takes a differential I/Q baseband input 100dB Power Control Range and mixes it up to IF through a quadrature modulator and IF variable-gain amplifier (VGA). The signal is then routed Supply Current Drops as Output Power Is Reduced to an external bandpass filter and upconverted to RF Dual Synthesizer for IF and RF LO through an SSB mixer and RF VGA. The signal is further amplified with an on-board PA driver. Dual IF synthesiz- Dual On-Chip IF VCO ers, dual RF synthesizers, a local oscillator (LO) buffer, QSPI/SPI/MICROWIRE-Compatible 3-Wire Bus and a 3-wire programmable bus complete the basic func- tional blocks of this IC. The MAX2362 supports single- Digitally Controlled Operational Modes band, single-mode (PCS) operation. The MAX2364 +2.7V to +5.5V Operation supports single-band cellular dual-mode operation. The MAX2360 enables architectural flexibility because Single Sideband Upconverter Eliminates SAW its two IF voltage-controlled oscillators (VCOs), two IF Filters ports, two RF LO input ports, and three PA driver output ports allow the use of a single receive IF frequency and split-band PCS filters for optimum out-of-band noise Ordering Information performance. The PA drivers allow up to three RF SAW PART TEMP. RANGE PIN-PACKAGE filters to be eliminated. Select a mode of operation by loading data on the SPI™/QSPI™/MICROWIRE™-com- MAX2360ECM -40°C to +85°C 48 TQFP-EP* patible 3-wire serial bus. Charge-pump current, side- MAX2362ECM -40°C to +85°C 48 TQFP-EP* band rejection, IF/RF gain balancing, standby, and MAX2364ECM -40°C to +85°C 48 TQFP-EP* shutdown are also controlled with the serial interface. *Exposed paddle The MAX2360/MAX2362/MAX2364 come in a 48-pin TQFP-EP package and are specified for the extended (-40°C to +85°C) temperature range. Functional Diagram

Applications

Triple-Mode, Dual-Mode, or Single-Mode Mobile Phones Satellite Phones RFL 1 RFPLL 36 REF Wireless Data Links (WAN/LAN) RFH0 2 IFPLL 35 N.C. Wireless Local Area Networks (LANs) LOCK 3 34 N.C. V 4 MAX2360 33 TANKH+ High-Speed Data Modems CC IDLE5Σ32 TANKH- High-Speed Digital Cordless Phones V 90CC6031 TANKL+ Wireless Local Loop (WLL) TXGATE 7 30 TANKL-45 -45 IFINL+ 8 /2 29 IFLO IFINL- 9 28 VCC Pin Configurations appear at end of data sheet. IFINH+ 10 0 /2 27 SHDNΣ 90 IFINH- 11 26 I- Selector Guide appears at end of data sheet. RBIAS 12 25 I+ SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp. _ Maxim Integrated Products 1

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CLK 13 48 GND DI 14 47 RFH1 CS 15 46 GND IFOUTH- 16 45 GND IFOUTH+ 17 44 LOL IFOUTL+ 18 43 LOH IFOUTL- 19 42 RFPLL VGC 20 41 VCC VCC 21 40 RFCP VCC 22 39 VCC Q+ 23 38 IFCP Q- 24 37 VCC,

ABSOLUTE MAXIMUM RATINGS

VCC to GND...-0.3V to +3.6V Continuous Power Dissipation (TA = +70°C) RFL, RFH0, RFH1...+5.5V 48-Pin TQFP-EP (derate 27mW/°C above +70°C)...2.16W DI, CLK, CS, VGC, SHDN, TXGATE, Operating Temperature Range ...-40°C to +85°C IDLE, LOCK...-0.3V to (VCC + 0.3V) Junction Temperature ...+150°C AC Input Pins (IFINL, IFINH, Q, I, TANKL, TANKH, Storage Temperature Range ...-65°C to +160°C REF, RFPLL, LOL, LOH)...1.0V peak Lead Temperature (soldering, 10s) ...+300°C Digital Input Current (SHDN, TXGATE, IDLE, CLK, DI, CS) ...±10mA Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS

(MAX2360/2/4 test fixture: VCC = VBATT = 2.75V, SHDN = IDLE = TXGATE = 2.0V, VGC = 2.5V, RBIAS = 16kΩ, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C, and operating modes are defined in Table 6.) PARAMETER CONDITIONS MIN TYP MAX UNITS Operating Supply Voltage 2.7 3.0 V VGC = 0.5V 92 118 PCS mode VGC = 2.0V 97 123 VGC = 2.5V 132 161 VGC = 0.5V 91 110 Cellular VGC = 2.0V 95 122 (Note 1) digital mode VGC = 2.5V 132 164 VGC = 0.5V 85 110 mA Operating Supply Current FM mode VGC = 2.0V 89 114 VGC = 2.5V 114 142 Addition for IFLO buffer 6.5 9.5 IDLE = 0.6V, cell idle 15 20 STBY = 0.6V, 26 34 TXGATE = 0.6V RFPLL off 11 SHDN = 0.6V, sleep mode 0.5 20 µA Logic High 2.0 V Logic Low 0.6 V Logic Input Current -5 +5 µA VGC Input Current -10 +10 µA VGC Input Resistance During Shutdown SHDN = 0.6V 225 280 kΩ Lock Indicator High 50kΩ pull-up load VCC - 0.4 V Lock Indicator Low 50kΩ pull-up load 0.4V2_,

ELECTRICAL CHARACTERISTICS

(MAX2360/62/64 evaluation kit, 50Ω system, operating modes as defined in Table 6, input voltage at I and Q = 200mVRMS differen- tial, common mode = VCC/2, 300kHz quadrature CW tones, RF and IF synthesizers locked with passive lead-lag second-order loop filter, REF = 200mVp-p at 19.68MHz, VCC = SHDN = IDLE = CS = TXGATE = 2.75V, VBAT = 2.75V, IF output load = 400Ω, LOH, LOL input power = -7dBm, fLOL = 966MHz, fLOH = 1750MHz, IFINH = 125mVRMS at 130MHz, IS-95 CDMA modulation fRFH0 = fRFH1 = 1880MHz, fRFL = 836MHz, TA = +25°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS MODULATOR, QUADRATURE MODES (CDMA, PCS, FM_IQ) IF_BAND = low 120–235 IF Frequency Range MHz IF_BAND = high 120–300 V - I/Q Common-Mode Input Voltage V = 2.7V to 3.0V (Notes 2, 3) 1.35 V /2 CC CC CC V1.25 IF Gain Control Range VGC = 0.5V to 2.5V, IFG = 100 85 dB IF Output Power at IFOUTL and IFOUTH, VGC = 2.5V, IFG = 100, ACPR = -70dBc -10 dBm CDMA Mode Relative to +25°C, T = -40°C to +85°C Gain Variation Over Temperature A -1 +1 dB (Note 4) Carrier Suppression VGC = 2.5V, IFG = 100 30 49 dB Sideband Suppression VGC = 2.5V, IFG = 100 30 38 dB MODULATOR, FM MODE IF Gain Control Range VGC = 0.5V to 2.5V, IFG = 100 85 dB Output Power at IFOUTL VGC = 2.5V, IFG = 111, I/Q modulation -8.5 dBm VGC = 2.5V, IFG = 111, Output Power at IFOUTL -5.5 dBm direct VCO modulation UPCONVERTER AND PREDRIVER IF_BAND = low 120–200 IF Frequency Range MHz IF_BAND = high 180–300 RFL Frequency Range RFL port 800–1000 MHz RFH Frequency Range RFH0 and RFH1 ports 1700–2000 MHz LOL Frequency Range 800–1150 MHz LOH Frequency Range 1400–2300 MHz Cellular frequency operation 1300 RFPLL Frequency Range MHz PCS frequency operation 2300 ACPR = -54dBc 7 Output Power, RFL Port VGC = 2.5V dBm FM mode 12 Output Power, RFH1 Port VGC = 2.6V, ACPR = -54dBc 7.5 dBm Output Power, RFH0 Port VGC = 2.6V, ACPR = -54dBc 6.6 dBm Power Control Range VGC = 0.5V to 2.5V 30 dB Relative to +25°C, TA = -40°C to +85°C Gain Variation Over Temperature ±1 ±2 dB (Note 4) LO Leakage -17 dBm Image Signal -29 dBc _ 3,

ELECTRICAL CHARACTERISTICS (continued)

(MAX2360/62/64 evaluation kit, 50Ω system, operating modes as defined in Table 6, input voltage at I and Q = 200mVRMS differen- tial, common mode = VCC/2, 300kHz quadrature CW tones, RF and IF synthesizers locked with passive lead-lag second-order loop filter, REF = 200mVp-p at 19.68MHz, VCC = SHDN = IDLE = CS = TXGATE = 2.75V, VBAT = 2.75V, IF output load = 400Ω, LOH, LOL input power = -7dBm, fLOL = 966MHz, fLOH = 1750MHz, IFINH = 125mVRMS at 130MHz, IS-95 CDMA modulation fRFH0 = fRFH1 = 1880MHz, fRFL = 836MHz, TA = +25°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS IF_PLL Reference Frequency 5 30 MHz Frequency Reference Signal Level 0.1 0.6 Vp-p IF Main Divide Ratio 256 16384 IF Reference Divider Ratio 2 2048 VCO = low 240–470 VCO Operating Range MHz VCO = high 240–600 IF LO Output Power BUF_EN = 1 -6 dBm ICP = 00 115 175 230 ICP = 01 145 235 315 Charge-Pump Source/Sink Current µA ICP = 10 235 350 470 ICP = 11 300 465 625 Turbolock Boost Current (Note 5) 265 450 615 µA Locked, all values of ICP, over specified Charge-Pump Source/Sink Matching 5 % compliance range Charge-Pump High-Z Leakage Over specified compliance range 10 nA RF_PLL RF Main Divide Ratio 4096 262144 RF Reference Divide Ratio 2 8192 Maximum Phase-Detector Comparison 10 MHz Frequency RCP = 00 100 165 225 RCP = 01 135 230 310 Charge-Pump Source/Sink Current µA RCP = 10 210 340 460 RCP = 11 270 450 630 Turbolock Boost Current (Note 5) 245 435 630 µA Locked, all values of RCP, over specified Charge-Pump Source/Sink Matching 5 % compliance range Charge-Pump High-Z Leakage Over specified compliance range 10 nA RFPLL Input Sensitivity 160 mVp-p Note 1: See Table 6 for register settings. Note 2: ACPR is met over the specified VCM range. Note 3: VCM must be supplied by the I/Q baseband source with ±6µA capability. Note 4: Guaranteed by design and characterization. Note 5: When enabled, turbolock is active during acquisition and injects boost current in addition to the normal charge-pump current. 4 _,

Typical Operating Characteristics

(MAX2360EVKIT, VCC = +2.75V, TA = +25°C, unless otherwise noted.) IF VCO VOLTAGE vs. TIME TANK 1/S11 vs. FREQUENCY OUTPUT POWER, ACPR, ICC vs. VGC MAX2360/2/4-01 MAX2360/2/4-03 20 200CELLULAR CDMA, RFL 10 182 LOCK540164POUT -10 1463 2 -20 128 z0 = 200Ω -30 I

CC

CS -40 92

ADJACENT

-50 74 -60 56 -70 38

ALTERNATE

EQUIVALENT PARALLEL R-C 3: 330MHz, 1.58kΩ, 0.34pF -80 20 TIME (200µs/div) 1: 200MHz, 1.76kΩ, 0.26pF 4: 780MHz, 1.21kΩ, 0.43pF 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2: 260MHz, 1.66kΩ, 0.31pF 5: 1GHz, 0.94kΩ, 0.47pF VGC (V) OUTPUT POWER, ACPR, OUTPUT POWER, ACPR, IF OUTPUT POWER ICC vs. VGC ICC TOTAL vs. VGC vs. VGC AND IF DAC SETTING MAX2360/2/4-04 MAX2360/2/4-05 10 200 10 200 0 PCS CDMA, RFH0 PCS CDMA, RFH1 0 180 0 180 -20 -10 POUT 160 -10 POUT 160 -20 140 -20 140 -40 -30 I 120 -30 I 120CC CC -60 110 -40 100 -40 100 000101 -50 ADJACENT

ADJACENT

80 -50 80 -80 111 001

ALTERNATE

-60 60 -60 60 010 -100 -70 40 -70 40 011

ALTERNATE

-80 20 -80 20 -120 1.5 1.7 1.9 2.1 2.3 2.5 2.7 1.5 1.7 1.9 2.1 2.3 2.5 2.7 0 0.5 1.0 1.5 2.0 2.5 3.0 VGC (V) VGC (V) VGC (V) SIDEBAND SUPPRESSION AND IF OUTPUT POWER vs. VGC IF OUTPUT POWER vs. VGC LO FEEDTHROUGH (IFOUTH) 000-10 -40°C -10 DESIRED -20 -20 -20 -30 +85°C 2.7V, 3.0V, 3.3V -30 -40 -40 -40 -50 -60 -50-60 SIDEBAND LO -70 -60 -80 -80 -70 -90 -80-100 -100 +25°C -90 -110 -120 -100 0 0.5 1.0 1.5 2.0 2.5 3.0 0 0.5 1.0 1.5 2.0 2.5 3.0 129.98 130.18 130.38 130.58 130.78 VGC (V) VGC (V) FREQUENCY (MHz) _ 5 IF POWER (dBm) POUT (dBm), ACPR/ALTR (dBc) VOLTS (1V/div) MAX2360/2/4-07 ICC TOTAL (mA) POUT (dBm) POUT (dBm), ACPR/ALTR (dBc) MAX2360/2/4-08 MAX2360/2/4-02 ICC TOTAL (mA) POUT (dBm) POUT (dBm) POUT (dBm), ACPR/ALTR (dBc) MAX2360/2/4-09 MAX2360/2/4-06 ICC (mA),

Typical Operating Characteristics (continued)

(MAX2360EVKIT, VCC = +2.75V, TA = +25°C, unless otherwise noted.) IFOUTH DIFFERENTIAL PORT IFINH DIFFERENTIAL PORT I/Q BASEBAND FREQUENCY RESPONSE OUTPUT IMPEDANCE INPUT IMPEDANCE MAX2360/2/4-11 MAX2360/2/4-12 0 800 4.0 600 6 700 3.5 -0.5 500 5 600 3.0 -1.0 500 400 4RESISTANCE 2.5

RESISTANCE

-1.5 400 2.0 300 3 300 1.5 -2.0 200 2 200 CAPACITANCE 1.0 CAPACITANCE -2.5 100 0.5 100 1 -3.000000510 15 20 25 30 35 40 45 50 100 120 140 160 180 200 220 240 260 280 300 100 120 140 160 180 200 220 240 260 280 300 FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz) PHASE NOISE LOW-BAND OSCILLATOR PHASE NOISE HIGH-BAND OSCILLATOR vs. FREQUENCY OFFSET (130.38MHz) vs. FREQUENCY OFFSET (165MHz) RFL OUTPUT SPECTRUM -50 -50 10 -60 -60 0 -70 -70 -10 -80 -80 -20 -90 -90 -30 LO -100 -100 -40 -110 -110 -50 -120 -120 -60 -130 -130 -70 DESIRED IMAGE -140 -140 -80 -150 -150 -90 1k 10k 100k 1M 10M 1k 10k 100k 1M 10M 566.38 766.38 966.38 1166.38 1366.38 FREQUENCY (Hz) FREQUENCY (Hz) FREQUENCY (MHz) RFHO CASCADE ACPR RFH0 OUTPUT SPECTRUM vs. POUT AND VBAT CASCADE ACPR vs. POUT AND VBAT 10 -40 -40 VCC = 2.75V VCC = 2.75V -10 -45 3.0V -45 3.0V -20 -50 2.8V -50 2.8V -30 2.7V 2.7V -40 LO -55 -55 -50 -60 -60 -60 -70 IMAGE DESIRED 3.3V-65 -65 3.3V -80 3.6V 3.6V -90 -70 -70 1350 1550 1750 1950 2150 -10 -8 -6 -4 -20246810 -10 -8 -6 -4 -20246810 FREQUENCY (MHz) POUT (dBm) POUT (dBm) 6 _ (dBc/Hz) AMPLITUDE (dBm) (dBc) MAX2360/2/4-16 MAX2360/2/4-13 MAX2360/2/4-10 (dBc/Hz) ACPR (dBc) PARALLEL RESISTANCE (Ω) MAX2360/2/4-17 MAX2360/2/4-14 PARALLEL CAPACITANCE (pF) ACPR (dBc) AMPLITUDE (dBm) PARALLEL RESISTANCE (Ω) MAX2360/2/4-18 MAX2360/2/4-15 PARALLEL CAPACITANCE (pF),

Typical Operating Characteristics (continued)

(MAX2360EVKIT, VCC = +2.75V, TA = +25°C, unless otherwise noted.) ICC vs. RFL OUTPUT POWER (836MHz) ICC vs. RFH0 OUTPUT POWER (1880MHz) ICC vs. RFH1 OUTPUT POWER (1880MHz) 180 180 180 170 170 170 160 160 160 150 150 150 140 140 140 130 130 130 120 120 120 110 110 110 100 100 100 -60 -50 -40 -30 -20 -10 0 10 -60 -50 -40 -30 -20 -10 0 10 -60 -50 -40 -30 -20 -10 0 10 OUTPUT POWER (dBm) OUTPUT POWER (dBm) OUTPUT POWER (dBm) BUFFERED LO OUTPUT LOL PORT S11 LOH PORT S11 -10 -20 -30 -40 -50 5 -60 43 -70432121-80 -90 1: 700MHz, 72Ω –j51Ω 1600MHz TO 2500MHz 2: 966MHz, 60Ω –j46Ω -100 1: 1.6GHz, 40Ω –j25Ω 129.18 129.78 130.38 130.98 131.58 3: 1.22MHz, 52Ω –j38Ω 2: 1.75GHz, 36Ω –j22Ω 4: 1.5GHz, 40Ω –j25Ω 3: 1.88GHz, 34Ω –j18Ω FREQUENCY (MHz) 4: 2.01GHz, 32Ω –j15Ω 5: 2.5GHz, 29Ω –j0Ω_7AMPLITUDE (dBm) ICC (mA) MAX2360/2/4-22 MAX2360/2/4-19 ICC (mA) MAX2360/2/4-23 MAX2360/2/4-21 ICC (mA) MAX2360/2/4-24 MAX2360/2/4-21,

Pin Description PIN

NAME FUNCTION MAX2360 MAX2362 MAX2364 Transmitter RF Output for Cellular Band (800MHz to 1000MHz)—for both FM and digital modes. This open-collector output requires a pull-up inductor to 1 — 1 RFL the supply voltage, which may be part of the output matching network and may be connected directly to the battery. 2, 10, 11, 1, 8, 9, 18, 16, 17, — 19, 30, 31, N.C. No Connection. Make no connection to these pins. 32–35 34, 35, 44 43, 47 Transmitter RF Output for PCS Band (1700MHz to 2000MHz). This open- collector output requires a shunt inductor to the supply voltage. The pull-up22— RFH0 inductor may be part of the output matching network and may be connected directly to the battery. Open-Collector Output Indicating Lock Status of the IF and/or the RF PLLs. 333LOCK Requires a pull-up resistor. Control using configuration register bit LD_MODEO, LD_MODE1. 444VCC Power Supply Digital Input. A logic low on IDLE shuts down everything except the RF PLL555IDLE and associated registers. A small R-C lowpass filter may be used to prevent digital noise. Supply Pin for the Upconverter Stage. VCC must be bypassed to system666VCC ground as close to the pin as possible. The ground vias for the bypass capacitor should not be shared by any other branch. Digital Input. A logic low on TXGATE shuts down everything except the RF777TXGATE PLL, IF PLL, IF VCO, and serial bus and registers. This mode is used for gated transmission. Differential Inputs to the RF Upconverter. These pins are internally biased to IFINL+, 1.5V. The input impedance for these ports is nominally 400Ω differential. The 8, 9 — 8, 9 IFINL- IF filter should be AC-coupled to these ports. Keep the differential lines as short as possible to minimize stray pick-up and shunt capacitance. Differential Inputs to the RF Upconverter. These pins are internally biased to IFINH+, 1.5V. The input impedance for these ports is nominally 400Ω differential. The 10, 11 10, 11 — IFINH- IF filter should be AC-coupled to these ports. Keep the differential lines as short as possible to minimize stray pick-up and shunt capacitance. Bias Resistor Pin. RBIAS is internally biased to a bandgap voltage of 1.18V. An external resistor or current source must be connected to this pin to set the bias 12 12 12 RBIAS current for the upconverters and PA driver stages. The nominal resistor value is 16kΩ. This value can be altered to optimize the linearity of the driver stage. CLK, DI, Input Pins from the 3-Wire Serial Bus (SPI/QSPI/MICROWIRE compatible). 13, 14, 15 13, 14, 15 13, 14, 15 CS An R-C filter on each of these pins may be used to reduce noise. 8 _,

Pin Description (continued) PIN

NAME FUNCTION MAX2360 MAX2362 MAX2364 Differential IF Outputs. These ports are active when the register bit IF_SEL is high. They do not support FM mode. These pins must be inductively pulled up to VCC. A differential IF bandpass filter is connected between this portIFOUTH-, 16, 17 16, 17 — and IFINH+ or IFINH-. The pull-up inductors can be part of the filter structure. IFOUTH+ The differential output impedance of this port is nominally 600Ω. The trans- mission lines from these pins should be short to minimize the pick-up of spu- rious signals and noise. Differential IF Outputs. These ports are active when the register bit IF_SEL is low. These pins must be inductively pulled up to VCC. A differential IF band- IFOUTL+, pass filter is connected between this port and IFINL+ and IFINL-. The pull-up 18, 19 — 18, 19 IFOUTL- inductors can be part of the filter structure. The differential output impedance of this port is nominally 600Ω. The transmission lines from these pins should be short to minimize the pick-up of spurious signals and noise. RF and IF Variable-Gain Control Analog Input. VGC floats to 1.5V. Apply 20 20 20 VGC 0.5V to 2.6V to control the gain of the RF and IF stages. An RC filter on this pin may be used to reduce DAC noise or PDM clock spurs from this line. Supply Pin for the IF VGA. Bypass with a capacitor as close to the pin as 21 21 21 VCC possible. The bypass capacitor must not share its ground vias with any other branches. Supply for the I/Q Modulator. Bypass with capacitor as close to the pin as 22 22 22 VCC possible. The bypass capacitor must not share its ground vias with any other branches. Differential Q-Channel Baseband Inputs to the Modulator. These pins go 23, 24 23, 24 23, 24 Q+, Q- directly to the bases of a differential pair and require an external common- mode bias voltage. Differential I-Channel Baseband Inputs to the Modulator. These pins go 25, 26 25, 26 25, 26 I+, I- directly to the bases of a differential pair and require an external common- mode bias voltage of 1.4V. 27 27 27 Shutdown Input. A logic low on SHDN shuts down the entire IC. An R-C low-SHDN pass filter may be used to reduce digital noise. Supply Pin to the VCO Section. Bypass as close to the pin as possible. The 28 28 28 VCC bypass capacitor should not share its vias with any other branches. Buffered LO Output. Control the output buffer using register bit BUF_EV and 29 29 29 IFLO the divide ratio using the register bit BUF_DIV. TANKL-, Differential Tank Pins for the Low-Frequency IF VCO. These pins are internally 30, 31 — 30, 31 TANKL+ biased to 1.6V. _ 9,

Pin Description (continued) PIN

NAME FUNCTION MAX2360 MAX2362 MAX2364 TANKH-, Differential Tank Pins for the High-Frequency IF VCO. These pins are internally 32, 33 32, 33 — TANKH+ biased to 1.6V. 34, 35 34, 35 34, 35 N.C. No Connection. Leave these pins floating. Reference Frequency Input. REF is internally biased to VCC - 0.7V and must 36 36 36 REF be AC-coupled to the reference source. This is a high-impedance port (25kΩ II 3pF). Supply for the IF Charge Pump. This supply can differ from the system VCC. 37 37 37 VCC Bypass as close to the pin as possible. The bypass capacitor must not share its vias with any other branches. High-Impedance Output of the IF Charge Pump. Connect to the tune input of the IF VCOs through the IF PLL loop filter. Keep the line from IFCP to the tune 38 38 38 IFCP input as short as possible to prevent spurious pick-up, and connect the loop filter as close to the tune input as possible. Supply Pin for Digital Circuitry. Bypass as close to the pin as possible. The 39 39 39 VCC bypass capacitor must not share its vias with any other branch. High-Impedance Output of the RF Charge Pump. Connect to the tune input of the RF VCOs through the RF PLL loop filter. Keep the line from this pin to the 40 40 40 RFCP tune input as short as possible to prevent spurious pick-up, and connect the loop filter as close to the tune input as possible. Supply for the RF Charge Pump. This supply can differ from the system VCC. 41 41 41 VCC Bypass as close to the pin as possible. The bypass capacitor must not share its vias with any other branches. 42 42 42 RFPLL RF PLL Input. AC-couple this port to the RF VCO. 43 43 — LOH High-band RF LO Input Port. AC-couple to this port. 44 — 44 LOL Low-band RF LO Input Port. AC-couple to this port. 45, 46, 48 45, 46, 48 45, 46, 48 GND Ground. Connect to PCB ground plane. Transmitter RF Output for PCS Band (1700MHz to 2000MHz). This open-col- lector output requires a shunt inductor to the supply voltage. The pull-up 47 47 — RFH1 inductor may be part of the output matching network and may be connected directly to the battery. Exposed Exposed Exposed DC and AC GND Return for the IC. Connect to PC board ground plane using

GND

paddle paddle paddle multiple vias. 10 _,

Detailed Description IFLO Output Buffer

The MAX2360 complete quadrature transmitter accepts IFLO provides a buffered LO output when BUF_EN is 1. differential I/Q baseband inputs with external common- The IFLO output frequency is equal to the VCO fre- mode bias. A modulator upconverts this to IF frequency quency when BUF_DIV is 0, and half the VCO frequen- in the 120MHz to 300MHz range. A gain control voltage cy when BUF_DIV is 1. The output power is -6dBm. This pin (VGC) controls the gain of both the IF and RF VGAs output is intended for applications where the receive IF simultaneously to achieve best noise and linearity per- is the same frequency as the transmit IF. formance. The IF signal is brought off-chip for filtering, IF/RF PLL then fed to a single sideband upconverter followed by The IF/RF PLL uses a charge-pump output to drive a the RF VGA and PA driver. The RF upconverter requires loop filter. The loop filter will typically be a passive sec- an external VCO for operation. The IF PLL, RF PLL, and ond-order lead lag filter. Outside the filter’s bandwidth, operating mode can be programmed by an SPI/QSPI/ phase noise will be determined by the tank compo- MICROWIRE-compatible 3-wire interface. nents. The two components that contribute most signifi- The following sections describe each block in the cantly to phase noise are the inductor and varactor. MAX2360 Functional Diagram. Use high-Q inductors and varactors to maximize equiv- alent parallel resistance. The IF_TURBO_CHARGE and I/Q Modulator the RF_TURBO_CHARGE bits in the CONFIG register Differential in-phase (I) and quadrature-phase (Q) input can be set to 1 to enable turbo mode. Turbo mode pro- pins are designed to be DC-coupled and biased with the vides maximum charge-pump current during frequency baseband output from a digital-to-analog converter acquisition. Turbo mode is disabled after the second (DAC). I and Q inputs need a DC bias of VCC/2 and a transition from phase lead to phase lag or from phase current-drive capability of 6µA. Common-mode voltage lag to phase lead. Turbo mode is also disabled after will work within a 1.35V to (VCC - 1.25V) range. Typically, frequency acquisition is achieved. When turbo mode is I and Q will be driven differentially with a 200mVRMS disabled, charge-pump current will return to the pro- baseband signal. Optionally, I and Q may be pro- grammed levels as set by ICP and RCP bits in the grammed for 100mVRMS operation with the IQ_LEVEL bit CONFIG register (Table 4). in the configuration register. The IF VCO output is fed into a divide-by-two/quadrature generator block to derive IF VGA quadrature components to drive the IQ modulator. The The IF VGA allows varying an IF output level that is con- output of the modulator is fed into the VGA. trolled by the VGC. The voltage range on VGC of 0.5V to 2.6V. provide a gain-control range of 85dB. There IF VCOs are two differential IF output ports from the VGA. There are two VCOs to support high IF and low IF appli- IFOUTL+/IFOUTL- are optimized for low IF operation cations. The VCOs oscillate at twice the desired IF fre- (120MHz to 235MHz) for IFOUTH+/IFOUTH- support quency. Oscillation frequency is determined by external high IF operation (120MHz to 300MHz). IFOUTL ports tank components (see Applications Information). support direct VCO FM modulation. The differential IF Typical phase-noise performance for the tank is as output port has an output impedance of 600Ω when shown in Table 1. The high-band and low-band VCOs pulled up to VCC through a choke. can be selected independently of the IF port being used. Single Sideband Mixer The RF transmit mixer uses a single sideband architec-

Table 1. Typical VCO Phase Noise ture to eliminate an off-chip RF filter. The single sideband

(IF = 130.38MHz) mixer has IF input stages that correspond to IF outputports of the VGA. The mixer is followed by the RF VGA. OFFSET (kHz) PHASE NOISE (dBc) The RF VGA is controlled by the same VGC pin as the IF VGA to provide optimum linearity and noise perfor- 1 -80 mance. The total power control range is >100dB. 12.5 -105 30 -111 PA Driver 120 -121 The MAX2360 include three power-amplifier (PA) drivers. Each is optimized for the desired operating frequency. 900 -128 RFL is optimized for cellular-band operation. RFH0 and _ 11, RFH1 are optimized for split-band PCS operation. The The configuration register (CONFIG) sets the configura- PA drivers have open-collector outputs and require tion for the RF/IF PLL and the baseband I/Q input lev- pull-up inductors. The pull-up inductors can act as the els. See Table 4 for a description of each bit. shunt element in a shunt series match. The test register is not needed for normal use. Programmable Registers Power Management The MAX2360/MAX2362/MAX2364 include seven pro- Bias control is distributed among several functional grammable registers consisting of four divide registers, sections and can be controlled to accommodate many a configuration register, an operational control register, different power-down modes as shown in Table 5. and a test register. Each register consists of 24 bits. The 4 least significant bits (LSBs) are the register’s The shutdown control bit is of particular interest since it address. The 20 most significant bits (MSBs) are used differs from the SHDN pin. When the shutdown control for register data. All registers contain some “don't care” bit is active (SHDN_BIT = 0), the serial interface is left bits. These can be either a “0” or a “1” and will not active so that the part can be turned on with the serial affect operation (Figure 1). Data is shifted in MSB first, bus while all other functions remain shut off. In contrast, followed by the 4-bit address. When CS is low, the when the SHDN pin is low it shuts down everything. In clock is active and data is shifted with the rising edge either case, PLL programming and register information of the clock. When CS transitions to high, the shift reg- is lost. To retain the register information, use standby ister is latched into the register selected by the con- mode (STBY = 0). tents of the address bits. Power-up defaults for the Signal Flow Control seven registers are shown in Table 2. The dividers and Table 6 shows an example of key registers for triple- control registers are programmed from the SPI/ mode operation, assuming half-band PCS and IF fre- QSPI/MICROWIRE-compatible serial port. quencies of 130MHz/165MHz. The RFM register sets the main frequency divide ratio for the RF PLL. The RFR register sets the reference fre- Applications Information quency divide ratio. The RF VCO frequency can be The MAX2360 is designed for use in dual-band, triple- determined by the following: mode systems. It is recommended for triple-mode hand- sets (Figure 2). The MAX2362 is designed for use in RF VCO frequency = fREF · (RFM / RFR) CDMA PCS handset or WLL single-mode 2.4GHz ISM IFM and IFR registers are similar: systems (Figure 3). The MAX2364 is designed for use in dual-mode cellular systems (Figure 4). IF VCO frequency = fREF · (IFM / IFR) 3-Wire Interface where fREF is the external reference frequency for the Figure 5 shows the 3-wire interface timing diagram. The MAX2360/MAX2362/MAX2364. 3-wire bus is SPI/QSPI/MICROWIRE compatible. The operational control register (OPCTRL) controls the state of the MAX2360/MAX2362/MAX2364. See Table 3 for the function of each bit.

Table 2. Register Power-Up Default States

REGISTER DEFAULT ADDRESS FUNCTION RFM 172087 dec 0000b RF M divider count RFR 1968 dec 0001b RF R divider count IFM 6519 dec 0010b IF M divider count IFR 0492 dec 0011b IF R divider count OPCTRL 892F hex 0100b Operational control settings CONFIG D03F hex 0101b Configuration and setup control TEST 0000 hex 0111b Test-mode control 12 _, MSB 24 BIT REGISTER LSB DATA 20 BITS ADDRESS 4 BITS B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 A3 A2 A1 A0 RFM DIVIDE RATIO (18) ADDRESS RFM DIVIDE REGISTERXXB17 B16 B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B00000RFR DIVIDE RATIO (13) ADDRESS RFR DIVIDE REGISTERXXXXXXXB12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B00001IFM DIVIDE RATIO (14) ADDRESS IFM DIVIDE REGISTERXXXXXXB13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B00010RFR DIVIDE RATIO (11) ADDRESS IFR DIVIDE REGISTERXXXXXXXXXB10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B00011CONTROL BITS (16) ADDRESS CONTROL REGISTERXXXXB15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B00100CONFIGURATION BITS (16) ADDRESS CONFIGURATION REGISTERXXXXB15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B00101TEST BITS (8) ADDRESS TEST REGISTERXXXXXXXXXXXXB7 B6 B5 B4 B3 B2 B1 B00111X= DON’T CARE Figure 1. Register Configuration

Electromagnetic provides for transient protection against IEC802 testing Compliance Considerations by shunting high frequencies to ground, while the

Two major concepts should be employed to produce a series resistance attenuates the transients for error-free noise-free and EMC-compliant transmitter: minimize cir- operation. The same applies to the override pins cular current-loop area to reduce H-field radiation and (SHDN, TXGATE, IDLE). minimize voltage drops to reduce E-field radiation. To High-frequency bypass capacitors are required close minimize circular current-loop area, bypass as close to to the pins with a dedicated via to ground. The 48-pin the part as possible and use the distributed capaci- TQFP-EP package provides minimal inductance ground tance of a ground plane. To minimize voltage drops, by using an exposed paddle under the part. Provide at make VCC traces short and wide, and make RF traces least five low-inductance vias under the paddle to short. ground, to minimize ground inductance. Use a solid The “don't care” bits in the registers should be “0” in ground plane wherever possible. Any cutout in the order to minimize electromagnetic radiation due to ground plane may act as slot radiator and reduce its unnecessary bit banging. RC filtering can also be used shield effectiveness. to slow the clock edges on the 3-wire interface, reduc- Keep the RF LO traces as short as possible to reduce ing high-frequency spectral content. RC filtering also LO radiation and susceptibility to interference. _ 13,

Table 3. Operation Control Register (OPCTRL) BIT

POWER-UP BIT NAME LOCATION FUNCTION STATE (0 = LSB) LO_SEL 1 15 1 selects LOL input port; 0 selects LOH port. 1 keeps RF turbo-mode current active even when frequency acquisition is RCP_MAX 0 14 achieved. This bit has no effect when RF_TURBO_CHARGE = 0. This mode is used when high operating RF charge-pump current is needed. 1 keeps IF turbo-mode current active even when frequency acquisition is ICP_MAX 0 13 achieved. This bit has no effect when IF_TURBO_CHARGE = 0. This mode is used when high operating IF charge-pump current is needed. Sets operating mode according to the following: 00 = FM mode MODE 01 12, 11 01 = Cellular digital mode, RFL is selected 10 = PCSHIGH mode, RFH1 is selected 11 = PCSLOW mode, RFH0 is selected 1 selects IFINH and IFOUTH; 0 selects IFINL and IFOUTL. For FM mode IF_BAND 0 10 (MODE = 00), set IF_BAND to 0. VCO091selects high-band IF VCO; 0 selects low-band IF VCO. 3-bit IF gain control. Alters IF gain by approximately 2dB per LSB (0 to 14dB). IFG 100 8, 7, 6 Provides a means for adjusting balance between RF and IF gain for optimized linearity. When this register is 1, the upper sideband is selected (LO below RF). When SIDE_BAND15this register is 0, the lower sideband is selected (LO above RF). BUF_EN040turns IFLO buffer off; 1 turns IFLO buffer on. 0 selects direct VCO modulation. (IF VCO is externally modulated and the I/Q MOD_TYPE13modulator is bypassed); 1 selects quadrature modulation. STBY120shuts down everything except registers and serial interface. 0 shuts down modulator and upconverter, leaving PLLs locked and registers TXSTBY11active. This is the programmable equivalent to the TXGATE pin. 0 shuts down everything except serial interface, and also resets all registers to SHDN_BIT10power-up state. 14 _,

Table 4. Configuration Register (CONFIG) BIT

POWER-UP BIT NAME LOCATION FUNCTION

STATE

(0 = LSB) IF_PLL_SHDN 1 15 0 shuts down the IF PLL. This mode is used with an external IF VCO and IF PLL. RF_PLL_ 1 14 0 shuts down the BF PLL. This mode is used with an external RF PLL.

SHDN

RESERVED 0 13 Must be set to 0 for normal operation. IQ_LEVEL 1 12 1 selects 200mVRMS input mode; 0 selects 100mVRMS input mode. BUF_DIV 0 11 1 selects ÷2 on IFLO port; 0 bypasses the divider. VCO_BYPASS 0 10 1 bypasses IF VCO and enables a buffered input for external VCO use. A 2-bit register sets the IF charge-pump current as follows: 00 = 175µA ICP 00 9, 8 01 = 235µA 10 = 350µA 11 = 465µA A 2-bit register sets the RF charge-pump current as follows: 00 = 165µA RCP 00 7, 6 01 = 230µA 10 = 340µA 11 = 450µA IF phase-detector polarity; 1 selects positive polarity (increasing tuning voltage IF_PD_POL15on the VCO produces increasing frequency); 0 selects negative polarity (increasing tuning voltage on the VCO produces decreasing frequency). RF phase-detector polarity; 1 selects positive polarity (increasing tuning voltage RF_PD_POL14on the VCO produces increasing frequency); 0 selects negative polarity (increasing voltage on the VCO produces decreasing frequency). IF_TURBO_ 1 activates turbocharge feature, providing an additional 450µA of IF charge- 1 3 CHARGE pump current during frequency acquisition. RF_TURBO_ 1 activates turbocharge feature, providing an additional 435µA of IF charge- 1 2 CHARGE pump current during frequency acquisition. Determines output mode for LOCK detector pin as follows: 00 = test mode, LD_MODE cannot be 00 for normal operation LD_MODE 11 1, 0 01 = IF PLL lock detector 10 = RF PLL lock detector 11 = logical AND of IF PLL and RF PLL lock detectors _ 15,

Table 5. Power-Down Modes

POWER-DOWN

COMMENTS MODE

SHDN Pin Ultra-low shutdown currentXXXXXXXXXXXIDLE Pin IDLE is low in RX modeXXXXXXTXGATE pin For punctured TX modeXXRF PLL SHDN For external RF PLL useXXIF PLL SHDN For external IF PLL useXXTX STBY TX is OFF, but IF and RF LOs stay lockedXXREG STBY Shuts down, but preserves registersXXXXXXREG SHDN Serial bus is still activeXXXXXXXXXXX= Off

Table 6. Register and Control Pin States for Key Operating Modes

CONFIG CONTROL OPCTRL REGISTER REGISTER PINS MODE DESCRIPTION PCS High PCS upper half-band, RFH1 selected 0 1011111111HHHPCS Low PCS lower half-band, RFH0 selected 0 1111111111HHHCellular Digital RFL selected 1 0100111111HHHFM Direct VCO modulation, RFL selected 1 0000011111HHHPCS Idle Listen for pages RX ON, TX OFF 0 1XXXX1X1X1LHHCellular Idle Listen for pages RX ON, TX OFF 1 0XXXX1X1X1LHHPCS TXGATE Gated transmission, PCS 0 1X1111X111HLHCellular TXGATE Gated transmission, cellular digital 1 010011X111HLHSleep Everything off X XXXXXXXXXXXXLX= Don’t care 16 _ LO SEL

MODE

IF BAND

VCO UPCONVERTER

FM TYPE

MODULATOR STBY

SERIAL BUS

TXSTBY

RF PLL SHDN_BIT RF PLL REGS IF PLL SHDN OPCTRL REG RF PLL SHDN IF LO BUFF IDLE IF VCO TXGATE IF PLL SHDN IF PLL REGS CONFIG REG, Figure 2. MAX2360 Typical Application Circuit _ 17

VREG

VBAT VBAT 100pF 100pF 100pF PCS Rx 1960MHz CELL PCS VCO VCO 5nH 22nH PCS V1880MHz BAT DUPLEXER 33pF 10k50Ω 33pF 33pF 33pF PCS 3.3pF

PA

8.7µH CELL RX 48 47 46 45 44 43 42 41 40 39 38 37 3300pF 0.033µF 3pF VCC 0.033µFDIPLEXER CELL 1 RF PPL 36 19.68MHz 10k

PA

CELL TCXO DUPLEXER 836MHzV235 N.C.REG IF PPL 12pF 10k 51k LOCK 3 34 N.C. 100pF TANKH4V33 22nH 4.3pFCC Σ 12pF 10k IDLE 5 90 32 0 TANK L 18pF 10k VREG 6 VCC MAX2360 31 1000pF TXGATE 7 45 -45 30 39nH 2.4pF 8 18pF/2 29 IFLO 10k 9 28 VREG 100pF 10 27 SHDNΣ0/2 11 90 26 DAC I 12 RBIAS 25 CLK DI CS VGC VCC 130MHz 16k 13 14 15 16 17 18 19 20 21 22 23 24 DAC Q 165MHz

VREG

3 WIRE 100pF 100pF

DAC

3300pF 0.033µF, Figure 3. MAX2362 Typical Application Circuit 18 _ VBAT VBAT PCS VCO 100pF 100pF 100pF PCS Rx V 1960MHz REG 5nH 22nH PCS 1880MHz DUPLEXER 33pF 10k 33pF 33pF

PCS

PA 3.3pF N.C. 48 47 46 45 44 43 42 41 40 39 38 37 3300pF 0.033µF VCC VCC 0.033µF 1 N.C. RF PLL 36 19.68MHz 10k

TCXO

V 2 35 N.C.REG IF PLL 18pF 10k 51k LOCK 3 34 N.C. 100pF TANK 4 VCC 33 39nH 2.4pF Σ 18pF 10k IDLE 5 90 32 VREG 6 VCC MAX2362 31 N.C. 1000pF TXGATE 7 45 -45 30 N.C. 47pF N.C. 8 /2 29 IFLO N.C. 9 28 VREG 100pF 10 27 SHDNΣ0/2 11 90 26 DAC I 12 RBIAS 25 CLK DI CS VGC VCC 130MHz 16k 13 14 15 16 17 18 19 20 21 22 23 24 N.C. N.C. DAC Q

VREG

3 WIRE 100pF 100pF

DAC

3300pF 0.033µF, Figure 4. MAX2364 Typical Application Circuit _ 19

PCS

VCO 100pF 100pF 100pF

VREG

CELL Rx 880MHz VBAT 10k 33pF 33pF

CELL

DUPLEXER N.C. N.C.8.7nH 48 47 46 45 44 43 42 41 40 39 38 37 3300pF 0.033µF 3pF 0.033µF CELL 1 RF PLL 36 19.68MHz 10kPA TCXO 836MHz N.C. V 2 35 N.C.REG IF PLL 51k LOCK 3 34 N.C. 100pF4VΣCC 33 N.C. IDLE5032 N.C. TANK L 18pF 10k VREG 6 VCC MAX2364 31 45 -45 1000pF TXGATE 7 30 39nH 2.4pF 47pF 8 29 18pF/2 IFLO 10k 9 28 VREG 100pF N.C. 10 27 SHDNΣ0/2 N.C. 11 90 26 DAC I 12 RBIAS 25 CLK DI CS VGC VCC 130MHz 16k 13 14 15 16 17 18 19 20 21 22 23 24 N.C. N.C. DAC Q

VREG

3 WIRE 100pF 100pF

DAC

3300pF 0.033µF, DI B19 (MSB) B18 B0 A3 A1 A0 (LSB) tCS > 50µs tCH > 10µs tCWH > 50µs CLK tES > 50µs tCWL tCS tCH tCWH tES

CS

Figure 5. 3-Wire Interface Diagram IF Tank Design The low-band tank (TANKL+, TANKL-) and high-band tank (TANKH+, TANKH-) are fully differential. The exter- nal tank components are shown in Figure 6. The fre- quency of oscillation is determined by the following CC MAX2360 equation: MAX2362 = 1fOSC MAX2364

CD

2π (CINT + CCENT + CVAR + CPAR) L CCENT L CPAR CINT -Rn = CD ⋅ C

CD CVAR C

2 (CD + CC)

CC

CINT = Internal capacitance of TANK port CD = Capacitance of varactor CVAR = Equivalent variable tuning capacitance CPAR = Parasitic capacitance due to PCB pads and Figure 6. Tank Port Oscillator traces CCENT = External capacitor for centering oscillation fre- Power-Supply Layout quency To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration, CC = External coupling capacitor to the varactor which has a large decoupling capacitor at a central Internal to the IC, the charge pump will have a leakage VCC node. The VCC traces branch out from this node, of less than 10nA. This is equivalent to a 300MΩ shunt each going to a separate VCC node in the MAX2360/ resistor. The charge-pump output must see an MAX2362/MAX2364 circuit. At the end of each trace is extremely high DC resistance of greater than 300MΩ. a bypass capacitor with impedance to ground less than This will minimize charge-pump spurs at the compari- 1Ω at the frequency of interest. This arrangement pro- son frequency. Make sure there is no solder flux under vides local decoupling at each VCC pin. Use at least the varactor or loop filter. one via per bypass capacitor for a low-inductance

Layout Issues ground connection.

The MAX2360/MAX2362/MAX2364 EV kit can be used Matching Network Layout as a starting point for layout. For best performance, The layout of a matching network can be very sensitive take into consideration power-supply issues as well as to parasitic circuit elements. To minimize parasitic the RF, LO, and IF layout. inductance, keep all traces short and place compo- nents as close to the IC as possible. To minimize para- sitic capacitance, a cutout in the ground plane (and 20 _, any other planes) below the matching network compo- Tank Layout nents can be used. Keep the traces coming out of the tank short to reduce On the high-impedance ports (e.g., IF inputs and out- series inductance and shunt capacitance. Keep the puts), keep traces short to minimize shunt capacitance. inductor pads and coupling capacitor pads small to minimize stray shunt capacitance.

Selector Guide

RF RANGE PART IF RANGE (MHz) RF LO RANGE (MHz) (MHz) 120 to 235 800 to 1150 800 to 1000 MAX2360 120 to 300 1400 to 2300 1700 to 2000 MAX2362 120 to 300 1400 to 2300 1700 to 2000 MAX2364 120 to 235 800 to 1150 800 to 1000 _ 21,

Pin Configurations (continued)

TOP VIEW RFL 1 36 REF N.C. 1 36 REF RFH0 2 35 N.C. RFH0 2 35 N.C. LOCK 3 34 N.C. LOCK 3 34 N.C. VCC 4 33 TANK H+ VCC 4 33 TANK H+ IDLE 5 32 TANK H- IDLE 5 32 TANK H- VCC 6 MAX2360 31 TANK L+ VCC 6 MAX2362 31 N.C. TXGATE 7 30 TANK L- TXGATE 7 30 N.C. IFINL+ 8 29 IFLO N.C. 8 29 IFLO IFINL- 9 28 VCC N.C. 9 28 VCC IFINH+ 10 27 SHDN IFINH+ 10 27 SHDN IFINH- 11 26 I- IFINH- 11 26 I- RBIAS 12 25 I+ RBIAS 12 25 I+ TQFP-EP TQFP-EP RFL 1 36 REF N.C. 2 35 N.C. LOCK 3 34 N.C. VCC 4 33 N.C. IDLE 5 32 N.C. VCC 6 MAX2364 31 TANK L+ TXGATE 7 30 TANK L- IFINL+ 8 29 IFLO IFINL- 9 28 VCC N.C. 10 27 SHDN N.C. 11 26 I- RBIAS 12 25 I+ BOTTOM SIDE GND TQFP-EP 22 _ CLK 13 48 GND DI 14 47 RFH1 CS 15 46 GND IFOUTH- 16 45 GND IFOUTH+ 17 44 LOL IFOUTL+ 18 43 LOH IFOUTL- 19 42 RFPLL VGC 20 41 VCC VCC 21 40 RFCP VCC 22 39 VCC Q+ 23 38 IFCP Q- 24 37 VCC CLK 13 48 GND DI 14 47 N.C. CS 15 46 GND N.C. 16 45 GND N.C. 17 44 LOL IFOUTL+ 18 43 N.C. IFOUTL- 19 42 RFPLL VGC 20 41 VCC VCC 21 40 RFCP VCC 22 39 VCC Q+ 23 38 IFCP Q- 24 37 VCC CLK 13 48 GND DI 14 47 RFH1 CS 15 46 GND IFOUTH- 16 45 GND IFOUTH+ 17 44 N.C. N.C. 18 43 LOH N.C. 19 42 RFPLL VGC 20 41 VCC VCC 21 40 RFCP VCC 22 39 VCC Q+ 23 38 IFCP Q- 24 37 VCC, Package Information _ 23 48L,TQFP.EPS,

Package Information (continued)

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 24 _Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2000 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.]

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