Download: SECAM chroma signal processor for VHS VCRs •Applications •Features •Absolute maximum ratings (Ta = 25°C)

Video ICs

SECAM chroma signal processor for VHS VCRs BA7207AS / BA7207AK

The BA7207AS and BA7207AK are LSI components that incorporate the contain circuitry required for SECAM chro- ma signal processing. The ICs have both recording and playback systems and each includes a bell filter, a band- pass filter, a limiter amplifier, a multiply-by-four circuit, a divide-by-four circuit, and a sync-gate circuit. •Applications SECAM and VHS format video cassette recorders and camcorders •Features 1) All filters required for SECAM chroma signal pro- 3) Built-in switch circuit for selecting PAL chroma or cessing are provided. SECAM chroma for the PB / REC system output. 2) Built-in chroma killer circuit. •Absolute maximum ratings (Ta = 25°C) Parameter Symbol Limits Unit Power supply voltage VCC7VBA7207AS 1400 (SDIP32)∗1 Power dissipation Pd mW BA7207AK 850 (QFP44)∗2 BA7207AS – 25 ~ + 75 Operating temperature Topr °C BA7207AK – 25 ~ + 65 Storage temperature Tstg – 55 ~ + 125 °C ∗1 Reduced by 14mW for each increase in Ta of 1°C over 25°C . ∗2 When mounted on a 70mm × 70mm, t = 1.6mm glass epoxy board, reduced by 8.5W for each increase in Ta of 1°C over 25°C. •Recommended operating conditions (Ta = 25°C) Parameter Symbol Min. Typ. Max. Unit Operating power supply voltage VCC 4.5 5.0 5.5 V, •Block diagram

BA7207AS (SDIP32)

32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

MODE CONTOROL VREG

PAL SCM LIMRP× 2 2.2MHzBPF × 2 LIM 1.1MHzP EQ BPF

R

4.3MHz PBPRRECPPBPF - B SYNC GATE ÷ 4 SYNC GATE 4.3MHzRRBPF—A BELLRPDET VCO SYNC GATE TIMINGGENERATOR SCM PAL

FREQUENCY ADJUSTER

12345678910 11 12 13 14 15 16

BA7207AK (SQFP44)

33 32 31 30 29 28 27 26 25 24 23

VCC

TRAP 34 22 CREF3

LIM MODE

PALRIN 35 CONTROL 21 RECH PAL SCM VREG 36 VREG 20 PBIN N.C. 37 19 N.C.

P

P R × 4O 38 × 2 2.2MHz × 2 LIM EQ 1.1MHz 18 BWLBPF BPFRPRN.C. 39 R 17 N.C.P P 4.3MHz R BPF—A BELL 4.3MHz PB REC BPF—B SYNC GATE ÷ 4 SYNC GATE RECIN 40 16 SYNCINRPSYNC GATE N.C. 41 FREQUENCY DET VCO TIMING 15 N.C. ADJUSTER GENERATOR MUL 42 14 DIV SCM PAL FADJ1 43 13 PALPIN FADJ2 44 12 SGC12345678910 11 RECIN × 4O

MUL VREG

GND1 RECOUT FADJ1 PALRIN AMPOUT CREF2 FADJ2 TRAP GND ABELO GND1 RECOUT N.C. N.C. AMPOUT CREF2 GND ABELO SCMPIN CREF1 SCMPIN CREF1 N.C. N.C. DET LAIN DET LAIN VCO VCC N.C. N.C. PBOUT LAO SGADJ CTL VCO VCC SGC CREF3 PBOUT LAO PALPIN RECH SGADJ CTL DIV PBIN SYNCIN BWL, •Pin descriptions Pin No.Pin name Function Pin No. Pin name Function Recording system input. 17 (18) BWL Chroma killer mode setting . "L" sets the IC in 1 (40) RECIN Input the REC system chroma signal. chroma killer mode. PB sync gate output. PB system input . Test pin. Outputs the chroma signal after it is 18 (20) PBIN Input chroma signal for the PB system. 2 (42) MUL multiplied by four and passed through the sync gate. Normally connected to VCC to prevent REC / PB mode switch. interference. 19 (21) RECH Set to open or "H" for REC mode, "L" for PB Filter fo adjustment pin 1. mode. 3 (43) FADJ1 Used to adjust fo for the equalizer, 1.1MHz BPF Bias terminal for the limiter amplifier before × 2. and 2.2MHz BPF. Connect a resistor and variable 20 (22) CREF3 Connect to GND via a capacitor. resistor from this pin to GND. Filter fo adjustment pin 2. SECAM / PAL output switch. Used to adjust fo for the bell filter, 4.3MHz BPF-A 21 (23) CTL Selects the signal output for the REC / PB 4 (44) FADJ2 and 4.3MHz BPF-B. Connect a resistor and terminal. Set to open or "H" for SECAM output variable resistor from this pin to GND. mode, "L" for PAL mode. Limiter amplifier output. 5 (1) GND1 Ground. Test pin. Outputs the amplitude-limited chroma 22 (24) LAO signal. Normally connected to VCC to prevent PB system preamplifier output. 6 (2) AMPOUT interference.Connect to GND via a variable resistor to adjust the level, and input to pin 8. 23 (25) VCC Power supply. 7 (3) GND Ground. Limiter amplifier input. 24 (27) LAIN Input the de-emphasised chroma signal. PB system output amplifier input. 8 (5) SCMPIN Input the level-adjusted PB system SECAM Limiter amplifier bias pin 1. chroma signal. 25 (29) CREF1 Connect to GND via a capacitor. Phase comparator output. REC BELL output. When in REC mode, 9 (7) DET Connect to GND via a RC LPF to obtain the error de-emphasised chroma signal is output via REC voltage. 26 (31) ABELO BELL. When in PB mode, the PB system chroma signal is output after being multiplied by four. VCO oscillator frequency control pin. The error voltage is input via a resistor. 10 (9) VCO Connected to GND via free-running frequency Limiter amplifier bias pin 2.27 (32) CREF2 setting resistor. Connect to GND via a capacitor. PB system output. REC system output. 11 (10) PBOUT 28 (33) RECOUTOutputs the PB system chroma signal. REC system chroma signal output. Fine adjustment for the sync gate phase. TRAP connection. The voltage from a resistor divider is used for fine 29 (34) TRAP Connect TRAP that rejects spurious signal 12 (11) SGADJ adjustment of the gate phase of the sync gate. component after × 2 multiplication. Normally open. PAL REC system input. 30 (35) PALRIN Sync gate timing output. PAL REC system chroma signal input. 13 (12) SGC Test pin. Outputs the REC sync gate timing. Normally open. Regulated voltage output. Output for the regulated 2.5V reference voltage 31 (36) VREG PAL PB system input. used for internal biasing. Connect to GND via a 14 (13) PALPIN Input chroma signal for the PAL PB system. bypass capacitor. Divide-by-four divider output. × 4 multiply output. Test pin. Outputs the chroma signal after it has 15 (14) DIV 32 (38) × 40 Test pin. Outputs the chroma signal after it is been divided by four. Normally connected to VCC multiplied by four. Normally connected to VCC to to prevent interference. prevent interference. Delayed sync signal input. BA7207AK pin numbers are given in brackets. 16 SYNCIN Input the synchronously-separated composite, •Input / output circuits 1pin 2pin 3pin (40pin) (42pin) (43pin)

VCC VCC

VCC VCC 40k VCC RECIN FADJ1 40k MUL GND GND

GND GND

4pin 5pin 6pin (44pin) (1pin) (2pin)

VCC VCC VCC VCC

GND1 FADJ2

GND AMPOUT

GND 5k

GND GND

7pin 8pin 9pin (3pin) (5pin) (7pin) VCC VCC 20k 20k

GND

SCMPIN SCMPIN

GND

30k 30k GND GND, 10pin 11pin 12pin (9pin) (10pin) (11pin) VCC VCC VCC

VCC

50k 5k 12k VCC 100k VCO SGADJ PBOUT GND

GND

2.2k 50k GND GND

GND

13pin 14pin 15pin (12pin) (13pin) (14pin)

VCC

VCC VCC

VCC

10k 20k SGC PALPIN 10k 30k DIV GND GND

GND

16pin 17pin 18pin (18pin) (20pin)

VCC

VCC VCC 20k 50k 15k SYNCIN BWL PBIN 35k 20k GND GND

GND

19pin 20pin 21pin (21pin) (22pin) (23pin) VCC VCC VCC 50k 50k RECH CREF3 CTL GND GND GND, 22pin 23pin 24pin (24pin) (25pin) (27pin)

VCC VCC

VCC LAIN

VCC

2k VCC GND

LAO GND GND

25pin 26pin 27pin (29pin) (31pin) (32pin) VCC VCC VCC 2k VCC 2k CREF1 CREF2 30k 30k

ABELO

GND GND 1.8k GND GND GND 28pin 29pin 30pin (33pin) (34pin) (35pin)

VCC

VCC VCC VCC 20k TRAP PALRIN RECOUT 200 30k 1.8k GND GND

GND

31pin 32pin (36pin) (38pin)

VCC VCC VCC VCC VREG

× 4O 3k 3k

GND

5.3k GND Pin numbers in parentheses are for the BA7207AK., •Electrical characteristics (unless otherwise noted, Ta = 25°C, VCC = 5.0V) Parameter Symbol Min. Typ. Max. Unit Conditions Measurementcircuit [Total device] REC mode supply current IREC 39.2 56.0 72.8 mA REC mode Fig.1 PB mode supply current IPB 46.9 67.0 87.1 mA PB mode Fig.1 Regulator voltage VREG 2.38 2.53 2.68 V Fig.1 [Sync-gate block] VCO free-running frequency fosc 13.8 15.625 17.4 kHz Fig.1 Capture range "H" CRH 1.8 — — kHz Delayed sync input Fig.1 Capture range "L" CRL — — – 1.8 kHz Delayed sync input Fig.1 Lock range "H" LRH 2.2 — — kHz Delayed sync input Fig.1 Lock range "L" LRL — — – 2.2 kHz Delayed sync input Fig.1 [REC system] RECOUT output amplitude VREC 187.5 250.0 312.5 mVP-P Cyan level (cyan frequency) Fig.1 Unwanted spectrum rejection 4MHz component HDR4 — — – 25 dB V1 = 170mVP-P, 4.286MHz Fig.1 3MHz component HDR3 — — – 25 dB V1 = 170mVP-P, 4.286MHz Fig.1 2MHz component HDR2 — — – 25 dB V1 = 170mVP-P, 4.286MHz Fig.1 Output switch voltage gain GRS – 101dB V30 = 0.3VP-P, 627kHz Fig.1 Output switch frequency characteristic fRS – 101dB V30 = 0.3VP-P, 5MHz / 100kHz Fig.1 Output switch crosstalk 1 CTR1 — – 60 — dB V18 = 25mVP-P, 1.0715MHz Fig.1 Output switch crosstalk 2 CTR2 — – 60 — dB V30 = 0.3VP-P, 627kHz Fig.1 [PB system] PB output amplitude VPB 202.5 270.0 337.5 mVP-P Cyan level (cyan frequency) Fig.1 Unwanted spectrum rejection 3MHz component HDP3 — — – 35 dB V18 = 25mVP-P, 1.0715MHz Fig.1 2MHz component HDP2 — — – 35 dB V18 = 25mVP-P, 1.0715MHz Fig.1 1MHz component HDP1 — — – 35 dB V18 = 25mVP-P, 1.0715MHz Fig.1 Output switch voltage gain 1 GP1567dB V8 = 0.3VP-P, 4.3MHz Fig.1 Output switch frequency characteristic 1 fP1 – 101dB V8 = 0.3VP-P, 5MHz / 100kHz Fig.1 Output switch crosstalk 1 CTP1 — – 60 — dB V8 = 0.3VP-P, 4.3MHz Fig.1 Output switch voltage gain 2 GP2 – 101dB V14 = 0.3VP-P, 4.43MHz Fig.1 Output switch frequency characteristic 2 fP2 – 101dB V14 = 0.3VP-P, 5MHz / 100kHz Fig.1 Output switch crosstalk 2 CTP2 — – 60 — dB V14 = 0.3VP-P, 4.43MHz Fig.1 RECIN crosstalk CTRIN — – 40 – 30 dB V1 = 0.5VP-P, 4.286MHz Fig.1 [Control system] Pins 14, 17, 19, 21 and 30 High level voltage VH 2.5 — — V (Pins 13,18,21,23 and 35)∗ Fig.1 Pins 14, 17, 19, 21 and 30 Low level voltage VL — — 1.5 V (Pins 13,18,21,23 and 35)∗ Fig.1 ∗ BA7207AK pin numbers are given in brackets., Parameter Symbol Min. Typ. Max. Unit Conditions Measurementcircuit [Filter block] 〈1.1MHz BPF characteristic〉 1.1MHz voltage gain GF11 – 2.8 0.7 4.2 dB V18 = 25mVP-P, 1.0715MHz Fig.1 0.5MHz voltage gain GF12 – 6.5 – 3.0 0.5 dB V18 = 25mVP-P, 0.5MHz Fig.1 3.2MHz voltage gain GF13 — – 35.0 – 26.0 dB V18 = 25mVP-P, 3.2145MHz Fig.1 〈4.3MHz BPF - A characteristic〉 4.3MHz voltage gain GF31 – 11.3 – 7.8 – 4.3 dB V1 = 500mVP-P, 4.286MHz Fig.1 3.2MHz voltage gain GF32 – 16.1 – 12.6 – 9.1 dB V1 = 500mVP-P, 3.2MHz Fig.1 5.5MHz voltage gain GF33 – 14.0 – 10.5 – 7.0 dB V1 = 500mVP-P, 5.5MHz Fig.1 〈REC BELL + 4.3MHz BPF - A characteristic〉 4.3MHz voltage gain GRB1 – 0.7 2.8 6.3 dB V1 = 170mVP-P, 4.286MHz Fig.1 4.1MHz voltage gain GRB2 – 7.0 – 3.5 0 dB V1 = 170mVP-P, 4.1MHz Fig.1 4.5MHz voltage gain GRB3 – 7.2 – 3.7 – 0.2 dB V1 = 170mVP-P, 4.5MHz Fig.1 〈PB BELL + 4.3MHz BPF - A characteristic〉 4.3MHz voltage gain GPB1 – 20.9 – 17.4 – 13.9 dB V1 = 800mVP-P, 4.286MHz Fig.1 4.1MHz voltage gain GPB2 – 16.2 – 12.7 – 9.2 dB V1 = 800mVP-P, 4.1MHz Fig.1 4.5MHz voltage gain GPB3 – 15.3 – 11.8 – 8.3 dB V1 = 800mVP-P, 4.5MHz Fig.1 〈REC EQ + 1.1MHz BPF characteristic〉 1.1MHz voltage gain GRE1 – 4.0 – 0.5 3.0 dB V18 = 95mVP-P, 1.0715MHz Fig.1 1.0MHz voltage gain GRE2 4.1 7.6 11.1 dB V18 = 95mVP-P, 1.0MHz Fig.1 1.2MHz voltage gain GRE3 6.7 10.2 13.7 dB V18 = 95mVP-P, 1.2MHz Fig.1 〈PB EQ + 1.1MHz BPF characteristic〉 1.1MHz voltage gain GPE1 2.5 6.0 9.5 dB V18 = 25mVP-P, 1.0715MHz Fig.1 1.0MHz voltage gain GPE2 – 5.1 – 1.6 1.9 dB V18 = 25mVP-P, 1.0MHz Fig.1 1.2MHz voltage gain GPE3 – 8.9 – 5.4 – 1.9 dB V18 = 25mVP-P, 1.2MHz Fig.1 •Guaranteed design parameters (unless otherwise noted, Ta = 25°C, VCC = 5.0V, delayed sync input) Parameter Symbol Min. Typ. Max. Unit Conditions REC sync-gate phase TDR 1.3 2.4 3.5 µs DIV (pin 14 / pin 15), REC mode PB sync-gate phase TDP 0.5 1.6 2.7 µs MUL (pin 2 / pin 42), PB mode REC sync-gate amplitude TWR 4.9 5.2 5.5 µs DIV (pin 15 / pin 14), REC mode PB sync-gate amplitude TWP 6.1 6.4 6.7 µs MUL (pin 2 / pin 42), PB mode The pin numbers in brackets are for the BA7207AS and the BA7207AK respectively., •Reference design data (unless otherwise noted, Ta = 25°C, VCC = 5.0V, fo (REC BELL) = 4.286MHz, fo (PB EQ) = 1.0715MHz) Parameter Symbol Min. Typ. Max. Unit Conditions 〈1.1MHzBPF〉 1.1MHz gain GF11 — 1.0 — dB VIN = 0.3VP-P, 1.0715MHz 0.5MHz suppression ratio GF12 — – 4.0 — dB VIN = 0.3VP-P, 0.5MHz 3.2MHz suppression ratio GF13 — – 30.0 — dB VIN = 0.3VP-P, 3.2145MHz Groupe delay time DF1 370 420 470 nS VIN = 0.3VP-P, 1.0715MHz 〈2.2MHzBPF〉 2.2MHz gain GF21 — – 6.0 — dB VIN = 0.3VP-P, 2.143MHz 1.1MHz suppression ratio GF22 — – 25.0 — dB VIN = 0.3VP-P, 1.0715MHz 3.2MHz suppression ratio GF23 — – 25.0 — dB VIN = 0.3VP-P, 3.2145MHz Groupe delay time DF2 180 230 280 ns VIN = 0.3VP-P, 2.143MHz 〈4.3MHz BPF - A〉 4.3MHz gain GF31 — 7.0 — dB VIN = 0.1VP-P, 4.286MHz 3.2MHz suppression ratio GF32 — – 3.0 — dB VIN = 0.1VP-P, 3.2MHz 5.5MHz suppression ratio GF33 — – 3.0 — dB VIN = 0.1VP-P, 5.5MHz Groupe delay time DF3 160 210 260 nS VIN = 0.1VP-P, 4.286MHz 〈4.3MHz BPF - B〉 4.3MHz gain GF41 — 9.0 — dB VIN = 0.1VP-P, 4.286MHz 3.5MHz suppression ratio GF42 — – 3.0 — dB VIN = 0.1VP-P, 3.5MHz 5.2MHz suppression ratio GF43 — – 3.0 — dB VIN = 0.1VP-P, 5.2MHz Groupe delay time DF4 250 300 350 nS VIN = 0.1VP-P, 4.286MHz 〈REC BELL〉 4.3MHz gain GRB1 — 19.5 — dB VIN = 0.3VP-P, 4.286MHz 4.1MHz suppression ratio GRB2 — – 5.0 — dB VIN = 0.3VP-P, 4.1MHz 4.5MHz suppression ratio GRB3 — – 5.5 — dB VIN = 0.3VP-P, 4.5MHz 〈PB BELL〉 4.3MHz gain GPB1 — – 19.5 — dB VIN = 0.3VP-P, 4.286MHz 4.1MHz gain GPB2 — 5.0 — dB VIN = 0.3VP-P, 4.1MHz 4.5MHz gain GPB3 — 5.5 — dB VIN = 0.3VP-P, 4.5MHz Center frequency ratio dfOB – 101% dfOB = (fO (PB) – fO (REC) ) / fO (REC) 〈PB EQ〉 1.1MHz gain GRE1 — 19.5 — dB VIN = 0.3VP-P, 1.0715MHz 1.0MHz suppression ratio GRE2 — – 8.0 — dB VIN = 0.3VP-P, 1.0MHz 1.2MHz suppression ratio GRE3 — – 11.0 — dB VIN = 0.3VP-P, 1.2MHz 〈REC EQ〉 1.1MHz gain GPE1 — – 19.5 — dB VIN = 0.3VP-P, 1.0715MHz 1.0MHz gain GPE2 — 8.0 — dB VIN = 0.3VP-P, 1.0MHz 1.2MHz gain GPE3 — 11.0 — dB VIN = 0.3VP-P, 1.2MHz Center frequency ratio dfOE – 101% dfOE = (fO (REC) – fO (PB) ) / fO (PB), •Measurement circuits

BA7207AS (SDIP32)

1N21N21N2SW30b SW21 SW19 OSC30 OSC181212SW30a SW18 VREG 0.01µ RECOUT Vcc I23 27p 0.1µ 0.1µ 0.1µ 47µ 0.1µ 0.01µ Vcc A Vcc 0.1µ + 47µ 0.01µ 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 CTL RECH BWL

MODE CONTOROL

Vreg PAL SCM LIMRP× 2 2.2MHz × 2 LIM EQ 1.1MHzBPF P BPF

R

4.3MHz PB BPF - B SYNC GATE ÷ 4

REC

P SYNC GATEP 4.3MHz R BPF - A BELLR R

R P

SYNC GATE TIMING DET VCO GENERATOR SCM PAL

FREQUENCY ADJUSTER

12345678910 11 12 13 14 15 16 SW2 SW3 SW4 100k SW15 0.01µ1212120.01µ 10k12100P 2k 2k 4700p 3.3k SW16 OSC1 VR1 VR23.9k 0.47µ + 1 2 8.5k 8.5k 33k PBOUT SGC 0.01VµV7.5k 7.5k SW8 SG16 AMPOUT SW14a Vcc 47012312Vcc OSC8 µ OSC14470 12 560p SW14b1N21.5V 2.5V

Fig. 1

,

BA7207AK (QFP44)

1N21N21N21N2REC OUT SW30b SW21 SW19 SW4b 1.5V 2.5V

VCC

0.1µ 0.1µ I23 0.01µ 0.1µ A 47µ + VCC 33 32 31 30 29 28 27 26 25 24 23 OSC30 0.1µ 27p ~ VCC1247µ SW30a 34 22 0.01µ LIM 35 MODECONTROL 21 PAL SCM VREG 36 VREG 20 0.01µ 0.1µ VCC 37 19 SW18

P

R 1 2P 38 × 2 2.2MHzBPF × 2 LIM EQ 1.1MHz 18 BPF ~ R OSC18PR39PR17 4.3MHz R PBELL 4.3MHz PB RECBPF—A BPF—B SYNC GATE ÷ 4 SYNC GATE 0.01µ 40 16R SW16

P

SYNC GATE 100p12OSC1 ~ 41 FREQUENCY DET VCO TIMING 15 ADJUSTER SG16GENERATOR 42 14 SW2 SCM PAL1243 13 0.01µ 3.9k 44 12 SW14a SW15 SW3 SW41212VCC1212~ OSC14 3.3k 2k 2k VR1 VR212345678910 11 VCC 8.5k 8.5k 0.01µ 100k 7.5k 7.5k 470 SW8 10k 33k123+ PB SG OUT 4700p 12µ OSC8 0.47µ 470 ~ 560p AMP OUT PB OUT SGC REC SG OUT

Fig. 2

, •Circuit operation (1) Recording system (REC) The input to REC IN is passed through the 4.3MHz BPF-A to remove unwanted frequency components, and is flat- tened by REC BELL which has an anti-bell characteristic. The flattened signal is wave-shaped by the limiter amplifer, and processed by the divide-by-four and sync gate circuits. Finally, unwanted frequency components are removed by the 1.1MHz BPF and the REC EQ prepares the signal for recording playback and the signal is output on REC OUT. Refer to Fig. 3. Composite video signal REC RECOUT 1 4.3MHz REC 1.1MHz RECBPF - A BELL 26 24 LIMAMP ÷ 4 SYNCGATE BPF EQ AMP 28 100pF ( 4 0 ) ( 3 1 ) ( 2 33 7 ) ( ) BA7207AS (BA7207AK) Fig. 3 (2) Playback system (PB) The input to PB IN is passed through the 1.1MHz BPF to remove unwanted frequency components, and is flattened by the PB EQ circuit. The amplitude of the flattened signal fixed by the 1st-stage limiter amplifier, and the frequency is multiplied by four by the multiplier circuit. Unwanted frequency components generated by the multiplier circuit are removed by the 2.2MHz BPF and 4.3MHz BPF-A. The signal is wave-shaped by the limiter amplifier, and has gate applied to it by the sync gate circuit then is passed through the 4.3MHz BPF-B to remove unwanted frequency com- ponents. The PB BELL circuit restores the original bell characteristic and the signal is output on PB OUT. Refer to Fig. 4. RF chroma signal LPF 18 1.1MHz PBAMP LIMAMP × 2 2.2MHz 4.3MHzBPF EQ BPF × 2 BPF - A fc62.2MHz ( 2 0 ) ( 3 1 ) PB PBOUT 24 LIMAMP SYNC 4.3MHz PB AMP68AMP 11 GATE BPF - B BELL ( 2 7 ) ( 2 ) ( 5 ) ( 1 0 ) TRAP BA7207AS (BA7207AK) Fig. 4 (3) Sync gate timing circuit REC and PB SYNC gate operation is as follows. The gate closes closes in synchronous with the SYNC IN input pulse during the synchronous signal pulse (SYNC) horizontal scan interval (64µs period). During vertical retrace (32µS period), the input pulse period becomes shorter than the horizontal scan interval. This is detected by the built- in vertical synchronous detector circuit which closes the gate. Refer to Fig. 5. Horizontal scan interval Vertical retrace interval 64µs 32µs 4µs

SYNCIN

REC / PBOUT Fig. 5, •Application examples

BA7207AS (SDIP32)

PAL REC C. REC C OUT

VCC

100 SCM / PAL 0.1 REC / PB 0.1µ 0.01 27p 0.01 0.1 ∆ LPF PBIN 0.01 + B / W ∆ 47 0.01 47 0.1 0.01 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17

MODE CONTOROL

Vreg PAL SCM LIMRP× 2 2.2MHz 1.1MHzBPF × 2 LIM EQP BPF

R

4.3MHz PB REC P BPF - B SYNC GATE ÷ 4 SYNC GATE

P

4.3MHz BPF - A BELL

R

R R

R P

DET VCO SYNC GATE TIMINGGENERATOR SCM PAL

FREQUENCY ADJUSTER

12345678910 11 12 13 14 15 16 VR1 VR2 VR3 100k 0.01 0.01 0.01 100p 100p ∆ ∗ ∗ 2KVR × 2 ∆ 10k 33k SYNC IN 7.5k 1k ∗ PALPB C∗ 7.5k ∗ 12 0.47 PB C OUTRECIN 560p ∗ T o cancel the temperature characteristic of the ID, the resistors marked with asterisks should be of the metal film, and have a temperature coefficient ± 100ppm / °C. ∆: Test pin. Connect to VCC if unused. The 100pF capacitor connected to pin 16 is intended to reduce temperature disper of the gate phase.It should have a static capacitance tolerance of ± 10% or Ic and a temperature coefficient of ± 30ppm / °C ( – 55°C to + 125°C) A (CG). Fig. 6 EQ fo ADJ BELL fo ADJ PBOUT LEVEL 4700p,

BA7207AK (QFP44)

PAL REC C. REC C OUT.

VCC

SCM/PAL 100µ REC/PB 0.01µ 0.01µ PBIN B/W 0.1µ 0.1µ + 0.01µ 0.01µ 47µ ∆ 33 32 31 30 29 28 27 26 25 24 23

VCC

34 22 LIM 0.1µ 47µ 35 MODECONTROL 21 PAL SCM 0.01µ 27p 36 Vreg 20 LPF 0.1µ 37 19 ∆ PR 38 × 2 2.2MHz

P

BPF × 2 LIM EQ 1.1MHz BPF 18RPR39PR17 100p 4.3MHzRPPB BPF—A BELL 4.3MHz REC BPF—B SYNC GATE ÷ 4 SYNC GATE 40 16

R P

SYNC GATE FREQUENCY 100p41 DET VCO TIMING 15 ADJUSTER GENERATOR ∆ ∆ 42 14 0.01µ SCM PAL 43 13 44 12 VR1 VR2 2k 2k VR ∗ VR ∗ 12345678910 11 ∗ ∗ VR3 0.01µ 100k7.5k 7.5k 10k 33k 0.01µ 1k 12µ + ∗ 4700p 0.47µ 580p SYNC IN PALPB C. PB C OUT

RECIN

∗ T o cancel the temperature characteristic of the ID, the resistors marked with asterisks should be of the metal film, and have a temperature coefficient ± 100ppm / °C. ∆: Test pin. Connect to VCC if unused. The 100pF capacitor connected to pin 16 is intended to reduce temperature disper of the gate phase.It should have a static capacitance tolerance of ± 10% or Ic and a temperature coefficient of ± 30ppm / °C ( – 55°C to + 125°C) A (CG). Fig. 7 •Control pin logic Pin Low High (Open) REC / PB setting switch RECH (19pin / 21pin) PB REC Output select switch CTL (21pin / 23pin) PAL SECAM Chroma killer switch BWL (17pin / 18pin) Chroma killer NORMAL (BA7207AS / BA7207AK) EQ of ADJ BELL of ADJ PBOUT LEVEL, •Operation notes (1) Equalizer fo adjustment (6) PBIN input Set to PB mode and input a 25mVP-P, 1.0715MHz sine If there is a chroma component imposed on the FM wave to PBIN. Adjust the variable resistor connected brightness signal, use a low-pass filter (with an fc of between FADJ1 and GND to maximize the REC OUT about 2.2MHz) to remove the FM brightness signal output. This adjustment also adjusts the 1.1MHz and component, and ensure that only the chroma compo- 2.2MHz band-pass filters. The value of the variable nent is input to PBIN. resistor must be at least 2kΩ. If it is less than this, adjustment may not be possible. (7) RECIN input In the case of composite video input, connect a 100pF (2) Bell filter fo adjustment capacitor to ensure that only the chroma component is Set to REC mode and input a 170mVP-P, 4.286MHz input to RECIN. sine wave to RECIN. Adjust the variable resistor con- nected between FADJ2 and GND to maximize the (8) Sync-gate phase adjustment AMP OUT output. This adjustment also adjusts the Perform fine adjustment of the sync-gate phase by 4.3MHz and 4.3MHz A and B band-pass filters. The applying a voltage to the SGADJ terminal, or using a value of the variable resistor must be at least 2kΩ. If it resistor divider connected between VCC and GND. The is less than this, adjustment may not be possible. adjustment sensitivity is shown in Fig. 6. SGADJ pin voltage when open: VSGADJ = 2.5V (3) Test pins Input impedance Z = 125kΩ The MUL, DIV, LAO and 4XO pins are test terminals. By connecting these pins to GND via a 3.6kΩ resistor, it is possible to monitor there waveforms. When unused, connect these pins to VCC to prevent interfer- + 3.2 ence. (4) REC / PB input levels 0 0.32µS / 0.1V The frequency characteristics of the built-in filters can change. For this reason use the following input signal levels: – 3.2 RECIN: 540mVP-P + / – 6dB (cyan level) PBIN: 75mVP-P + / – 6dB (cyan level) 1.5 2.5 3.5 SGADJ PIN APPLY VOLTAGE: VSGADJ (V) (5) Capacitor connected to VREG Use a ceramic with a static capacitance of 0.1µF. The Fig. 8 Sync-gate phase filter may not operate correctly with other capacitance values. GATE PHASE ADJUSTMENT: TDR (µS), •Electrical characteristic curves 1.3 5.5 4.40 Conditions VCC = 5.0V 4.35 fo = 4.286MHz 1.2 5.0 V = 170mVP-P 4.30 1.1 4.5 4.25 fo 1.0 4.0 4.20 0.9 4.15 7.5 8.0 8.5 9.0 9.5 3.5 7.5 8.0 8.5 9.0 9.5 0 100 200 300 400 500 FADJ1 RESISTANCE VALUE: RADJ1 (kΩ) FADJ2 RESISTANCE VALUE: RADJ2 (kΩ) 1PIN REC IN LEVEL: VIREC (mVP-P)

Fig. 9 REC / PB EQ fO Fig. 10 REC / PB BELL fO Fig. 11 REC / BELL fO

frequency adjustment frequency adjustment frequency variation range range 1.09 – 10 – 10 Conditions Fundamental frequency – 20 RECIN component PB INVCC = 5.0V f = 4.286MHz – 20 f = 1.0715MHz 1.08 fo = 1.0715MHz – 30 V = 170mVP-P – 30 V = 25mVP-P V = 25mVP-P 8MHz component – 40 – 40 1.07 6MHz component– 50 – 50 – 60 – 60 1MHz 3MHz fo component component 1.06 – 70 – 70 – 80 – 80 5MHz 7MHz component component 1.05 – 90 – 90 – 100 Fundamentalfrequency 2MHz 3MHz 4MHz – 100 component component component component 2MHz component 1.04 0 20 40 60 80 100 – 110 – 1100 1.0 2.0 3.0 4.0 5.0012345678910 18PIN PB IN LEVEL: VIPB (mVP-P) FREQUENCY: f (MHz) FREQUENCY: f (MHz)

Fig. 12 PB EQ fO frequency Fig. 13 REC OUT spurious Fig. 14 PB OUT spurious

variation characteristics characteristics characteristics 28PIN PB EQ FREQUENCY: fo (MHz) REC / PB EQ FREQUENCY: fo (MHz) REC OUT LEVEL: VOREC (dBm) REC / PB BELL FREQUENCY: fo (MHz) PB OUT LEVEL: VOPB (dBm) 6PIN REC BELL FREQUENCY: fo (MHz), •External dimensions (Units: mm) BA7207AS BA7207AK 28.0 ± 0.3 32 17 14.0 ± 0.3 10.0 ± 0.2 33 23 34 22 1 16 10.16 44 12 1 11 0.15 ± 0.1 0.3 ± 0.1 1.778 0.5 ± 0.1 0° ~ 15° 0.8 0.35 ± 0.1 0.15

SDIP32 QFP44

3.2 ± 0.2 4.7 ± 0.3 0.51Min. 8.4 ± 0.3 14.0 ± 0.3 2.15 ± 0.1 10.0 ± 0.2 0.05 1.2]

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