Download: Introduction to Single Chip National SemiconductorApplication Note 885 Microwave PLLs Cynthia L. Barker Wireless Communications March 1993

Introduction to Single Chip National SemiconductorApplication Note 885 Microwave PLLs Cynthia L. Barker Wireless Communications March 1993

ABSTRACT ceiver demodulators and modulators. This application note Synthesizer and Phase Locked Loop (PLL) figures of merit will concentrate on the use of a PLL as a frequency synthe- including phase noise, spurious output and lock time, at mi- sizer, as shown in Figure 1. crowave frequencies, are examined. Measurement methods There are two main reasons for using a PLL as a frequency for these parameters and supporting software are discussed synthesizer. One is to translate the frequency accuracy of a in detail. The requirements for the loop filler, the charge high quality signal source to a tunable signal source. The pump, the dual modulus prescaler and their effects on PLL second is to translate the noise characteristics of a high performance are analyzed. quality signal source to a lower quality signal source. The block diagram of a basic PLL is shown in Figure 1. The high

INTRODUCTION

quality signal source, in this case, is a crystal reference. Phase Locked Loops are used for many radio applications A single chip PLL consists of the reference divider, the main including frequency synthesizers, carrier recovery and clock divider (including a dual modulus prescaler), the phase de- recovery circuits, tunable filters, frequency multipliers, re- tector and a charge pump. TL/W/11815–1 FIGURE 1. Block Diagram of a Basic Phase Locked Loop SYNTHESIZER AND PLL FIGURES OF MERIT ence between the level of the carrier and the noise level Phase noise is a measure of the spectral purity of the tone minus 10 [log (resolution bandwidth)] is equal to the phase produced by the PLL. It is dependent on the noise charac- noise in dBc/Hz. The resolution bandwidth is read directly teristics of the crystal oscillator reference and the VCO as from the spectrum analyzer. The phase noise result in well as some noise contribution of the dividers. Phase noise dBc/Hz is a negative number. Since phase noise is mea- is defined as the ratio of the single sideband power (within a sured in dBc/Hz the measurement is always normalized toa1Hz bandwidth at some offset frequency) to the total carrier 1 Hz bandwidth. The video averaging feature of the analyzer power. Phase noise is often measured in units of dBc/Hz. is used to better determine the noise level. An example of such a measurement, for the LMX1501A PLL using a refer- Spurious output is a measure of the level of the reference ence frequency of 25 kHz, is shown inFigure 2. Refer to the spurs (sometimes referred to as reference sidebands) on LMX1501A data sheet for application circuits. the output tone. The reference spurs appear on the output tone at the center frequency g the reference frequency and at integer multiples of the reference frequency. For exam- ple, a PLL operating at 836 MHz with a reference frequency of 25 kHz will have reference spurs at 836.025 MHz, 835.075 MHz, 836.050 MHz, 835.050 MHz, etc. Lock time or switching speed is a measure of the settling time of the PLL once a change in frequency has been initiat- ed. The frequency step and the frequency accuracy to de- fine ‘‘locked’’ must both be defined for this measurement to be useful. PHASE NOISE MEASUREMENT METHODS The phase noise characteristics of the PLL can be mea- sured on a spectrum analyzer or using a phase noise test set. The spectrum analyzer test technique is described here. Phase noise is measured in units of dBc/Hz. This is done at several offsets from the output signal such as 1 kHz, 10 kHz and 100 kHz. The spectrum analyzer is tuned to the desired center frequency and the span is adjusted so TL/W/11815–2 the appropriate offset frequency can be viewed. The differ- FIGURE 2. An 826 MHz Synthesizer Phase Noise Measurement @ 100 kHz e b116 dBc/Hz. Using the LMX1501A PLL. C1995 National Semiconductor Corporation TL/W/11815 RRD-B30M75/Printed in U. S. A.

Introduction to Single Chip Microwave PLLs AN-885

, Example Phase Noise Calculation directly. This method shows the damping characteristics of phase noise the loop but does not provide the accuracy of the frequency @ match.( 100 kHz) e b76 dBc b10 # log(res.BW) # Figure 4 illustrates an evaluation method using a mixer toe b76 dBc b 10 log (10 kHz) determine the accuracy of the frequency match. The signal e (b76 b 10 # 4) dBc/Hz generator is phase locked to the crystal reference input to e b116 dBc/Hz the PLL. This is accomplished by using a signal generator for the crystal reference and having the 10 MHz reference REFERENCE SIDEBAND MEASUREMENT METHODS used as an external reference for the other signal generator. The reference sidebands can be seen on a spectrum ana- The output of the VCO is mixed with a signal (from a signal lyzer and are measured in dBc. The analyzer is set to the generator) at the desired frequency (using the mixer as a desired center frequency and the span is set to allow the phase detector). When the frequencies are matched a DC reference sidebands to be viewed. For example, to see the voltage appears at the output of the mixer. When the fre- reference spurs for a 1.7 MHz reference frequency the span quencies are mismatched a beat note appears at the output would be set to 10 MHz. The spurious output is the differ- of the mixer. Either of these signals is viewed on a scope. ence between the level of the PLL tone (at the center fre- The peak to peak amplitude of the beat note represents a quency) and the level of the reference spur (at the center phase offset of g180§. The slope of the beat note repre- frequency g the reference frequency). In Figure 3, the ref- sents a change in phase divided by time, which is equivalent erence sidebands for a 1.7 MHz reference frequency are to frequency. This frequency represents the frequency mis- about 78 dB down from the PLL tone, or b78 dBc. Refer to match. As the slope of the line approaches zero the fre- the LMX2320 data sheet for application circuits. quencies converge, and the loop locks. This method gives a frequency accuracy within 100 Hz. An example of the above two types of switching speed mea- surements is shown in Figure 4. Channel 1 shows the VCO tuning voltage and channel 2 shows the output of the mixer IF port. A third method uses a spectrum anaIyzer to view the tran- sient response by setting the frequency span to 0 Hz. The display is effectively now frequency versus time. The video band width should be set on maximum. The frequency off- set will be equal to the resolution bandwidth setting at 10 dB down from the top on the vertical axis. This is due to the filter characteristics of the analyzer. To be fully accurate the external trigger of the analyzer should be triggered off the loading of the new frequency. This method is not recom- mended for measuring lock times under 10 milliseconds be- cause on some spectrum analyzers the display response time of the analyzer is longer than a few milliseconds and TL/W/11815–3 erroneous data can result. A modulation domain analyzer FIGURE 3. An 1881 MHz Synthesizer with a can also be used to measure switching speed. It displays Reference Frequency of 1.7 MHz and Sidebands frequency versus time directly but it is not available in all @ 1.7 MHz e b78 dBc. Using the LMX2320 PLL. labs. SWITCHING SPEED MEASUREMENT METHODS Switching speed is measured on an oscilloscope by probing the VCO tuning voltage. The transient response will be seen Trigger on the rising edge of Load Enable. TL/W/11815–4 TL/W/11815–5 FIGURE 4. Test Setup and Lock Time for 10 MHz Step e 1.77 ms using a LMX1501A with a Reference Frequency of 25 kHz., SUPPORTING SOFTWARE (in North or South America) A software program of some kind is needed in order to pro- Wireless Communications Applications gram the PLL chip to test it. National Semiconductors LMX National Semiconductor Corp. series of PLL chips are programmed via a three line 1090 Kifer Rd. MlCROWIRETM serial interface (clock, data, load enable). Santa Clara, CA National Semiconductor Corporation provides a DOS pro- (408) 721-4748 gram to allow the user to program the chip from the parallel LOOP FILTER port of a DOS personal computer. The user enters the fre- quency of operation, the reference frequency and the crys- The design of the loop filter involves a trade off between tal frequency then presses one key to load in the appropri- reference sidebands and switching speed. The loop filter ate divider values. The frequency can be tuned in steps of must be designed for the correct balance between refer- the reference frequency and a switching mode is available ence spurs and lock time that the system requires. General- to test the lock time. The user enters the number of steps ly, the narrower the loop bandwidth the lower the reference and the PLL will switch between the two frequencies. The spurs but the longer the lock time. The circuit in Figure 5 user interface for the program is function key driven. De- shows a type 2 third order passive loop filter configuration tailed operating instructions are provided with the software. and its transfer function. For more information on the PLL software program contact: (in Asia Pacific region) Wireless Communications Product Applications National Semiconductor Hong Kong Ltd. Ocean Center 15/F, Straight Block 5 Canton Road Tsimshatsui, Kowloon, Hong Kong 852-737-1800 TL/W/11815–6 (in Europe) R # C2 # sa1GLF(s) e Wireless Communications Field Applications s (C2 a C1 (R # C2 # s a 1)) National Semiconductor European Headquarters FIGURE 5. Passive Loop Filter Circuit Industriestrasse 10 and Loop Filter Transfer Function. D-8080 Furstenteldbruck A type 2 loop has two integrators within the loop, a VCO and Germany an integrator/filter. The order of the loop is determined by 49-8141-103-557 number of poles of the transfer function. Using the phase (in Japan) detector and VCO constants (Kw and KV) and the loop filter Innovative Product Application Engineering transfer function (GLF) the open loop Bode plot can be cal- Communication Business Center culated. Kw and KV are available from the PLL IC and VCO National Semiconductor Japan Ltd. manufacturers. The control circuit, the open loop transfer Sansei-doh Shinjuku Bldg. 5F function and the open loop Bode plot are shown inFigure 6. 4-15-3 Nishi Shinjuku The loop bandwidth is shown on the Bode plot as (0p) the Shinjuku-ku, Tokyo, Japan point of unity gain. 81-3-3299-7001 Control Circuit TL/W/11815–8 Open Loop Response Bode Plot (G e Forward transfer function, H e Feed back) Open Loop Transfer Equation Kw GLF(s) KV GH(s) e Ns TL/W/11815–9 FIGURE 6. Control Circuit, Open Loop Equation and Bode Plot, CHARGE PUMP AND PHASE DETECTOR tinguish them. This is the deadband or dead zone, as shown A current charge pump and a phase frequency detector are in Figure 9. The LMX series of PLLs use a proprietary feed- implemented in National Semiconductor’s LMX series of back method to minimize deadband. PLL chips. To increase the VCO frequency the charge pump outputs a pump up (source) current. To decrease the VCO Charge Pump Current vs Do Voltage frequency the charge pump outputs a pump down (sink) cur- rent. This current pulse charges the voltage of the capacitor C1. The charge pump is capable of supplying a controlled charge to the loop filter over a wide range of voltages, as shown in Figure 7. The phase detector and charge pump are difficult to charac- terize separately. The figures of merit for the combination include linearity, sensitivity and deadband range. The linear- ity of the charge produced by the charge pump with respect to the detected phase error is critical to providing low spuri- ous and low phase noise. The sensitivity (Kw) is measured in mA/radian and depends on the charge pump current ca- pability. Current mode charge pumps commonly have a dead zone where the gain changes dramatically for a very small phase error. The divider outputs fr and fp are a series TL/W/11815–7 of pulses whose relative timing reflect the phase or frequen- FIGURE 7. Charge Pump Current vs Voltage for the LMX cy error, as shown in Figure 8. At some point the pulses are Series of PLL Chips too close together for the phase frequency detector to dis- TL/W/11815–11 FIGURE 8. Phase/Frequency Error Pulses, Phase Detector/Charge Pump Linearity 1881.792MHz to 1897.344 MHz with a channel spacing of 1.728 MHz. The reference frequency used is 1.728 MHz. 1881.792 1897.344 e 1089 and e 1098 1.728 1.728 The minimum continuous divide ratio for a 64/65 prescaler is 64(64b1) or 4032. The minimum continuous divide ratio for a 128/129 prescaler is 128(128b1) or 16,256. For DECT the divide ratios required do not exceed the minimum continuous divide ratio for a 64/65 or 128/129 prescaler. Therefore, it must be verified that the condition ofBtAholds true. This is determined as follows: TABLE I. Example Dual Modulus Prescaler Calculation 64/65 128/129

N

BABA1089 171865 TL/W/11815–10 1090 172866 FIGURE 9. Charge Pump Current vs. Phase Error, showing Deadband. - - - - - DUAL MODULUS PRESCALER - - - - - Dual modulus prescalers allow operation of the divider chain - - - - - at high frequencies while most of the divider operates at a 1097 179873 lower frequency. However, this capability sets limits on the range of the divider. The divider is made up of an A counter 1098 17 10 8 74 andaBcounter. The A counter is the swallow counter and the B counter is the programmable divider. The condition for For the 64/65 prescaler, Table 1 showsBtAtherefore it a legal divide ratio is thatBtA. can be used. The 128/129 prescaler cannot be used since l The necessary divide number (N) is calculated by dividing A B. The above calculation demonstrates that a 64/65 the desired frequency by the reference frequency. prescaler can be used in the DECT system for the transmit PLL.

N

fout e Nfref e fcrystal R CONCLUSION crystal frequency The performance of a PLL as a frequency synthesizer isRereference divide ratio e measured in terms of phase noise, spurious output and lock fref time. The techniques for measuring these parameters have The output frequency must be an integer multiple of the been discussed. The loop filter, charge pump/phase detec- reference frequency. Once the divide ratio is calculated a tor and dual modulus prescaler and their impact on PLL check can be made to determine whether it is above the performance have been analyzed. Example performance minimum continuous divide ratio. The minimum continuous metrics were demonstrated for National Semiconductor’s divide ratio is equal to P(Pb1) where P is the prescaler LMX series of PLL chips. These ICs provide the capability to divider. For example the minimum divide ratio for a 64/65 produce a low power, low noise, low spurious and fast prescaler is 64(64b1) or 4032. If the divide ratio required switching frequency synthesizer. With a properly designed (N) is below the minimum continuous divide ratio it may be a loop filter excellent performance can be achieved. The LMX legal number but it must be verified thatBtA. The values series of PLL chips provide the building block around which for A and B can be calculated from the following equations: a high performance frequency synthesizer can be designed. BeNdiv P ReferencesAeNmod P W.F. Egan: Frequency Synthesizers By Phase Lock, John A divide ratio that is above the minimum continuous divide Wiley and Sons, 1981 ratio or satisfies the conditionBtAis a legal divide num- F.M. Gardner: Phaselock Techniques, Wiley, 1989 ber. The PLL will not operate if it is programmed with an illegal divide number. For example, in choosing a prescaler F.M. Gardner: ‘‘Charge-Pump Phase-Lock Loops’’, IEEE for a DECT (Digital European Cordless Telephony) system Transactions on Communications, Com-28, No. 11, Novem- the required divide ratios for the transmit side would be ber 1980 1089 to 1098. The frequencies of operation for DECT are U.L. Rohde: Digital PLL Frequency Synthesizers: Theory and Design, Prentice Hall, 1983,

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AN-885 Introduction to Single Chip Microwave PLLs

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