Download: STA013 MPEG 2.5 LAYER III AUDIO DECODER

STA013

® STA013B STA013T

MPEG 2.5 LAYER III AUDIO DECODER

SINGLE CHIP MPEG2 LAYER 3 DECODER SUPPORTING: - All features specified for Layer III in ISO/IEC 11172-3 (MPEG 1 Audio) - All features specified for Layer III in ISO/IEC 13818-3.2 (MPEG 2 Audio) SO28 - Lower sampling frequencies syntax extension, (not specified by ISO) called MPEG 2.5 DECODES LAYER III STEREO CHANNELS, DUAL CHANNEL, SINGLE CHANNEL (MONO) SUPPORTING ALL THE MPEG 1 & 2 SAM- PLING FREQUENCIES AND THE EXTEN- TQFP44 SION TO MPEG 2.5: 48, 44.1, 32, 24, 22.05, 16, 12, 11. 025, 8 KHz ACCEPTS MPEG 2.5 LAYER III ELEMEN- TARY COMPRESSED BITSTREAM WITH DATA RATE FROM 8 Kbit/s UP TO 320 Kbit/s DIGITAL VOLUME CONTROL DIGITAL BASS & TREBLE CONTROL SERIAL BITSTREAM INPUT INTERFACE LFBGA64 ANCILLARY DATA EXTRACTION VIA I2C IN- TERFACE. ORDERING NUMBERS: STA013$ (SO28) SERIAL PCM OUTPUT INTERFACE (I2S STA013T$ (TQFP44) AND OTHER FORMATS) STA013B$ (LFBGA 8x8) PLL FOR INTERNAL CLOCK AND FOR OUT- PUT PCM CLOCK GENERATION LOW POWER CONSUMPTION: 85mW AT 2.4V DESCRIPTION CRC CHECK AND SYNCHRONISATION ER- The STA013 is a fully integrated high flexibility ROR DETECTION WITH SOFTWARE INDI- MPEG Layer III Audio Decoder, capable of de- CATORS coding Layer III compressed elementary streams, I2C CONTROL BUS as specified in MPEG 1 and MPEG 2 ISO stand- LOW POWER 3.3V CMOS TECHNOLOGY ards. The device decodes also elementary streams 10 MHz, 14.31818 MHz, OR 14.7456 MHz compressed by using low sampling rates, as speci- EXTERNAL INPUT CLOCK OR BUILT-IN IN- fied by MPEG 2.5. DUSTRY STANDARD XTAL OSCILLATOR STA013 receives the input data through a Serial DIFFERENT FREQUENCIES MAY BE SUP- Input Interface. The decoded signal is a stereo, PORTED UPON REQUEST TO STM mono, or dual channel digital output that can besent directly to a D/A converter, by the PCM Out- put Interface. This interface is software program- APPLICATIONS mable to adapt the STA013 digital output to the most common DACs architectures used on the PC SOUND CARDS market. MULTIMEDIA PLAYERS The functional STA013 chip partitioning is de- scribed in Fig.1. February 2004 1/38,

Figure 1. Block Diagram: MPEG 2.5 Layer III Decoder Hardware Partitioning.

RESET SDA SCL 2634I2C CONTROL59SDI CHANNEL SDO MPEG 2.5 6 SERIAL CONFIG.LAYER III PCM 10 SCKR BUFFER PARSER & OUTPUTINPUT DECODER BUFFER OUTPUT

SCKT

7 INTERFACE

VOLUME

CORE INTERFACE 11 BIT_EN CONTROL LRCKT SYSTEM & AUDIO CLOCKS TEST INTERFACE 8 28 21 20 12 24 25 SRC_INT OUT_CLK/DATA_REQ XTI XTO OCLK TESTEN SCANEN D98AU965

THERMAL DATA

Symbol Parameter Value Unit Rth j-amb Thermal resistance Junction to Ambient 85 °C/W

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit VDD Power Supply -0.3 to4VVi Voltage on Input pins -0.3 to VDD +0.3 V VO Voltage on output pins -0.3 to VDD +0.3 V Tstg Storage Temperature -40 to +150 °C Toper Operative ambient temp -40 to +85 (*) °C Tj Operating Junction Temperature -40 to 125 °C (*) guaranteed by design. 2/38,

Figure 2. Pin Connection

VDD_1 1 28 OUT_CLK/DATA_REQ VSS_1 2 27 VSS_5 SDA 3 26 RESET SCL 4 25 SCANEN SDI 5 24 TESTEN SCKR 6 23 VDD_4 BIT_EN 7 SO28 22 VSS_4 SRC_INT 8 21 XTI SDO 9 20 XTO SCKT 10 19 FILT LRCKT 11 18 PVSS OCLK 12 17 PVDD VSS_2 13 16 VDD_3 VDD_2 14 15 VSS_3 D98AU911A 44 43 42 41 40 39 38 37 36 35 34 N.C. 1 33 N.C. LRCKT 2 32 SCL OCLK 3 31 SDA N.C. 4 30 VSS_1 VSS_2 5 29 VDD_1 VDD_2 6 TQFP44 28 N.C. VSS_3 7 27 OUT_CLK/DATA_REC VDD_3 8 26 VSS_5 N.C. 9 25 RESET PVDD 10 24 SCANEN PVSS 11 23 N.C. 12 13 14 15 16 17 18 19 20 21 22 D99AU101987654321

A1 = SDI G7 = FILT A B2 = SCKR G8 = XTO D4 = BIT_EN F7 = XTI B D1 = SRC_INT E7 = VSS4 C E2 = SDO C8 = VDD4 F2 = SCKT D7 = TESTEN D H1 = LRCKT A7 = SCANEN E H3 = OCLK B6 = RESET F3 = VSS_2 A5 = VSS5 F E4 = VDD_2 C5 = OUT_CLK/DATA_REQ G G4 = VSS_3 B5 = VDD1 G5 = VDD_3 B4 = VSS1 H F5 = PVDD A4 = SDA G6 = PVSS B3 = SCL

D99AU1085

LFBGA64

3/38 FILT SCKT XTO N.C. N.C. SDO XTI N.C. N.C. SRC_INT N.C. N.C. N.C. BIT_EN VSS_4 N.C. N.C. SCKR VDD_4 N.C. TESTEN SDI,

PIN DESCRIPTION

SO28 TQFP44 LFBGA64 Pin Name Type Function PAD Description 1 29 B5 VDD_1 Supply Voltage 2 30 B4 VSS_1 Ground 3 31 A4 SDA I/O i2C Serial Data + Acknowledge CMOS Input Pad Buffer CMOS 4mA Output Drive 4 32 B3 SCL I I2C Serial Clock CMOS Input Pad Buffer 5 34 A1 SDI I Receiver Serial Data CMOS Input Pad Buffer 6 36 B2 SCKR I Receiver Serial Clock CMOS Input Pad Buffer 7 38 D4 BIT_EN I Bit Enable CMOS Input Pad Buffer with pull up 8 40 D1 SRC_INT I Interrupt Line For S.R. Control CMOS Input Pad Buffer 9 42 E2 SDO O Transmitter Serial Data (PCM CMOS 4mA Output Drive Data) 10 44 F2 SCKT O Transmitter Serial Clock CMOS 4mA Output Drive 11 2 H1 LRCKT O Transmitter Left/Right Clock CMOS 4mA Output Drive 12 3 H3 OCLK I/O Oversampling Clock for DAC CMOS Input Pad Buffer CMOS 4mA Output Drive 13 5 F3 VSS_2 Ground 14 6 E4 VDD_2 Supply Voltage 15 7 G4 VSS_3 Ground 16 8 G5 VDD_3 Supply Voltage 17 10 F5 PVDD PLL Power 18 11 G6 PVSS PLL Ground 19 12 G7 FILT O PLL Filter Ext. Capacitor Conn. 20 13 G8 XTO O Crystal Output CMOS 4mA Output Drive 21 15 F7 XTI I Crystal Input (Clock Input) Specific Level Input Pad (see paragraph 2.1) 22 19 E7 VSS_4 Ground 23 21 C8 VDD_4 Supply Voltage 24 22 D7 TESTEN I Test Enable CMOS Input Pad Buffer with pull up 25 24 A7 SCANEN I Scan Enable CMOS Input Pad Buffer 26 25 B6 RESET I System Reset CMOS Input Pad Buffer with pull up 27 26 A5 VSS_5 Ground 28 27 C5 OUT_CLK/ O Buffered Output Clock/ CMOS 4mA Output Drive DATA_REQ Data Request Signal Note: SRC_INT signal is used by STA013 internal software in Broadcast Mode only; in Multimedia mode SRC_INT must be connected to VDD In functional mode TESTEN must be connected to VDD, SCANEN to ground. 4/38, 1. ELECTRICAL CHARACTERISTICS: VDD = 2.7V ±0.3V; Tamb = 0 to 70°C; Rg = 50Ω unless otherwise specified

DC OPERATING CONDITIONS

Symbol Parameter Value VDD Power Supply Voltage 2.4 to 3.6V

GENERAL INTERFACE ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Note IIL Low Level Input Current Vi = 0V -10 10 µA 1 Without pull-up device IIH High Level Input Current Vi = VDD = 3.6V -10 10 µA 1 Without pull-up device Vesd Electrostatic Protection Leakage < 1µA 2000V2Note 1: The leakage currents are generally very small, < 1nA. The value given here is a maximum that can occur after an electrostatic stress on the pin. Note 2: Human Body Model.

DC ELECTRICAL CHARACTERISTICS

Symbol Parameter Test Condition Min. Typ. Max. Unit Note VIL Low Level Input Voltage 0.2*VDD V VIH High Level Input Voltage 0.8*VDD V Vol Low Level Output Voltage Iol = Xma 0.4V V 1, 2 Voh High Level Output Voltage 0.85*VDD V 1, 2 Note 1: Takes into account 200mV voltage drop in both supply lines. Note 2: X is the source/sink current under worst case conditions and is reflected in the name of the I/O cell according to the drive capability. Symbol Parameter Test Condition Min. Typ. Max. Unit Note Ipu Pull-up current Vi = 0V; pin numbers 7, 24 -25 -66 -125 µA1REquivalent Pull-up and 26; V = 3Vpu DD 50 kΩ Resistance Note 1: Min. condition: VDD = 2.4V, 125°C Min process Max. condition: VDD = 3.6V, -20°C Max.

POWER DISSIPATION

Symbol Parameter Test Condition Min. Typ. Max. Unit Note PD Power Dissipation Sampling_freq ≤24 kHz 76 mW @ VDD = 3V Sampling_freq ≤32 kHz 79 mW Sampling_freq ≤48 kHz 85 mW 5/38,

Figure 3. Test Circuit

OUT_CLK/DATA_REQ 28 SDA VDD 1 SCL 100nF SDO 2 SCKT VSS 10

LRCKT

VDD 14 11

OCLK

100nF 12

SDI

13 5 VSS SCKR VDD 16 BIT_EN 100nF SCR_INT 15 8

VSS XTI

VDD 23 21

XTO

100nF 20 10K 22 19

VSS

17 18 27 26 25 24 VDD PVDD 100nF RESET SCANEN TESTEN 1K 4.7µF 4.7µF 470pF 4.7nF PVDD PVSS D98AU966 VSS PVSS PVSS

Figure 4. Test Load Circuit Test Load VDD

I Output IOL IOH CL VREFOL SDA 1mA 100pF 3.6V Other Outputs 100µA 100µA 100pF 1.5V OUTPUT VREF CL IOH D98AU967 2. FUNCTIONAL DESCRIPTION 2.1 - Clock Signal

The STA013 input clock is derivated from an ex- Other frequencies may be supported upon re-

ternal source or from a industry standard crystal quest to STMicroelectronics. Each frequency is oscillator, generating input frequencies of 10, supported by downloading a specific configura- 14.31818 or 14.7456 MHz. tion file, provided by STM

XTI is an input Pad with specific levels.

Symbol Parameter Test Condition Min. Typ. Max. Unit VIL Low Level Input Voltage VDD-1.8 V VIH High Level Input Voltage VDD-0.8 V

CMOS compatibility The XTI pad low and high levels are CMOS compatible; XTI pad noise margin is better than typical CMOS pads. TTL compatibility The XTI pad low level is compatible with TTL while the high level is not compatible (for example if VDD =

3V TTL min high level = 2.0V while XTI min high level = 2.2V) 6/38, Figure 5. MPEG Decoder Interfaces. µP XTI XTO FILT IIC SCL SDA DATA_REQ PLL IIC SDI SDO

MPEG

DATA SCKR SCKT SOURCE DECODER DAC BIT_EN LRCKT SERIAL AUDIO INTERFACE RX TX

OCLK

D98AU912 Figure 6. Serial Input Interface Clocks SDI DATA IGNORED SCKR SCLK_POL=0 SCKR SCLK_POL=4 BIT_EN DATA VALID DATA IGNORED D98AU968A 2.2 - Serial Input Interface 2.3 - PLL & Clock Generator System STA013 receives the input data (MSB first) When STA013 receives the input clock, as de- thought the Serial Input Interface (Fig.5). It is a scribed in Section 2.1, and a valid layer III input serial communication interface connected to the bit stream, the internal PLL locks, providing to the SDI (Serial Data Input) and SCKR (Receiver Se- DSP Core the master clock (DCLK), and to the rial Clock). Audio Output Interface the nominal frequencies of The interface can be configured to receive data the incoming compressed bit stream. The STA013 sampled on both rising and falling edge of the PLL block diagram is described in Figure 7. SCKR clock. The audio sample rates are obtained dividing the The BIT_EN pin, when set to low, forces the bit- oversampling clock (OCLK) by software program- stream input interface to ignore the incoming mable factors. The operation is done by STA013 data. For proper operation Bit-EN line shold be embedded software and it is transparent to the toggled only when SCR is stable low (for both user. SCLK_POL configuration) The possible configu- The STA013 PLL can drive directly most of the rations are described in Fig. 6. commercial DACs families, providing an over sampling clock, OCLK, obtained dividing the VCO frequency with a software programmable dividers. 7/38,

Figure 7. PLL and Clocks Generation System

XTI N PFD CP

R

CCMVCO Disable PLL Switching OCLK

FRAC

Circuit X XTI2OCLK Update FRAC DCLK

S

XTI2DSPCLK 2.4 - PCM Output Interface 16 to 24 bits/word, by setting the output precision with PCMCONF (16, 18, 20 and 24 bits mode)

The decoded audio data are output in serial PCM register. Data can be output either with the most

format. The interface consists of the following sig- significant bit first (MS) or least significant bit first nals: (LS), selected by writing into a flag of the

SDO PCM Serial Data Output PCMCONF register. SCKT PCM Serial Clock Output Figure 8 gives a description of the several STA013 PCM Output Formats. LRCLK Left/Right Channel Selection Clock The sample rates set decoded by STA013 is de- The output samples precision is selectable from scribed in Table 1. Figure 8. PCM Output Formats

16 SCLK Cycles 16 SCLK Cycles 16 SCLK Cycles LRCKT 16 SCLK Cycles 16 SCLK CyclesMLMLMLMLPCM_ORD = 0 SDOSSSSSSSSPCM_PREC is 16 bit modeLMLMLMLMPCM_ORD = 1 SDOSSSSSSSSPCM_PREC is 16 bit mode 32 SCLK Cycles 32 SCLK Cycles 32 SCLK Cycles LRCKT 32 SCLK Cycles 32 SCLK CyclesMLMLMLMLPCM_FORMAT = 1 SDO 0 0SSSS0SSS0S PCM_DIFF = 10ML0ML0MLSDOSSSS0MLPCM_FORMAT = 0SSSSPCM_DIFF = 00ML00ML0M0LMLPCM_FORMAT = 0SDO 0SSSSSS0SS0PCM_DIFF = 1MLMLMLMLPCM_FORMAT = 1 SDO MSB MSB MSBS S MSBSSSSSSPCM_DIFF = 1

Table 1: MPEG Sampling Rates (KHz)

MPEG 1 MPEG 2 MPEG 2.5 48 24 12 44.1 22.05 11.025 32 16 8 8/38, 2.5 - STA013 Operation Mode the configuration register of the device. The DAC connected to STA013 can be initialised during The STA013 can work in two different modes, this mode (set MUTE to 1). called Multimedia Mode and Broadcast Mode. In Multimedia Mode, STA013 decodes the in- PLAY MUTE Clock State PCM Output coming bitstream, acting as a master of the data communication from the source to itself. X 0 Not Running 0 This control is done by a specific buffer manage- X 1 Running 0 ment, controlled by STA013 embedded software. The data source, by monitoring the DATA_REQ Init Mode line, send to STA013 the input data, when the "PLAY" and "MUTE" changes are ignored in this signal is high (default configuration). mode. The internal state of the decoder will be The communication is stopped when the updated only when the decoder changes from the DATA_REQ line is low. state "init" to the state "decode". The "init" phase In this mode the fractional part of the PLL is dis- ends when the first decoded samples are at the abled and the audio clocks are generated at output stage of the device. nominal rates. Fig. 9 describes the default DATA_REQ signal behaviour. Programming STA013 it is possible to invert the Decode Mode polarity of the DATA_REQ line (register This mode is completely described by the follow- REQ_POL). ing table: Figure 9. PLAY MUTE Clock State PCMOutput Decoding00Not Running 0 No01Running 0 No SOURCE STOPS TRANSMITTING DATA SOURCE STOPS TRANSMITTING DATA10Running Decoded Yes DATA_REQ Samples SOURCE SEND DATA TO STA013 D98AU91311Running 0 Yes 3 - I2C BUS SPECIFICATION In Broadcast Mode, STA013 works receivinga2bitstream with the input speed regulated by the The STA013 supports theICprotocol. This pro- source. In this configuration the source has to tocol defines any device that sends data on to the guarantee that the bitrate is equivalent to the bus as a transmitter and any device that reads nominal bitrate of the decoded stream. the data as a receiver. The device that controls the data transfer is known as the master and the To compensate the difference between the nomi- others as the slave. The master always starts the nal and the real sampling rates, the STA013 em- transfer and provides the serial clock for synchro- bedded software controls the fractional PLL op- nisation. The STA013 is always a slave device in eration. Portable or Mobile applications need all its communications. normally to operate in Broadcast Mode. In both modes the MPEG Synchronisation is automatic and transparent to the user. To operate in Multi- 3. 1 - COMMUNICATION PROTOCOL media mode, the STA013, pin nr. 8, SCR-INT must be connected to VDD on the application 3.1.0 - Data transition or change board. Data changes on the SDA line must only occur when the SCL clock is low. SDA transition while 2.6 - STA013 Decoding States the clock is high are used to identify START or STOP condition. There are three different decoder states: Idle, Init, and Decode. Commands to change the de- coding states are described in the STA013 I2C 3.1.1 - Start condition registers description. START is identified by a high to low transition of the data bus SDA signal while the clock signal Idle Mode SCL is stable in the high state. In this mode the decoder is waiting for the RUN A START condition must precede any command command. This mode should be used to initialise for data transfer. 9/38, 3.1.2 - Stop condition The 7 most significant bits are the device address STOP is identified by low to high transition of the identifier, corresponding to the I 2C bus definition. data bus SDA signal while the clock signal SCL is For the STA013 these are fixed as 1000011. stable in the high state. A STOP condition termi- The 8th bit (LSB) is the read or write operation nates communications between STA013 and the RW, this bit is set to 1 in read mode and 0 for bus master. write mode. After a START condition the STA013 identifies on the bus the device address and, if a match is found, it acknowledges the identification 3.1.3 - Acknowledge bit on SDA bus during the 9th bit time. The following An acknowledge bit is used to indicate a success- byte after the device identification byte is the in- ful data transfer. The bus transmitter, either mas- ternal space address. ter or slave, releases the SDA bus after sending 8 bit of data. 3.3 - WRITE OPERATION (see fig. 10) During the 9th clock pulse the receiver pulls the SDA bus low to acknowledge the receipt of 8 bits Following a START condition the master sends a of data. device select code with the RW bit set to 0. The STA013 acknowledges this and waits for the byte of internal address. 3.1.4 - Data input After receiving the internal bytes address the During the data input the STA013 samples the STA013 again responds with an acknowledge. SDA signal on the rising edge of the clock SCL. For correct device operation the SDA signal has to be stable during the rising edge of the clock 3.3.1 - Byte write and the data can change only when the SCL line In the byte write mode the master sends one data is low. byte, this is acknowledged by STA013. The mas- ter then terminates the transfer by generating a 3.2 - DEVICE ADDRESSING STOP condition. To start communication between the master and the STA013, the master must initiate with a start 3.3.2 - Multibyte write condition. Following this, the master sends onto The multibyte write mode can start from any inter- the SDA line 8 bits (MSB first) corresponding to nal address. The transfer is terminated by the the device select address and read or write master generating a STOP condition. mode. Figure 10. Write Mode Sequence ACK ACK ACK BYTE DEV-ADDR SUB-ADDR DATA IN

WRITE

START RW STOP ACK ACK ACK ACK MULTIBYTE DEV-ADDR SUB-ADDR DATA IN DATA IN

WRITE

START RW D98AU825B STOP Figure 11. Read Mode Sequence ACK NO ACK

CURRENT

ADDRESS DEV-ADDR DATA

READ

START RW STOP ACK ACK ACK NO ACK

RANDOM

ADDRESS DEV-ADDR SUB-ADDR DEV-ADDR DATA

READ

START RW START RW STOP RW= ACK ACK ACK NO ACK

HIGH SEQUENTIAL

CURRENT DEV-ADDR DATA DATA DATA

READ

START STOP ACK ACK ACK ACK ACK NO ACK

SEQUENTIAL

RANDOM DEV-ADDR SUB-ADDR DEV-ADDR DATA DATA DATA

READ

START RW START RW D98AU826A STOP 10/38, 3.4 - READ OPERATION (see Fig. 11) terminates the transfer with a STOP condition. The output data stream is from consecutive byte 3.4.1 - Current byte address read addresses, with the internal byte address counter automatically incremented after one byte output. The STA013 has an internal byte address counter. Each time a byte is written or read, this counter is incremented. 4 - I2C REGISTERS For the current byte address read mode, follow- The following table gives a description of the ing a START condition the master sends the de- MPEG Source Decoder (STA013) register list. vice address with the RW bit set to 1. The first column (HEX_COD) is the hexadecimal The STA013 acknowledges this and outputs the code for the sub-address. byte addressed by the internal byte address The second column (DEC_COD) is the decimal counter. The master does not acknowledge the code. received byte, but terminates the transfer with a The third column (DESCRIPTION) is the descrip- STOP condition. tion of the information contained in the register. The fourth column (RESET) inidicate the reset 3.4.2 - Sequential address read value if any. When no reset value is specifyed, the default is "undefined". This mode can be initiated with either a current address read or a random address read. How- The fifth column (R/W) is the flag to distinguish ever in this case the master does acknowledge register "read only" and "read and write", and the the data byte output and the STA013 continues to useful size of the register itself. output the next byte in sequence. Each register is 8 bit wide. The master shall oper- To terminate the streams of bytes the master ate reading or writing on 8 bits only. does not acknowledge the last received byte, but I2C REGISTERS HEX_COD DEC_COD DESCRIPTION RESET R/W $00 0 VERSION R (8) $01 1 IDENT 0xAC R (8) $05 5 PLLCTL [7:0] 0xA1 R/W (8) $06 6 PLLCTL [20:16] (MF[4:0]=M) 0x0C R/W (8) $07 7 PLLCTL [15:12] (IDF[3:0]=N) 0x00 R/W (8) $0B 11 reserved $0C 12 REQ_POL 0x01 R/W (8) $0D 13 SCLK_POL 0x04 R/W (8) $0F 15 ERROR_CODE 0x00 R (8) $10 16 SOFT_RESET 0x00 W (8) $13 19 PLAY 0x01 R/W(8) $14 20 MUTE 0x00 R/W(8) $16 22 CMD_INTERRUPT 0x00 R/W(8) $18 24 DATA_REQ_ENABLE 0x00 R/W(8) $40 64 SYNCSTATUS 0x00 R (8) $41 65 ANCCOUNT_L 0x00 R (8) $42 66 ANCCOUNT_H 0x00 R (8) 11/38,

I2C REGISTERS (continued)

HEX_COD DEC_COD DESCRIPTION RESET R/W $43 67 HEAD_H[23:16] 0x00 R(8) $44 68 HEAD_M[15:8] 0x00 R(8) $45 69 HEAD_L[7:0] 0x00 R(8) $46 70 DLA 0x00 R/W (8) $47 71 DLB 0xFF R/W (8) $48 72 DRA 0x00 R/W (8) $49 73 DRB 0xFF R/W (8) $50 80 MFSDF_441 0x00 R/W (8) $51 81 PLLFRAC_441_L 0x00 R/W (8) $52 82 PLLFRAC_441_H 0x00 R/W (8) $54 84 PCM DIVIDER 0x03 R/W (8) $55 85 PCMCONF 0x21 R/W (8) $56 86 PCMCROSS 0x00 R/W (8) $59 89 ANC_DATA_1 [7:0] 0x00 R (8) $5A 90 ANC_DATA_2 [15:8] 0x00 R (8) $5B 91 ANC_DATA_3 [23:16] 0x00 R (8) $5C 92 ANC_DATA_4 [31:24] 0x00 R (8) $5D 93 ANC_DATA_5 [39:32] 0x00 R (8) $61 97 MFSDF (X) 0x07 R/W (8) $63 99 DAC_CLK_MODE 0x00 R/W (8) $64 100 PLLFRAC_L 0x46 R/W (8) $65 101 PLLFRAC_H 0x5B R/W (8) $67 103 FRAME_CNT_L 0x00 R (8) $68 104 FRAME_CNT_M 0x00 R (8) $69 105 FRAME_CNT_H 0x00 R (8) $6A 106 AVERAGE_BITRATE 0x00 R (8) $71 113 SOFTVERSION R (8) $72 114 RUN 0x00 R/W (8) $77 119 TREBLE_FREQUENCY_LOW 0x00 R/W (8) $78 120 TREBLE_FREQUENCY_HIGH 0x00 R/W (8) $79 121 BASS_FREQUENCY_LOW 0x00 R/W (8) $7A 122 BASS_FREQUENCY_HIGH 0x00 R/W (8) $7B 123 TREBLE_ENHANCE 0x00 R/W (8) $7C 124 BASS_ENHANCE 0x00 R/W (8) $7D 125 TONE_ATTEN 0x00 R/W (8) Note: 1) The HEX_COD is the hexadecimal adress that the microcontroller has to generate to access the information. 2) RESERVED: register used for production test only, or for future use. 12/38, 4.1 - STA013 REGISTERS DESCRIPTION MSB LSB The STA013 device includes 128 I2C registers. In b7 b6 b5 b4 b3 b2 b1 b0 this document, only the user-oriented registers XTO_ XTOD OCLK SYS2O PPLD XTI2DS XTI2O UPD_F are described. The undocumented registers are BUF IS EN CLK IS PCLK CLK RAC reserved. These registers must never be ac- UPD_FRAC: when is set to 1, update FRAC in cessed (in Read or in Write mode). The Read- the switching circuit. It is set to 1 after autoboot. Only registers must never be written. XTI2OCLK: The following table describes the meaning of the when is set to 1, use the XTI as input 2 of the divider X instead of VCO output. It is set toabbreviations used in theICregisters descrip- 0 on HW reset. tion: XTI2DSPCLK: when is to 1, set use the XTI as in- Symbol Comment put of the divider S instead of VCO output. It is NA Not Applicable set to 0 on HW reset. UND Undefined PLLDIS: when set to 1, the VCO output is dis- abled. It is set to 0 on HW reset. NC No Charge SYS2OCLK: when is set to 1, the OCLK fre- RO Read Only quency is equal to the system frequency. It is WO Write Only useful for testing. It is set to 0 on HW reset. R/W Read and Write OCLKEN: when is set to 1, the OCLK pad is en- R/WS Read, Write in specific mode able as output pad. It is set to 1 on HW reset. XTODIS: when is set to 1, the XTO pad is dis- VERSION able. It is set to 0 on HW reset. Address: 0x00 XTO_BUF: when this bit is set, the pin nr. 28(OUT_CLOCK/DATA_REQ) is enabled. It is set Type: RO to 0 after autoboot. MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 PLLCTL (M) V8 V7 V6 V5 V4 V3 V2 V1 Address: 0x06 The VERSION register is read-only and it is used Type: R/W to identify the IC on the application board. Software Reset: 0x0C Hardware Reset: 0x0C

IDENT

Address: 0x01 PLLCTL (N) Type: RO Address: 0x07 Software Reset: 0xAC Type: R/W Hardware Reset: 0xAC Software Reset: 0x00 MSB LSB Hardware Reset: 0x00 b7 b6 b5 b4 b3 b2 b1 b0 The M and N registers are used to configure the STA013 PLL by DSP embedded software. 10101100Mand N registers are R/W type but they are IDENT is a read-only register and is used to iden- completely controlled, on STA013, by DSP soft- tify the IC on an application board. IDENT always ware. has the value "0xAC" REQ_POL PLLCTL Address: 0x0C Address: 0x05 Type: R/W Type: R/W Software Reset: 0x01 Software Reset: 0x21 Hardware Reset: 0x00 Hardware Reset: 0x21 13/38, Hardware Reset: 0x01 ERROR_CODE register contains the last error The REQ_POL registers is used to program the occourred if any. The codes can be as follows: polarity of the DATA_REQ line. Code Description MSB LSB (1) 0x00 No error since the last SW or HW Reset b7 b6 b5 b4 b3 b2 b1 b0 (2) 0x01 CRC Failure00000001(3) 0x02 DATA not available Default polarity (the source sends data when the SOFT_RESET DATA_REQ line is high) Address: 0x10 MSB LSB Type: WO b7 b6 b5 b4 b3 b2 b1 b0 Software Reset: 0x0000000101Hardware Reset: 0x00 Inverted polarity (the source sends data when the DATA_REQ line is low) MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 SCKL_POLXXXXXXX0Address: 0x0D 1 Type: R/W X = don’t care; 0 = normal operation; 1 = reset Software Reset: 0x04 When this register is written, a soft reset occours. Hardware Reset: 0x04 The STA013 core command register and the in- terrupt register are cleared. The decoder goes in MSB LSB to idle mode. b7 b6 b5 b4 b3 b2 b1 b0XXXXX000(1)

PLAY

100(2) Address: 0x13 X = don’t care Type: R/W SCKL_POL is used to select the working polarity Software Reset: 0x01 of the Input Serial Clock (SCKR). Hardware Reset: 0x01 (1) If SCKL_POL is set to 0x00, the data (SDI) are sent with the falling edge of SCKR MSB LSB and sampled on the rising edge. b7 b6 b5 b4 b3 b2 b1 b0 (2) If SCKL_POL is set to 0x04, the data (SDI) are sent with the rising edge of SCKR andXXXXXXX0sampled on the falling edge. 1 X = don’t care; 0 = normal operation; 1 = play ERROR_CODE Address: 0x0F The PLAY command is handled according to the Type: RO state of the decoder, as described in section 2.5. PLAY only becomes active when the decoder is Software Reset: 0x00 in DECODE mode. Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0XXXX0000(1) 0001(2) 0010(3) X = don’t care 14/38, MUTE CMD_INTERRUPT Address: 0x14 Address: 0x16 Type: R/W Type: R/W Software Reset: 0x00 Software Reset: 0x00 Hardware Reset: 0x00 Hardware Reset: 0x00 MSB LSB MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0XXXXXXX0XXXXXXX011X= don’t care; 0 = normal operation; 1 = mute X = don’t care; 0 = normal operation; 1 = write into I2C/Ancillary Data The MUTE command is handled according to the state of the decoder, as described in section 2.5. The INTERRUPT is used to give STA013 the command to write into the I2C/Ancillary Data MUTE sets the clock running. Buffer (Registers: 0x59 ... 0x5D). Every time the Master has to extract the new buffer content (5 bytes) it writes into this register, setting it to a non-zero value. DATA_REQ_ENABLE Address: 0x18 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 DescriptionXXXXX0XXbuffered output clockXXXXX1XXrequest signal The DATA_REQ_ENABLE register is used to mode. configure Pin n. 28 working as buffered output The buffered Output Clock has the same fre- clock or data request signal, used for multimedia quency than the input clock (XTI)

SYNCSTATUS

Address: 0x40 Type: RO Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 DescriptionXXXXXXSS1 SS000Research of sync word01Wait for Confirmation10Synchronised11not used 15/38, ANCCOUNT_L HEAD_M[15:8] Address: 0x41 MSB LSB Type: RO b7 b6 b5 b4 b3 b2 b1 b0 Software Reset: 0x00 H15 H14 H13 H12 H1‘1 H10 H9 H8 Hardware Reset: 0x00 MSB LSB HEAD_L[7:0] b7 b6 b5 b4 b3 b2 b1 b0 MSB LSB AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 b7 b6 b5 b4 b3 b2 b1 b0 H7 H6 H5 H4 H3 H2 H1 H0 ANCCOUNT_H Address: 0x43, 0x44, 0x45 Address: 0x42 Type: RO Type: RO Software Reset: 0x00 Software Reset: 0x00 Hardware Reset: 0x00 Hardware Reset: 0x00 Head[1:0] emphasis ANCCOUNT_H Head[2] original/copy MSB LSB Head[3] copyrightHead b7 b6 b5 b4 b3 b2 b1 b0 [5:4] mode extension AC15 AC14 AC13 AC12 AC11 AC10 AC9 AC8 Head[7:6] mode Head[8] private bit ANCCOUNT registers are logically concatenated Head[9] padding bit and indicate the number of Ancillary Data bits Head[11:10] sampling frequency index available at every correctly decoded MPEG frame. Head[15:12] bitrate index Head[16] protection bit HEAD_H[23:16] Head[18:17] layer Head[19] ID MSB LSB Head[20] ID_ex b7 b6 b5 b4 b3 b2 b1 b0XXXH20 H19 H18 H17 H16 The HEAD registers can be viewed as logically concatenated to store the MPEG Layer III Header x = don’t care content. The set of three registers is updated every time the synchronisation to the new MPEG frame is achieved 16/38, The meaning of the flags are shown in the follow- Padding bit ing tables: if this bit equals ’1’, the frame contains an addi- MPEG IDs tional slot to adjust the mean bitrate to the sam- pling frequency, otherwise this bit is set to ’0’. IDex ID00MPEG 2.5 Private bit01reserved Bit for private use. This bit will not be used in the10MPEG 2 future by ISO/IEC. 1 1 MPEG 1 Mode Layer Indicates the mode according to the following ta- in Layer III these two flags must be set always to ble. The joint stereo mode is intensity_stereo "01". and/or ms_stereo. Protection_bit mode mode specified It equals "1" if no redundancy has been added ’00’ stereo and "0" if redundancy has been added. ’01’ joint stereo (intensity_stereo and/or ms_stereo) Bitrate_index ’10’ dual_channel indicates the bitrate (Kbit/sec) depending on the ’11’ single_channel (mono) MPEG ID. Mode extension bitrate index ID = 1 ID = 0 These bits are used in joint stereo mode. They in- ’0000’ free free dicates which type of joint stereo coding method ’0001’ 32 8 is applied. The frequency ranges, over which the intensity_stereo and ms_stereo modes are ap- ’0010’ 40 16 plied, are implicit in the algorithm. ’0011’ 48 24 ’0100’ 56 32 Copyright ’0101’ 64 40 ’0110’ 80 48 If this bit is equal to ’0’, there is no copyright onthe bitstream, ’1’ means copyright protected. ’0111’ 96 56 ’1000’ 112 64 Original/Copy ’1001’ 128 80 This bit equals ’0’ if the bitstream is a copy, ’1’ if it ’1010’ 160 96 is original. ’1011’ 192 112 ’1100’ 224 128 Emphasis ’1101’ 256 144 Indicates the type of de-emphasis that shall be ’1110’ 320 160 used. ’1111’ forbidden forbidden Sampling Frequency emphasis emphasis specified indicates the sampling frequency of the encoded ’00’ none audio signal (KHz) depending on the MPEG ID ’01’ 50/15 microseconds ’10’ reserved Sampling Frequency MPEG1 MPEG2 MPEG2.5 ’11’ CCITT J,17 ’00’ 44.1 22.05 11.03 ’01’ 48 24 12 ’10’ 32 16 8 ’11’ reserved reserved reserved 17/38,

DLA

Address: 0x46 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description DLA7 DLA6 DLA5 DLA4 DLA3 DLA2 DLA1 DLA0 OUTPUT ATTENUATION00000000NO ATTENUATION00000001-1dB00000010-2dB : : : : : : : : : 01100000-96dB DLA register is used to attenuate the level of 255 (0xFF), the maximum attenuation is audio output at the Left Channel using the butter- achieved. fly shown in Fig. 12. When the register is set to A decimal unit correspond to an attenuation step of 1 dB. Figure 12. Volume Control and Output Setup

DLA

DSP Left Channel Output Left Channel X +

DLB X DRB X DRA

Output Right Channel X + DSP Right Channel D97AU667

DLB

Address: 0x47 Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description DLB7 DLB6 DLB5 DLB4 DLB3 DLB2 DLB1 DLB0 OUTPUT ATTENUATION00000000NO ATTENUATION00000001-1dB00000010-2dB : : : : : : : : : 01100000-96dB DLB register is used to re-direct the Left Channel Default value is 0x00, corresponding at the maxi- on the Right, or to mix both the Channels. mum attenuation in the re-direction channel. 18/38,

DRA

Address: 0x48 Type: R/W Software Reset: 0X00 Hardware Reset: 0X00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description DRA7 DRA6 DRA5 DRA4 DRA3 DRA2 DRA1 DRA0 OUTPUT ATTENUATION00000000NO ATTENUATION00000001-1dB00000010-2dB : : : : : : : : : 01100000-96dB DRA register is used to attenuate the level of 255 (0xFF), the maximum attenuation is audio output at the Right Channel using the but- achieved. terfly shown in Fig. 11. When the register is set to A decimal unit correspond to an attenuation step of 1 dB.

DRB

Address: 0x49 Type: R/W Software Reset: 0xFF Hardware Reset: 0xFF MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description DRB7 DRB6 DRB5 DRB4 DRB3 DRB2 DRB1 DRB0 OUTPUT ATTENUATION00000000NO ATTENUATION00000001-1dB00000010-2dB : : : : : : : : : 01100000-96dB DRB register is used to re-direct the Right Chan- Default value is 0x00, corresponding at the maxi- nel on the Left, or to mix both the Channels. mum attenuation in the re-direction channel. MFSDF_441 The VCO output frequency, when decoding Address: 0x50 44.1KHz bitstream, is divided by (MFSDF_441 +1) Type: R/W Software Reset: 0x00 PLLFRAC_441_L Hardware Reset: 0x00 Address: 0x51 Type: R/W MSB LSB Software Reset: 0x00 b7 b6 b5 b4 b3 b2 b1 b0 Hardware Reset: 0x00XXXM4 M3 M2 M1 M0 MSB LSB This register contains the value for the PLL X b7 b6 b5 b4 b3 b2 b1 b0 driver for the 44.1KHz reference frequency. PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 19/38, PLLFRAC_441_H PCMDIVIDER Address: 0x52 Address: 0x54 Type: R/W Type: RW Software Reset: 0x00 Software Reset: 0x03 Hardware Reset: 0x00 Hardware Reset: 0x03 MSB LSB76543210b7 b6 b5 b4 b3 b2 b1 b0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 PF15 PF14 PF13 PF12 PF11 PF10 PF9 PF8 PCMDIVIDER is used to set the frequency ratio The registers are considered logically concate- between the OCLK (Oversampling Clock for nated and contain the fractional values for the DACs), and the SCKT (Serial Audio Transmitter PLL, for 44.1KHz reference frequency. Clock). (see also PLLFRAC_L and PLLFRAC_H regis- The relation is the following: ters) OCLK_freq SCKT_freq = 2 (1 + PCM_DIV) The Oversampling Factor (O_FAC) is related to OCLK and SCKT by the following expression: 1) OCLK_freq = O_FAC * LRCKT_ Freq (DAC relation) 2) OCLK_ Freq = 2 * (1+PCM_DIV) * 32* LRCKT_Freq (when 16 bit PCM mode is used) 3) OCLK_ Freq = 2 * (1+PCM_DIV) * 64* LRCKT_Freq (when 32 bit PCM mode is used) 4) PCM_DIV = (O_FAC/64) - 1 in 16 bit mode 5) PCM_DIV = (O_FAC/128) - 1 in 32 bit mode Example for setting: MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD00000011116 bit mode 512 x Fs0000010116 bit mode 384 x Fs0000001116 bit mode 256 x Fs0000001132 bit mode 512 x Fs0000001032 bit mode 384 x Fs0000000132 bit mode 256 x Fs for 16 bit PCM Mode for 32 bit PCM Mode O_FAC = 512 ; PCM_DIV = 7 O_FAC = 512 ; PCM_DIV = 3 O_FAC = 256 ; PCM_DIV = 3 O_FAC = 256 ; PCM_DIV = 1 O_FAC = 384 ; PCM_DIV = 5 O_FAC = 384 ; PCM_DIV = 2 20/38,

PCMCONF

Address: 0x55 Type: R/W Software Reset: 0x21 Hardware Reset: 0x21 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Description X ORD DIF INV FOR SCL PREC (1) PREC (1) X 1 PCM order the LS bit is transmitted FirstX0PCM order the MS bit is transmitted FirstX0The word is right paddedX1The word is left paddedX1LRCKT Polarity compliant to I2S formatX0LRCKT Polarity invertedX0I2S formatX1Different formatsX1Data are sent on the rising edge of SCKTX0Data are sent on the falling edge of SCKTX0016 bit mode (16 slots transmitted) X0118 bit mode (18 slots transmitted) X1020 bit mode (20 slots transmitted) X1124 bit mode (24 slots transmitted) PCMCONF is used to set the PCM Output Inter- rising edge of SCKT and sampled on the falling. If face configuration: set to ’0’ , the data are sent on the falling edge and sampled on the rising. This last option is the ORD: PCM order. If this bit is set to’1’, the LS Bit most commonly used by the commercial DACs. is transmitted first, otherwise MS Bit is transmiited The default configuration for this flag is ’0’. first. DIF: PCM_DIFF. It is used to select the position Figure 14. SCKT Polarity Selection of the valid data into the transmitted word. This setting is significant only in 18/20/24 bit/word

SCKT

mode.If it is set to ’0’ the word is right-padded, otherwise it is left-padded. SDO INV (fig.13): It is used to select the LRCKT clock INV_SCLK=0 polarity. If it is set to ’1’ the polarity is compliant to I2S format (low -> left , high -> right), otherwise the LRCKT is inverted. The default value is ’0’. (if SCKT I2S have to be selected, must be set to ’1’ in the SDO STA013 configuration phase). INV_SCLK=1 Figure 13. LRCKT Polarity Selection PREC [1:0]: PCM PRECISION left left It is used to select the PCM samples precision, as LRCKT right INV_LRCLK=0 follows: right ’00’: 16 bit mode (16 slots transmitted) LRCKT left left INV_LRCLK=1 ’01’: 18 bit mode (32 slots transmitted) ’10’: 20 bit mode (32 slots transmitted) FOR: FORMAT is used to select the PCM Output ’11’: 24 bit mode (32 slots transmitted) Interface format. After hw and sw reset the value is set to 0 corre- The PCM samples precision in STA013 can be sponding to I2S format. 16 or 18-20-24 bits. SCL (fig.14): used to select the Transmitter Serial When STA013 operates in 16 (18-20-24) bits Clock polarity. If set to ’1’ the data are sent on the mode, the number of bits transmitted during aLRCLT period is 32 (64). 21/38,

PCMCROSS

Address: 0x56 Type: R/W Software Reset: 0x00 Hardware Reset: 0x00 MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 DescriptionXXXXXX00Left channel is mapped on the left output. Right channel is mapped on the Right outputXXXXXX01Left channel is duplicated on both Output channels. XXXXXX10Right channel is duplicated on both Output channelsXXXXXX11Right and Left channels are toggled The default configuration for this register is ’0x00’. ANCILLARY DATA BUFFER The value is changed by the internal STA013 Core, to set the clocks frequencies, according to Address: 0x59 - 0x5D the incoming bitstream. This value can be even set by the user to select the PCM interface con- Type: RO figuration. Software Reset: 0x00 The VCO output frequency is divided by (X+1). Hardware Reset: 0x00 This register is a reference for 32KHz and 48 KHz input bitstream. STA013 can extract max 56 bytes/MPEG frame. To know the number of A.D. bits available every MPEG frame, the ANCCOUNT_L and ANC- DAC_CLK_MODE COUNT_H registers (0x41 and 0x42) have to be read. Address: 0x63 The buffer dimension is 5 bytes, written by Type: RW STA013 core in sequential order. The timing in- formation to read the buffer can be obtained by Software Reset: 0x00 reading the FRAME_CNT registers (0x67 - 0x69). Hardware Reset: 0x00 To fill up the buffer with a new 5-bytes slot, the STA013 waits until a CMD_INTERRUPT register MSB LSB is written by the master. b7 b6 b5 b4 b3 b2 b1 b0XXXXXXXMODE MFSDF (X) This register is used to select the operating mode for OCLK clock signal. Address: 0x61 If it is set to ’1’, the OCLK frequency is fixed, and Type: R/W it is mantained to the value fixed by the user even Software Reset: 0x07 if the sampling frequency of the incoming bit-stream changes. Hardware Reset: 0x07 It the MODE flag is set to ’0’, the OCLK frequency MSB LSB changes, and can be set to (512, 384, 256) * Fs. The default configuration for this mode is 256 * b7 b6 b5 b4 b3 b2 b1 b0 Fs. XXXM4 M3 M2 M1 M0 When this mode is selected, the default OCLK The register contains the values for PLL X divider frequency is 12.288 MHz. (see Fig. 7). 22/38, PLLFRAC_L ([7:0]) FRAME_CNT_H MSB LSB MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 PF7 PF6 PF5 PF4 PF3 PF2 PF1 PF0 FC23 FC22 FC21 FC20 FC19 FC18 FC17 FC016 PLLFRAC_H ([15:8]) Address: 0x67, 0x68, 0x69 MSB LSB Type: RO b7 b6 b5 b4 b3 b2 b1 b0 Software Reset: 0x00 PF15 PF14 PF13 PF12 PF11 PF10 PF9 PF8 Hardware Reset: 0x00 Address: 0x64 - 0x65 The three registers are considered logically con-catenated and compose the Global Frame Type: R/W Counter as described in the table. Software Reset: 0x46 | 0x5B It is updated at every decoded MPEG Frame. Hardware Reset: 0xNA | 0x5B The registers are reset on both hardware and software reset. The registers are considered logically concate- nated and contain the fractional values for the AVERAGE_BITRATE PLL, used to select the internal configuration. After Reset, the values are NA, and the opera- Address: 0x6A tional setting are done when the MPEG synchro- Type: RO nisation is achieved. Software Reset: 0x00 The following formula describes the relationships among all the STA013 fractional PLL parameters: Hardware Reset: 0x00 MSB LSB 1 MCLK_freq OCLK_Freq = ⋅ ⋅ + + FRACM1b7 b6 b5 b4 b3 b2 b1 b0 X + 1 N + 1 65536 AB7 AB6 AB5 AB4 AB3 AB2 AB1 AB0 where: AVERAGE_BITRATE is a read-only register and FRAC=256 x FRAC_H + FRAC_L (decimal) it contains the average bitrate of the incoming bit- stream. The value is rounded with an accuracy of These registers are a reference for 48 / 24 / 12 / 1 Kbit/sec. 32 / 16 / 8KHz audio.

SOFTVERSION

FRAME_CNT_L MSB LSB Address: 0x71 b7 b6 b5 b4 b3 b2 b1 b0 Type: RO FC7 FC6 FC5 FC4 FC3 FC2 FC1 FC0 MSB LSB FRAME_CNT_M b7 b6 b5 b4 b3 b2 b1 b0 MSB LSB SV7 SV6 SV5 SV4 SV3 SV2 SV1 SV0 b7 b6 b5 b4 b3 b2 b1 b0 After the STA013 boot, this register contains the FC15 FC14 FC13 FC12 FC11 FC10 FC9 FC8 version code of the embedded software. 23/38, RUN BASS_FREQUENCY_LOW Address: 0x72 Address: 0x79 Type: RW Software Reset: 0x00 Software Reset: 0x00 Hardware Reset: 0x00 Hardware Reset: 0x00 MSB LSB MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 b7 b6 b5 b4 b3 b2 b1 b0 BF7 BF6 BF5 BF4 BF3 BF2 BF1 BF0XXXXXXXRUN BASS_FREQUENCY_HIGH Setting this register to 1, STA013 leaves the idle state, starting the decoding process. The Microcontroller is allowed to set the RUN Address: 0x7A flag, once all the control registers have been in- Software Reset: 0x00 itialized. Hardware Reset: 0x00 TREBLE_FREQUENCY_LOW MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 Address: 0x77 BF15 BF14 BF13 BF12 BF11 BF10 BF9 BF8 Type: RW Software Reset: 0x00 The registers BASS_FREQUENCY_HIGH and Hardware Reset: 0x00 BASS_FREQUENCY_LOW, logically concate-nated as a 16 bit wide register, are used to select MSB LSB the frequency, in Hz, where the selected fre- quency is -12dB respect to the pass-band. By b7 b6 b5 b4 b3 b2 b1 b0 setting the BASS_FREQUENCY registers, the TF7 TF6 TF5 TF4 TF3 TF2 TF1 TF0 following rules must be kept: Bass_Freq <= Treble_Freq TREBLE_FREQUENCY_HIGH Bass_Freq > 0 Address: 0x78 (suggested range: 20 Hz < Bass_Freq < 750 Hz) Type: RW Example: Software Reset: 0x00 Bass = 200Hz Hardware Reset: 0x00 Treble = 3kHz MSB LSB b7 b6 b5 b4 b3 b2 b1 b0 TFS TF15 TF14 TF13 TF12 TF11 TF10 TF9 TF8 15 14 13 12 11 1098765432100000101110111000The registers TREBLE_FREQUENCY-HIGH and TREBLE_FREQUENCY-LOW, logically concate- nated as a 16 bit wide register, are used to select BFS the frequency, in Hz, where the selected fre- quency is +12dB respect to the stop band. 15 14 13 12 11 109876543210By setting these registers, the following rule must0000000011001000be kept: Treble_Freq < Fs/2 24/38, TREBLE_ENHANCE Signed number (2 complement) This register is used to select the enhancement Address: 0x7B or attenuation STA013 has to perform on Treble Frequency range at the digital signal. Software Reset: 0x00 A decrement (increment) of a decimal unit corre- Hardware Reset: 0x00 sponds to a step of attenuation (enhancement) of 1.5dB. MSB LSB The allowed Attenuation/Enhancement range is b7 b6 b5 b4 b3 b2 b1 b0 [-18dB, +18dB]. TE7 TE6 TE5 TE4 TE3 TE2 TE1 TE0 MSB LSB ENHANCE/ATTENUATION b7 b6 b5 b4 b3 b2 b1 b0 1.5dB step00001100+1800001011+16.500001010+1500001001+13.5 .00000001+100000000011111111-1 .11110111-13.511110110-1511110100-16.511110100-18 25/38, BASS_ENHANCE Signed number (2 complement) This register is used to select the enhancement Address: 0x7C or attenuation STA013 has to perform on Bass Software Reset: 0x00 Frequency range at the digital signal. Hardware Reset: 0x00 A decrement (increment) of a decimal unit corre- sponds to a step of attenuation (enhancement) of MSB LSB 1.5dB. b7 b6 b5 b4 b3 b2 b1 b0 The allowed Attenuation/Enhancement range is [-18dB, +18dB]. BE7 BE6 BE5 BE4 BE3 BE2 BE1 BE0 MSB LSB ENHANCE/ATTENUATION b7 b6 b5 b4 b3 b2 b1 b0 1.5dB step00001100+1800001011+16.500001010+1500001001+13.5 .00000001+100000000011111111-1 .11110111-13.511110110-1511110100-16.511110100-18 26/38, TONE_ATTEN In the digital output audio, the full signal is achieved with 0 dB of attenuation. For this rea- Address: 0x7D son, before applying Bass & Treble Control, the user has to set the TONE_ATTEN register to the Type: RW maximum value of enhancement is going to per- Software Reset: 0x00 form. Hardware Reset: 0x00 For example, in case ofa0dB signal (max. level) only attenuation would be possible. If enhance- MSB LSB ment is desired, the signal has to be attenuated b7 b6 b5 b4 b3 b2 b1 b0 accordingly before in order to reserve a margin in dB.An increment of a decimal unit corresponds to a Tone TA7 TA6 TA5 TA4 TA3 TA2 TA1 TA0 Attenuation step of 1.5dB. MSB LSB ATTENUATION b7 b6 b5 b4 b3 b2 b1 b0 -1.5dB step000000000dB00000001-1.5dB00001010-3dB00000011-4.5dB .00001010-15dB00001011-16.5dB00001100-18dB 5. GENERAL INFORMATION 5.1. MPEG 2.5 Layer III Algorithm. DEMULTIPLEXING INVERSEHUFFMAN & QUANTISATION

INVERSE

DECODING IMDCT& FILTERBANKERROR CHECK

DESCALING

SIDE INFORMATION STEREOPHONIC AUDIO DECODING SIGNAL (2*768Kbit/s) ANCILLARY DATA D98AU903 ENCODED AUDIO BITSTREAM (8Kbit/s ... 128Kbit/s) 5.2 - MPEG Ancillary Data Description: As specifyed in the ISO standard, the MPEG pling frequencies. The time duration of the Layer Layer III frames have a variable bit lenght, and III frames is shown in Tab 2. are constant in time depending on the audio sam- Table2: MPEG Layer III Frames Time Duration Sampling Frequency (KHz) 48 44.1 32 24 22.5 16 12 11.025 8 MPEG Frame Lenght (ms) 24 29 36 24 29 36 48 48 72 27/38, The Ancillary Data extraction on STA013 can be specific register, to require the new 5 byte slot to described as follow: STA003 is needed. STA013 has a specific Ancillary Data buffer, This register is: mapped into the I2C registers: 0x16 CMD_INTERRUPT 0x59 ANC_DATA_1 The interrupt register, is sensitive to any non-zero 0x5A ANC_DATA_2 value written by the Microcontroller. When this 0x5B ANC_DATA_3 register is updated the Ancillary Data buffer is 0x5C ANC_DATA_4 filled up with new values and the registers 0x5D ANC_DATA_5 0x41 ANCCOUNT_L 0x42 ANCCOUNT_H Since the content of Ancillary Data into an MPEG are updated (decremented) accordingly. Frame STA013 can extract is max. 56 bytes, a 5.3. I/O CELL DESCRIPTION 1) CMOS Tristate Output Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 9, 10, 11, 20, 28

EN

Z OUTPUT PIN MAX LOADAZ100pF D98AU904 2) CMOS Bidir Pad Buffer, 4mA, with Slew Rate Control / Pin numbers 3, 12

EN

IO OUTPUT CAPACITANCE OUTPUT MAX A PIN PIN LOAD IO 5pF IO 100pF

ZI

D98AU905 3) CMOS Inpud Pad Buffer / Pin numbers 4, 5, 6, 8, 21, 25AZINPUT PIN CAPACITANCE A 3.5pF D98AU906 4) CMOS Inpud Pad Buffer with Active Pull-Up / Pin numbers 7, 24, 26 INPUT PIN CAPACITANCEAZA3.5pF D98AU907 28/38, 5.4. TIMING DIAGRAMS 5.4.1. Audio DAC Interface a) OCLK in output. The audio PLL is used to clock the DAC OCLK (OUTPUT)

SDO

tsdo

SCKT

tsckt

LRCLK

tlrclk D98AU969 tsdo = 3.5 + pad_timing (Cload_SDO) - pad_timing Pad-timing versus load (Cload_ OCLK) Load (pF) Pad_timing tsckt = 4 + pad_timing (Cload_SCKT) - pad_timing 25 2.90ns (Cload_ OCLK) tlrckt = 3.5 + pad_timing (Cload_LRCCKT) - 50 3.82ns pad_timing (Cload_ OCLK) 75 4.68ns 100 5.52ns Cload_XXX is the load in pF on the XXX output. pad_timing (Cload_XXX) is the propagation delay added to the XXX pad due to the load. b) OCLK in input. t t OCLK (INPUT) hi lo

SDO

tsdo

SCKT

tsckt

LRCLK

tlrclk toclk D98AU970 Thi min = 3ns Tlo min = 3ns Toclk min = 25ns tsdo = 5.5 + pad_timing (Cload_SDO) ns tsckt = 6 + pad_timing (Cload_SCKT) ns tlrckt = 5.5 + pad_timing (Cload_LRCKT) ns 29/38, 5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 0 BIT_EN t_biten t_biten tsckr_min_period tsckr_min_low SCKR SCLK_POL=0 tsckr_min_high SDI IGNORED VALID IGNORED tsdi_setup tsdi_hold D98AU971A 5.4.2. Bitstream input interface (SDI, SCKR, BIT_EN) SCL_POL = 1 BIT_EN t_biten t_biten tsckr_min_period tsckr_min_low SCKR SCLK_POL=4 tsckr_min_high SDI IGNORED IGNORED VALID IGNORED tsdi_setup tsdi_hold D99AU1038 tsdi_setup_min = 2ns tsdi_hold_min = 3ns tsckr_min_hi = 10ns tsckr_min_low = 10ns tsckr_min_lperiod = 50ns t_biten (min) = 2ns 5.4.3. SRC_INT

This is an asynchronous input used in "broadcast’ mode. SRC_INT is active low

t t SRC_INT _src_hi _src_low D98AU972 t_src_low min duration is 50ns (1DSP clock period) t_src_high min duration is 50ns (1DSP clock period) 5.4.4. XTI,XTO and CLK_OUT timingsttXTI (INPUT) hi lo

XTO

txto CLK_OUT tclk_out D98AU973 txto = 1.40 + pad_timing (Cload_XTO) ns tclk_out = 4 + pad_timing (Cload_CLK_OUT) ns Note: In "multimedia" mode, the CLK_OUT pad is DATA_REQ. In that case, no timing is given between the XTI input and this pad. 30/38, 5.4.5. RESET

The Reset min duration (t_reset_low_min) is 100ns RESET

treset_low_min D98AU974 5.5. CONFIGURATION FLOW HW RESET set PCM-DIVIDER PCM OUTPUT

INTERFACE

CONFIGURATION THE OVERALL set PCM-CONF. SETTING STEPS ARE INCLUDED IN THE STA013

CONFIGURATION

set { PLL FRAC_441_H, FILE AND CAN PLL FRAC_441_L, BE DOWNLOADEDPLL PLL FRAC_H, IN ONE STEP.CONFIGURATION PLL FRAC_L } STM PROVIDESFOR: A SPECIFIC • { 48, 44.1, 32 CONFIGURATION set { MFS DF_441, 29, 22.05, 16 FILE FOR EACH MFSDF } 12, 11.025, 8 } KHz SUPPORTED INPUT CLOCK • MULTIMEDIA FREQUENCY MODE see set PLL CTRL {TAB 5 to TAB12} INPUT SERIAL CLOCK POLARITY set SCLK_POL CONFIGURATION DATA REQUEST set DATA_REQ_ENABLE PIN ENABLE DATA REQUEST

POLARITY

set REQ_POL CONFIGURATION set RUN D98AU975 31/38, Table 5: Table 7: PLL Configuration Sequence For PLL Configuration Sequence For 10MHz Input Clock 14.31818MHz Input Clock 256 Oversapling Clock 256 Oversapling Rathio REGISTER NAME VALUE REGISTER NAME VALUE ADDRESS ADDRESS 6 reserved 18 6 reserved 12 11 reserved 3 11 reserved 3 97 MFSDF (x) 15 97 MFSDF (x) 15 80 MFSDF-441 16 80 MFSDF-441 16 101 PLLFRAC-H 169 101 PLLFRAC-H 187 82 PLLFRAC-441-H 49 82 PLLFRAC-441-H 103 100 PLLFRAC-L 42 100 PLLFRAC-L 58 81 PLLFRAC-441-L 60 81 PLLFRAC-441-L 119 5 PLLCTRL 161 5 PLLCTRL 161 Table 6: Table 8: PLL Configuration Sequence For PLL Configuration Sequence For 10MHz Input Clock 14.31818MHz Input Clock 384 Oversapling Rathio 384 Oversapling Rathio REGISTER NAME VALUE REGISTER NAME VALUE ADDRESS ADDRESS 6 reserved 17 6 reserved 11 11 reserved 3 11 reserved 3 97 MFSDF (x) 9 97 MFSDF (x) 6 80 MFSDF-441 10 80 MFSDF-441 7 101 PLLFRAC-H 110 101 PLLFRAC-H 3 82 PLLFRAC-441-H 160 82 PLLFRAC-441-H 157 100 PLLFRAC-L 152 100 PLLFRAC-L 211 81 PLLFRAC-441-L 186 81 PLLFRAC-441-L 157 5 PLLCTRL 161 5 PLLCTRL 161 32/38, Table 9: Table 11: PLL Configuration Sequence For PLL Configuration Sequence For 14.31818MHz Input Clock 14.7456MHz Input Clock 512 Oversapling Rathio 384 Oversapling Rathio REGISTER NAME VALUE REGISTER NAME VALUE ADDRESS ADDRESS 6 reserved 11 6 reserved 10 11 reserved 3 11 reserved 3 97 MFSDF (x) 6 97 MFSDF (x) 8 80 MFSDF-441 7 80 MFSDF-441 9 101 PLLFRAC-H 3 101 PLLFRAC-H 64 82 PLLFRAC-441-H 157 82 PLLFRAC-441-H 124 100 PLLFRAC-L 211 100 PLLFRAC-L 0 81 PLLFRAC-441-L 157 81 PLLFRAC-441-L05PLLCTRL 161 5 PLLCTRL 161 Table 10: Table 12: PLL Configuration Sequence For PLL Configuration Sequence For 14.7456MHz Input Clock 14.7456MHz Input Clock 256 Oversapling Rathio 512 Oversapling Rathio REGISTER NAME VALUE REGISTER NAME VALUE ADDRESS ADDRESS 6 reserved 12 6 reserved 9 11 reserved 3 11 reserved 2 97 MFSDF (x) 15 97 MFSDF (x) 5 80 MFSDF-441 16 80 MFSDF-441 6 101 PLLFRAC-H 85 101 PLLFRAC-H 0 82 PLLFRAC-441-H 4 82 PLLFRAC-441-H 184 100 PLLFRAC-L 85 100 PLLFRAC-L 0 81 PLLFRAC-441-L 0 81 PLLFRAC-441-L05PLLCTRL 161 5 PLLCTRL 161 33/38, 5.6. STA013 CONFIGURATION FILE FORMAT The STA013 Configuration File is an ASCII format. An example of the file format is the following: 58 1 42 4 128 15 ... It is a sequence of rows and each one can be interpreted as an I2C command. The first part of the row is the I2C address (register) and the second one is the I2C data (value). To download the STA013 configuration file into the device, a sequence of write operation to STA013 I2C interface must be performed. The following program describes the I2C routine to be implemented for the configuration driver: 42 4 I2C REGISTER VALUE I2C SUB-ADDRESS D98AU976 STA013 Configuration Code (pseudo code) download cfg - file { fopen (cfg_file); fp:=1; /*set file pointer to first row */ do { I2C_start_cond; /* generate I2C start condition for STA013 device address */ I2C_write_dev_addr; /* write STA013 device address */ I2C_write_subaddress (fp); /* write subaddress */ I2C_write_data (fp); /* write data */ I2C_stop_cond; /* generate I2C stop condition */ fp++; /* update pointer to new file row */ } while (!EDF) /* repeat until End of File */ } /* End routine */ Note:1 STA013 is a device based on an integrated DSP core. Some of the I2C registers default values are loaded after an internal DSP boot operation. The bootstrap time is 60 micro second. Only after this time lenght, the data in the register can be considered stable. Note 2: Refer also to the application note 1090 34/38, mm inch DIM. OUTLINE AND MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA A 2.65 0.104 a1 0.1 0.3 0.004 0.012 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 C 0.5 0.020 c1 45° (typ.) D 17.7 18.1 0.697 0.713 E 10 10.65 0.394 0.419 e 1.27 0.050 e3 16.51 0.65 F 7.4 7.6 0.291 0.299 L 0.4 1.27 0.016 0.050 SO28S8° (max.) 35/38, mm inch DIM. OUTLINE AND MIN. TYP. MAX. MIN. TYP. MAX.

MECHANICAL DATA

A 1.60 0.063 A1 0.05 0.15 0.002 0.006 A2 1.35 1.40 1.45 0.053 0.055 0.057 B 0.30 0.37 0.45 0.012 0.015 0.018 C 0.09 0.20 0.004 0.008 D 11.80 12.00 12.20 0.464 0.472 0.480 D1 9.80 10.00 10.20 0.386 0.394 0.401 D3 8.00 0.315 E 11.80 12.00 12.20 0.464 0.472 0.480 E1 9.80 10.00 10.20 0.386 0.394 0.401 E3 8.00 0.315 e 0.80 0.031 L 0.45 0.60 0.75 0.018 0.024 0.030 L1 1.00 0.039 TQFP44 (10 x 10 x 1.4mm) k 0˚(min.), 3.5˚(typ.), 7˚(max.)

D

D1

A

A2 A1 33 23 34 22 0.10mm .004 Seating Plane 44 12 1 11

C

e

K

TQFP4410 0076922 D 36/38

B

E1

E L B

, mm inch DIM. OUTLINE AND MIN. TYP. MAX. MIN. TYP. MAX. MECHANICAL DATA A 1.700 0.067 A1 0.350 0.400 0.450 0.014 0.016 0.018 A2 1.100 0.043 b 0.500 0.20 D 8.000 0.315 D1 5.600 0.220 e 0.800 0.031 Body: 8x8x1.7mm E 8.000 0.315 E1 5.600 0.220

LFBGA64

f 1.200 0.047 BALL 1 IDENTIFICATION 0.15

A

D1 f DA187654321f

A B C D

E1 E

E F G H

φ b (64 PLACES) e A2 LFBGA64M 37/38, Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners © 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia – Belgium - Brazil - Canada - China – Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 38/38]

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